1 /* 2 * Arm IoT Kit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qapi/error.h" 15 #include "trace.h" 16 #include "hw/sysbus.h" 17 #include "hw/registerfields.h" 18 #include "hw/arm/iotkit.h" 19 #include "hw/misc/unimp.h" 20 #include "hw/arm/arm.h" 21 22 /* Create an alias region of @size bytes starting at @base 23 * which mirrors the memory starting at @orig. 24 */ 25 static void make_alias(IoTKit *s, MemoryRegion *mr, const char *name, 26 hwaddr base, hwaddr size, hwaddr orig) 27 { 28 memory_region_init_alias(mr, NULL, name, &s->container, orig, size); 29 /* The alias is even lower priority than unimplemented_device regions */ 30 memory_region_add_subregion_overlap(&s->container, base, mr, -1500); 31 } 32 33 static void init_sysbus_child(Object *parent, const char *childname, 34 void *child, size_t childsize, 35 const char *childtype) 36 { 37 object_initialize(child, childsize, childtype); 38 object_property_add_child(parent, childname, OBJECT(child), &error_abort); 39 qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); 40 } 41 42 static void irq_status_forwarder(void *opaque, int n, int level) 43 { 44 qemu_irq destirq = opaque; 45 46 qemu_set_irq(destirq, level); 47 } 48 49 static void nsccfg_handler(void *opaque, int n, int level) 50 { 51 IoTKit *s = IOTKIT(opaque); 52 53 s->nsccfg = level; 54 } 55 56 static void iotkit_forward_ppc(IoTKit *s, const char *ppcname, int ppcnum) 57 { 58 /* Each of the 4 AHB and 4 APB PPCs that might be present in a 59 * system using the IoTKit has a collection of control lines which 60 * are provided by the security controller and which we want to 61 * expose as control lines on the IoTKit device itself, so the 62 * code using the IoTKit can wire them up to the PPCs. 63 */ 64 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; 65 DeviceState *iotkitdev = DEVICE(s); 66 DeviceState *dev_secctl = DEVICE(&s->secctl); 67 DeviceState *dev_splitter = DEVICE(splitter); 68 char *name; 69 70 name = g_strdup_printf("%s_nonsec", ppcname); 71 qdev_pass_gpios(dev_secctl, iotkitdev, name); 72 g_free(name); 73 name = g_strdup_printf("%s_ap", ppcname); 74 qdev_pass_gpios(dev_secctl, iotkitdev, name); 75 g_free(name); 76 name = g_strdup_printf("%s_irq_enable", ppcname); 77 qdev_pass_gpios(dev_secctl, iotkitdev, name); 78 g_free(name); 79 name = g_strdup_printf("%s_irq_clear", ppcname); 80 qdev_pass_gpios(dev_secctl, iotkitdev, name); 81 g_free(name); 82 83 /* irq_status is a little more tricky, because we need to 84 * split it so we can send it both to the security controller 85 * and to our OR gate for the NVIC interrupt line. 86 * Connect up the splitter's outputs, and create a GPIO input 87 * which will pass the line state to the input splitter. 88 */ 89 name = g_strdup_printf("%s_irq_status", ppcname); 90 qdev_connect_gpio_out(dev_splitter, 0, 91 qdev_get_gpio_in_named(dev_secctl, 92 name, 0)); 93 qdev_connect_gpio_out(dev_splitter, 1, 94 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); 95 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); 96 qdev_init_gpio_in_named_with_opaque(iotkitdev, irq_status_forwarder, 97 s->irq_status_in[ppcnum], name, 1); 98 g_free(name); 99 } 100 101 static void iotkit_forward_sec_resp_cfg(IoTKit *s) 102 { 103 /* Forward the 3rd output from the splitter device as a 104 * named GPIO output of the iotkit object. 105 */ 106 DeviceState *dev = DEVICE(s); 107 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); 108 109 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); 110 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, 111 s->sec_resp_cfg, 1); 112 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); 113 } 114 115 static void iotkit_init(Object *obj) 116 { 117 IoTKit *s = IOTKIT(obj); 118 int i; 119 120 memory_region_init(&s->container, obj, "iotkit-container", UINT64_MAX); 121 122 init_sysbus_child(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), 123 TYPE_ARMV7M); 124 qdev_prop_set_string(DEVICE(&s->armv7m), "cpu-type", 125 ARM_CPU_TYPE_NAME("cortex-m33")); 126 127 init_sysbus_child(obj, "secctl", &s->secctl, sizeof(s->secctl), 128 TYPE_IOTKIT_SECCTL); 129 init_sysbus_child(obj, "apb-ppc0", &s->apb_ppc0, sizeof(s->apb_ppc0), 130 TYPE_TZ_PPC); 131 init_sysbus_child(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1), 132 TYPE_TZ_PPC); 133 init_sysbus_child(obj, "mpc", &s->mpc, sizeof(s->mpc), TYPE_TZ_MPC); 134 init_sysbus_child(obj, "timer0", &s->timer0, sizeof(s->timer0), 135 TYPE_CMSDK_APB_TIMER); 136 init_sysbus_child(obj, "timer1", &s->timer1, sizeof(s->timer1), 137 TYPE_CMSDK_APB_TIMER); 138 init_sysbus_child(obj, "dualtimer", &s->dualtimer, sizeof(s->dualtimer), 139 TYPE_UNIMPLEMENTED_DEVICE); 140 object_initialize(&s->ppc_irq_orgate, sizeof(s->ppc_irq_orgate), 141 TYPE_OR_IRQ); 142 object_property_add_child(obj, "ppc-irq-orgate", 143 OBJECT(&s->ppc_irq_orgate), &error_abort); 144 object_initialize(&s->sec_resp_splitter, sizeof(s->sec_resp_splitter), 145 TYPE_SPLIT_IRQ); 146 object_property_add_child(obj, "sec-resp-splitter", 147 OBJECT(&s->sec_resp_splitter), &error_abort); 148 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 149 char *name = g_strdup_printf("ppc-irq-splitter-%d", i); 150 SplitIRQ *splitter = &s->ppc_irq_splitter[i]; 151 152 object_initialize(splitter, sizeof(*splitter), TYPE_SPLIT_IRQ); 153 object_property_add_child(obj, name, OBJECT(splitter), &error_abort); 154 } 155 init_sysbus_child(obj, "s32ktimer", &s->s32ktimer, sizeof(s->s32ktimer), 156 TYPE_UNIMPLEMENTED_DEVICE); 157 } 158 159 static void iotkit_exp_irq(void *opaque, int n, int level) 160 { 161 IoTKit *s = IOTKIT(opaque); 162 163 qemu_set_irq(s->exp_irqs[n], level); 164 } 165 166 static void iotkit_realize(DeviceState *dev, Error **errp) 167 { 168 IoTKit *s = IOTKIT(dev); 169 int i; 170 MemoryRegion *mr; 171 Error *err = NULL; 172 SysBusDevice *sbd_apb_ppc0; 173 SysBusDevice *sbd_secctl; 174 DeviceState *dev_apb_ppc0; 175 DeviceState *dev_apb_ppc1; 176 DeviceState *dev_secctl; 177 DeviceState *dev_splitter; 178 179 if (!s->board_memory) { 180 error_setg(errp, "memory property was not set"); 181 return; 182 } 183 184 if (!s->mainclk_frq) { 185 error_setg(errp, "MAINCLK property was not set"); 186 return; 187 } 188 189 /* Handling of which devices should be available only to secure 190 * code is usually done differently for M profile than for A profile. 191 * Instead of putting some devices only into the secure address space, 192 * devices exist in both address spaces but with hard-wired security 193 * permissions that will cause the CPU to fault for non-secure accesses. 194 * 195 * The IoTKit has an IDAU (Implementation Defined Access Unit), 196 * which specifies hard-wired security permissions for different 197 * areas of the physical address space. For the IoTKit IDAU, the 198 * top 4 bits of the physical address are the IDAU region ID, and 199 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS 200 * region, otherwise it is an S region. 201 * 202 * The various devices and RAMs are generally all mapped twice, 203 * once into a region that the IDAU defines as secure and once 204 * into a non-secure region. They sit behind either a Memory 205 * Protection Controller (for RAM) or a Peripheral Protection 206 * Controller (for devices), which allow a more fine grained 207 * configuration of whether non-secure accesses are permitted. 208 * 209 * (The other place that guest software can configure security 210 * permissions is in the architected SAU (Security Attribution 211 * Unit), which is entirely inside the CPU. The IDAU can upgrade 212 * the security attributes for a region to more restrictive than 213 * the SAU specifies, but cannot downgrade them.) 214 * 215 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff 216 * 0x20000000..0x2007ffff 32KB FPGA block RAM 217 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff 218 * 0x40000000..0x4000ffff base peripheral region 1 219 * 0x40010000..0x4001ffff CPU peripherals (none for IoTKit) 220 * 0x40020000..0x4002ffff system control element peripherals 221 * 0x40080000..0x400fffff base peripheral region 2 222 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff 223 */ 224 225 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); 226 227 qdev_prop_set_uint32(DEVICE(&s->armv7m), "num-irq", s->exp_numirq + 32); 228 /* In real hardware the initial Secure VTOR is set from the INITSVTOR0 229 * register in the IoT Kit System Control Register block, and the 230 * initial value of that is in turn specifiable by the FPGA that 231 * instantiates the IoT Kit. In QEMU we don't implement this wrinkle, 232 * and simply set the CPU's init-svtor to the IoT Kit default value. 233 */ 234 qdev_prop_set_uint32(DEVICE(&s->armv7m), "init-svtor", 0x10000000); 235 object_property_set_link(OBJECT(&s->armv7m), OBJECT(&s->container), 236 "memory", &err); 237 if (err) { 238 error_propagate(errp, err); 239 return; 240 } 241 object_property_set_link(OBJECT(&s->armv7m), OBJECT(s), "idau", &err); 242 if (err) { 243 error_propagate(errp, err); 244 return; 245 } 246 object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); 247 if (err) { 248 error_propagate(errp, err); 249 return; 250 } 251 252 /* Connect our EXP_IRQ GPIOs to the NVIC's lines 32 and up. */ 253 s->exp_irqs = g_new(qemu_irq, s->exp_numirq); 254 for (i = 0; i < s->exp_numirq; i++) { 255 s->exp_irqs[i] = qdev_get_gpio_in(DEVICE(&s->armv7m), i + 32); 256 } 257 qdev_init_gpio_in_named(dev, iotkit_exp_irq, "EXP_IRQ", s->exp_numirq); 258 259 /* Set up the big aliases first */ 260 make_alias(s, &s->alias1, "alias 1", 0x10000000, 0x10000000, 0x00000000); 261 make_alias(s, &s->alias2, "alias 2", 0x30000000, 0x10000000, 0x20000000); 262 /* The 0x50000000..0x5fffffff region is not a pure alias: it has 263 * a few extra devices that only appear there (generally the 264 * control interfaces for the protection controllers). 265 * We implement this by mapping those devices over the top of this 266 * alias MR at a higher priority. 267 */ 268 make_alias(s, &s->alias3, "alias 3", 0x50000000, 0x10000000, 0x40000000); 269 270 271 /* Security controller */ 272 object_property_set_bool(OBJECT(&s->secctl), true, "realized", &err); 273 if (err) { 274 error_propagate(errp, err); 275 return; 276 } 277 sbd_secctl = SYS_BUS_DEVICE(&s->secctl); 278 dev_secctl = DEVICE(&s->secctl); 279 sysbus_mmio_map(sbd_secctl, 0, 0x50080000); 280 sysbus_mmio_map(sbd_secctl, 1, 0x40080000); 281 282 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); 283 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); 284 285 /* The sec_resp_cfg output from the security controller must be split into 286 * multiple lines, one for each of the PPCs within the IoTKit and one 287 * that will be an output from the IoTKit to the system. 288 */ 289 object_property_set_int(OBJECT(&s->sec_resp_splitter), 3, 290 "num-lines", &err); 291 if (err) { 292 error_propagate(errp, err); 293 return; 294 } 295 object_property_set_bool(OBJECT(&s->sec_resp_splitter), true, 296 "realized", &err); 297 if (err) { 298 error_propagate(errp, err); 299 return; 300 } 301 dev_splitter = DEVICE(&s->sec_resp_splitter); 302 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, 303 qdev_get_gpio_in(dev_splitter, 0)); 304 305 /* This RAM lives behind the Memory Protection Controller */ 306 memory_region_init_ram(&s->sram0, NULL, "iotkit.sram0", 0x00008000, &err); 307 if (err) { 308 error_propagate(errp, err); 309 return; 310 } 311 object_property_set_link(OBJECT(&s->mpc), OBJECT(&s->sram0), 312 "downstream", &err); 313 if (err) { 314 error_propagate(errp, err); 315 return; 316 } 317 object_property_set_bool(OBJECT(&s->mpc), true, "realized", &err); 318 if (err) { 319 error_propagate(errp, err); 320 return; 321 } 322 /* Map the upstream end of the MPC into the right place... */ 323 memory_region_add_subregion(&s->container, 0x20000000, 324 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mpc), 325 1)); 326 /* ...and its register interface */ 327 memory_region_add_subregion(&s->container, 0x50083000, 328 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mpc), 329 0)); 330 331 /* Devices behind APB PPC0: 332 * 0x40000000: timer0 333 * 0x40001000: timer1 334 * 0x40002000: dual timer 335 * We must configure and realize each downstream device and connect 336 * it to the appropriate PPC port; then we can realize the PPC and 337 * map its upstream ends to the right place in the container. 338 */ 339 qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); 340 object_property_set_bool(OBJECT(&s->timer0), true, "realized", &err); 341 if (err) { 342 error_propagate(errp, err); 343 return; 344 } 345 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, 346 qdev_get_gpio_in(DEVICE(&s->armv7m), 3)); 347 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); 348 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[0]", &err); 349 if (err) { 350 error_propagate(errp, err); 351 return; 352 } 353 354 qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); 355 object_property_set_bool(OBJECT(&s->timer1), true, "realized", &err); 356 if (err) { 357 error_propagate(errp, err); 358 return; 359 } 360 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, 361 qdev_get_gpio_in(DEVICE(&s->armv7m), 3)); 362 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); 363 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[1]", &err); 364 if (err) { 365 error_propagate(errp, err); 366 return; 367 } 368 369 qdev_prop_set_string(DEVICE(&s->dualtimer), "name", "Dual timer"); 370 qdev_prop_set_uint64(DEVICE(&s->dualtimer), "size", 0x1000); 371 object_property_set_bool(OBJECT(&s->dualtimer), true, "realized", &err); 372 if (err) { 373 error_propagate(errp, err); 374 return; 375 } 376 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); 377 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[2]", &err); 378 if (err) { 379 error_propagate(errp, err); 380 return; 381 } 382 383 object_property_set_bool(OBJECT(&s->apb_ppc0), true, "realized", &err); 384 if (err) { 385 error_propagate(errp, err); 386 return; 387 } 388 389 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); 390 dev_apb_ppc0 = DEVICE(&s->apb_ppc0); 391 392 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); 393 memory_region_add_subregion(&s->container, 0x40000000, mr); 394 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); 395 memory_region_add_subregion(&s->container, 0x40001000, mr); 396 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); 397 memory_region_add_subregion(&s->container, 0x40002000, mr); 398 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { 399 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, 400 qdev_get_gpio_in_named(dev_apb_ppc0, 401 "cfg_nonsec", i)); 402 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, 403 qdev_get_gpio_in_named(dev_apb_ppc0, 404 "cfg_ap", i)); 405 } 406 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, 407 qdev_get_gpio_in_named(dev_apb_ppc0, 408 "irq_enable", 0)); 409 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, 410 qdev_get_gpio_in_named(dev_apb_ppc0, 411 "irq_clear", 0)); 412 qdev_connect_gpio_out(dev_splitter, 0, 413 qdev_get_gpio_in_named(dev_apb_ppc0, 414 "cfg_sec_resp", 0)); 415 416 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external 417 * ones) are sent individually to the security controller, and also 418 * ORed together to give a single combined PPC interrupt to the NVIC. 419 */ 420 object_property_set_int(OBJECT(&s->ppc_irq_orgate), 421 NUM_PPCS, "num-lines", &err); 422 if (err) { 423 error_propagate(errp, err); 424 return; 425 } 426 object_property_set_bool(OBJECT(&s->ppc_irq_orgate), true, 427 "realized", &err); 428 if (err) { 429 error_propagate(errp, err); 430 return; 431 } 432 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, 433 qdev_get_gpio_in(DEVICE(&s->armv7m), 10)); 434 435 /* 0x40010000 .. 0x4001ffff: private CPU region: unused in IoTKit */ 436 437 /* 0x40020000 .. 0x4002ffff : IoTKit system control peripheral region */ 438 /* Devices behind APB PPC1: 439 * 0x4002f000: S32K timer 440 */ 441 qdev_prop_set_string(DEVICE(&s->s32ktimer), "name", "S32KTIMER"); 442 qdev_prop_set_uint64(DEVICE(&s->s32ktimer), "size", 0x1000); 443 object_property_set_bool(OBJECT(&s->s32ktimer), true, "realized", &err); 444 if (err) { 445 error_propagate(errp, err); 446 return; 447 } 448 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); 449 object_property_set_link(OBJECT(&s->apb_ppc1), OBJECT(mr), "port[0]", &err); 450 if (err) { 451 error_propagate(errp, err); 452 return; 453 } 454 455 object_property_set_bool(OBJECT(&s->apb_ppc1), true, "realized", &err); 456 if (err) { 457 error_propagate(errp, err); 458 return; 459 } 460 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); 461 memory_region_add_subregion(&s->container, 0x4002f000, mr); 462 463 dev_apb_ppc1 = DEVICE(&s->apb_ppc1); 464 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, 465 qdev_get_gpio_in_named(dev_apb_ppc1, 466 "cfg_nonsec", 0)); 467 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, 468 qdev_get_gpio_in_named(dev_apb_ppc1, 469 "cfg_ap", 0)); 470 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, 471 qdev_get_gpio_in_named(dev_apb_ppc1, 472 "irq_enable", 0)); 473 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, 474 qdev_get_gpio_in_named(dev_apb_ppc1, 475 "irq_clear", 0)); 476 qdev_connect_gpio_out(dev_splitter, 1, 477 qdev_get_gpio_in_named(dev_apb_ppc1, 478 "cfg_sec_resp", 0)); 479 480 /* Using create_unimplemented_device() maps the stub into the 481 * system address space rather than into our container, but the 482 * overall effect to the guest is the same. 483 */ 484 create_unimplemented_device("SYSINFO", 0x40020000, 0x1000); 485 486 create_unimplemented_device("SYSCONTROL", 0x50021000, 0x1000); 487 create_unimplemented_device("S32KWATCHDOG", 0x5002e000, 0x1000); 488 489 /* 0x40080000 .. 0x4008ffff : IoTKit second Base peripheral region */ 490 491 create_unimplemented_device("NS watchdog", 0x40081000, 0x1000); 492 create_unimplemented_device("S watchdog", 0x50081000, 0x1000); 493 494 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 495 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); 496 497 object_property_set_int(splitter, 2, "num-lines", &err); 498 if (err) { 499 error_propagate(errp, err); 500 return; 501 } 502 object_property_set_bool(splitter, true, "realized", &err); 503 if (err) { 504 error_propagate(errp, err); 505 return; 506 } 507 } 508 509 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { 510 char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); 511 512 iotkit_forward_ppc(s, ppcname, i); 513 g_free(ppcname); 514 } 515 516 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { 517 char *ppcname = g_strdup_printf("apb_ppcexp%d", i); 518 519 iotkit_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); 520 g_free(ppcname); 521 } 522 523 for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { 524 /* Wire up IRQ splitter for internal PPCs */ 525 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); 526 char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", 527 i - NUM_EXTERNAL_PPCS); 528 TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; 529 530 qdev_connect_gpio_out(devs, 0, 531 qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); 532 qdev_connect_gpio_out(devs, 1, 533 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); 534 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, 535 qdev_get_gpio_in(devs, 0)); 536 g_free(gpioname); 537 } 538 539 iotkit_forward_sec_resp_cfg(s); 540 541 system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; 542 } 543 544 static void iotkit_idau_check(IDAUInterface *ii, uint32_t address, 545 int *iregion, bool *exempt, bool *ns, bool *nsc) 546 { 547 /* For IoTKit systems the IDAU responses are simple logical functions 548 * of the address bits. The NSC attribute is guest-adjustable via the 549 * NSCCFG register in the security controller. 550 */ 551 IoTKit *s = IOTKIT(ii); 552 int region = extract32(address, 28, 4); 553 554 *ns = !(region & 1); 555 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); 556 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 557 *exempt = (address & 0xeff00000) == 0xe0000000; 558 *iregion = region; 559 } 560 561 static const VMStateDescription iotkit_vmstate = { 562 .name = "iotkit", 563 .version_id = 1, 564 .minimum_version_id = 1, 565 .fields = (VMStateField[]) { 566 VMSTATE_UINT32(nsccfg, IoTKit), 567 VMSTATE_END_OF_LIST() 568 } 569 }; 570 571 static Property iotkit_properties[] = { 572 DEFINE_PROP_LINK("memory", IoTKit, board_memory, TYPE_MEMORY_REGION, 573 MemoryRegion *), 574 DEFINE_PROP_UINT32("EXP_NUMIRQ", IoTKit, exp_numirq, 64), 575 DEFINE_PROP_UINT32("MAINCLK", IoTKit, mainclk_frq, 0), 576 DEFINE_PROP_END_OF_LIST() 577 }; 578 579 static void iotkit_reset(DeviceState *dev) 580 { 581 IoTKit *s = IOTKIT(dev); 582 583 s->nsccfg = 0; 584 } 585 586 static void iotkit_class_init(ObjectClass *klass, void *data) 587 { 588 DeviceClass *dc = DEVICE_CLASS(klass); 589 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); 590 591 dc->realize = iotkit_realize; 592 dc->vmsd = &iotkit_vmstate; 593 dc->props = iotkit_properties; 594 dc->reset = iotkit_reset; 595 iic->check = iotkit_idau_check; 596 } 597 598 static const TypeInfo iotkit_info = { 599 .name = TYPE_IOTKIT, 600 .parent = TYPE_SYS_BUS_DEVICE, 601 .instance_size = sizeof(IoTKit), 602 .instance_init = iotkit_init, 603 .class_init = iotkit_class_init, 604 .interfaces = (InterfaceInfo[]) { 605 { TYPE_IDAU_INTERFACE }, 606 { } 607 } 608 }; 609 610 static void iotkit_register_types(void) 611 { 612 type_register_static(&iotkit_info); 613 } 614 615 type_init(iotkit_register_types); 616