1 /* 2 * Arm SSE (Subsystems for Embedded): IoTKit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qemu/bitops.h" 16 #include "qapi/error.h" 17 #include "trace.h" 18 #include "hw/sysbus.h" 19 #include "migration/vmstate.h" 20 #include "hw/registerfields.h" 21 #include "hw/arm/armsse.h" 22 #include "hw/arm/boot.h" 23 #include "hw/irq.h" 24 25 /* Format of the System Information block SYS_CONFIG register */ 26 typedef enum SysConfigFormat { 27 IoTKitFormat, 28 SSE200Format, 29 } SysConfigFormat; 30 31 struct ARMSSEInfo { 32 const char *name; 33 int sram_banks; 34 int num_cpus; 35 uint32_t sys_version; 36 uint32_t cpuwait_rst; 37 SysConfigFormat sys_config_format; 38 bool has_mhus; 39 bool has_ppus; 40 bool has_cachectrl; 41 bool has_cpusecctrl; 42 bool has_cpuid; 43 Property *props; 44 }; 45 46 static Property iotkit_properties[] = { 47 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 48 MemoryRegion *), 49 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 50 DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), 51 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 52 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 53 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), 54 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), 55 DEFINE_PROP_END_OF_LIST() 56 }; 57 58 static Property armsse_properties[] = { 59 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 60 MemoryRegion *), 61 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 62 DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), 63 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 64 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 65 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), 66 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), 67 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), 68 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), 69 DEFINE_PROP_END_OF_LIST() 70 }; 71 72 static const ARMSSEInfo armsse_variants[] = { 73 { 74 .name = TYPE_IOTKIT, 75 .sram_banks = 1, 76 .num_cpus = 1, 77 .sys_version = 0x41743, 78 .cpuwait_rst = 0, 79 .sys_config_format = IoTKitFormat, 80 .has_mhus = false, 81 .has_ppus = false, 82 .has_cachectrl = false, 83 .has_cpusecctrl = false, 84 .has_cpuid = false, 85 .props = iotkit_properties, 86 }, 87 { 88 .name = TYPE_SSE200, 89 .sram_banks = 4, 90 .num_cpus = 2, 91 .sys_version = 0x22041743, 92 .cpuwait_rst = 2, 93 .sys_config_format = SSE200Format, 94 .has_mhus = true, 95 .has_ppus = true, 96 .has_cachectrl = true, 97 .has_cpusecctrl = true, 98 .has_cpuid = true, 99 .props = armsse_properties, 100 }, 101 }; 102 103 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) 104 { 105 /* Return the SYS_CONFIG value for this SSE */ 106 uint32_t sys_config; 107 108 switch (info->sys_config_format) { 109 case IoTKitFormat: 110 sys_config = 0; 111 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 112 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); 113 break; 114 case SSE200Format: 115 sys_config = 0; 116 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 117 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 118 sys_config = deposit32(sys_config, 24, 4, 2); 119 if (info->num_cpus > 1) { 120 sys_config = deposit32(sys_config, 10, 1, 1); 121 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1); 122 sys_config = deposit32(sys_config, 28, 4, 2); 123 } 124 break; 125 default: 126 g_assert_not_reached(); 127 } 128 return sys_config; 129 } 130 131 /* Clock frequency in HZ of the 32KHz "slow clock" */ 132 #define S32KCLK (32 * 1000) 133 134 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ 135 static bool irq_is_common[32] = { 136 [0 ... 5] = true, 137 /* 6, 7: per-CPU MHU interrupts */ 138 [8 ... 12] = true, 139 /* 13: per-CPU icache interrupt */ 140 /* 14: reserved */ 141 [15 ... 20] = true, 142 /* 21: reserved */ 143 [22 ... 26] = true, 144 /* 27: reserved */ 145 /* 28, 29: per-CPU CTI interrupts */ 146 /* 30, 31: reserved */ 147 }; 148 149 /* 150 * Create an alias region in @container of @size bytes starting at @base 151 * which mirrors the memory starting at @orig. 152 */ 153 static void make_alias(ARMSSE *s, MemoryRegion *mr, MemoryRegion *container, 154 const char *name, hwaddr base, hwaddr size, hwaddr orig) 155 { 156 memory_region_init_alias(mr, NULL, name, container, orig, size); 157 /* The alias is even lower priority than unimplemented_device regions */ 158 memory_region_add_subregion_overlap(container, base, mr, -1500); 159 } 160 161 static void irq_status_forwarder(void *opaque, int n, int level) 162 { 163 qemu_irq destirq = opaque; 164 165 qemu_set_irq(destirq, level); 166 } 167 168 static void nsccfg_handler(void *opaque, int n, int level) 169 { 170 ARMSSE *s = ARMSSE(opaque); 171 172 s->nsccfg = level; 173 } 174 175 static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) 176 { 177 /* Each of the 4 AHB and 4 APB PPCs that might be present in a 178 * system using the ARMSSE has a collection of control lines which 179 * are provided by the security controller and which we want to 180 * expose as control lines on the ARMSSE device itself, so the 181 * code using the ARMSSE can wire them up to the PPCs. 182 */ 183 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; 184 DeviceState *armssedev = DEVICE(s); 185 DeviceState *dev_secctl = DEVICE(&s->secctl); 186 DeviceState *dev_splitter = DEVICE(splitter); 187 char *name; 188 189 name = g_strdup_printf("%s_nonsec", ppcname); 190 qdev_pass_gpios(dev_secctl, armssedev, name); 191 g_free(name); 192 name = g_strdup_printf("%s_ap", ppcname); 193 qdev_pass_gpios(dev_secctl, armssedev, name); 194 g_free(name); 195 name = g_strdup_printf("%s_irq_enable", ppcname); 196 qdev_pass_gpios(dev_secctl, armssedev, name); 197 g_free(name); 198 name = g_strdup_printf("%s_irq_clear", ppcname); 199 qdev_pass_gpios(dev_secctl, armssedev, name); 200 g_free(name); 201 202 /* irq_status is a little more tricky, because we need to 203 * split it so we can send it both to the security controller 204 * and to our OR gate for the NVIC interrupt line. 205 * Connect up the splitter's outputs, and create a GPIO input 206 * which will pass the line state to the input splitter. 207 */ 208 name = g_strdup_printf("%s_irq_status", ppcname); 209 qdev_connect_gpio_out(dev_splitter, 0, 210 qdev_get_gpio_in_named(dev_secctl, 211 name, 0)); 212 qdev_connect_gpio_out(dev_splitter, 1, 213 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); 214 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); 215 qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder, 216 s->irq_status_in[ppcnum], name, 1); 217 g_free(name); 218 } 219 220 static void armsse_forward_sec_resp_cfg(ARMSSE *s) 221 { 222 /* Forward the 3rd output from the splitter device as a 223 * named GPIO output of the armsse object. 224 */ 225 DeviceState *dev = DEVICE(s); 226 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); 227 228 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); 229 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, 230 s->sec_resp_cfg, 1); 231 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); 232 } 233 234 static void armsse_init(Object *obj) 235 { 236 ARMSSE *s = ARMSSE(obj); 237 ARMSSEClass *asc = ARMSSE_GET_CLASS(obj); 238 const ARMSSEInfo *info = asc->info; 239 int i; 240 241 assert(info->sram_banks <= MAX_SRAM_BANKS); 242 assert(info->num_cpus <= SSE_MAX_CPUS); 243 244 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); 245 246 for (i = 0; i < info->num_cpus; i++) { 247 /* 248 * We put each CPU in its own cluster as they are logically 249 * distinct and may be configured differently. 250 */ 251 char *name; 252 253 name = g_strdup_printf("cluster%d", i); 254 object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER); 255 qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); 256 g_free(name); 257 258 name = g_strdup_printf("armv7m%d", i); 259 sysbus_init_child_obj(OBJECT(&s->cluster[i]), name, 260 &s->armv7m[i], sizeof(s->armv7m), TYPE_ARMV7M); 261 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", 262 ARM_CPU_TYPE_NAME("cortex-m33")); 263 g_free(name); 264 name = g_strdup_printf("arm-sse-cpu-container%d", i); 265 memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); 266 g_free(name); 267 if (i > 0) { 268 name = g_strdup_printf("arm-sse-container-alias%d", i); 269 memory_region_init_alias(&s->container_alias[i - 1], obj, 270 name, &s->container, 0, UINT64_MAX); 271 g_free(name); 272 } 273 } 274 275 sysbus_init_child_obj(obj, "secctl", &s->secctl, sizeof(s->secctl), 276 TYPE_IOTKIT_SECCTL); 277 sysbus_init_child_obj(obj, "apb-ppc0", &s->apb_ppc0, sizeof(s->apb_ppc0), 278 TYPE_TZ_PPC); 279 sysbus_init_child_obj(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1), 280 TYPE_TZ_PPC); 281 for (i = 0; i < info->sram_banks; i++) { 282 char *name = g_strdup_printf("mpc%d", i); 283 sysbus_init_child_obj(obj, name, &s->mpc[i], 284 sizeof(s->mpc[i]), TYPE_TZ_MPC); 285 g_free(name); 286 } 287 object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate, 288 TYPE_OR_IRQ); 289 290 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 291 char *name = g_strdup_printf("mpc-irq-splitter-%d", i); 292 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 293 294 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 295 g_free(name); 296 } 297 sysbus_init_child_obj(obj, "timer0", &s->timer0, sizeof(s->timer0), 298 TYPE_CMSDK_APB_TIMER); 299 sysbus_init_child_obj(obj, "timer1", &s->timer1, sizeof(s->timer1), 300 TYPE_CMSDK_APB_TIMER); 301 sysbus_init_child_obj(obj, "s32ktimer", &s->s32ktimer, sizeof(s->s32ktimer), 302 TYPE_CMSDK_APB_TIMER); 303 sysbus_init_child_obj(obj, "dualtimer", &s->dualtimer, sizeof(s->dualtimer), 304 TYPE_CMSDK_APB_DUALTIMER); 305 sysbus_init_child_obj(obj, "s32kwatchdog", &s->s32kwatchdog, 306 sizeof(s->s32kwatchdog), TYPE_CMSDK_APB_WATCHDOG); 307 sysbus_init_child_obj(obj, "nswatchdog", &s->nswatchdog, 308 sizeof(s->nswatchdog), TYPE_CMSDK_APB_WATCHDOG); 309 sysbus_init_child_obj(obj, "swatchdog", &s->swatchdog, 310 sizeof(s->swatchdog), TYPE_CMSDK_APB_WATCHDOG); 311 sysbus_init_child_obj(obj, "armsse-sysctl", &s->sysctl, 312 sizeof(s->sysctl), TYPE_IOTKIT_SYSCTL); 313 sysbus_init_child_obj(obj, "armsse-sysinfo", &s->sysinfo, 314 sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO); 315 if (info->has_mhus) { 316 sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]), 317 TYPE_ARMSSE_MHU); 318 sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]), 319 TYPE_ARMSSE_MHU); 320 } 321 if (info->has_ppus) { 322 for (i = 0; i < info->num_cpus; i++) { 323 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 324 int ppuidx = CPU0CORE_PPU + i; 325 326 sysbus_init_child_obj(obj, name, &s->ppu[ppuidx], 327 sizeof(s->ppu[ppuidx]), 328 TYPE_UNIMPLEMENTED_DEVICE); 329 g_free(name); 330 } 331 sysbus_init_child_obj(obj, "DBG_PPU", &s->ppu[DBG_PPU], 332 sizeof(s->ppu[DBG_PPU]), 333 TYPE_UNIMPLEMENTED_DEVICE); 334 for (i = 0; i < info->sram_banks; i++) { 335 char *name = g_strdup_printf("RAM%d_PPU", i); 336 int ppuidx = RAM0_PPU + i; 337 338 sysbus_init_child_obj(obj, name, &s->ppu[ppuidx], 339 sizeof(s->ppu[ppuidx]), 340 TYPE_UNIMPLEMENTED_DEVICE); 341 g_free(name); 342 } 343 } 344 if (info->has_cachectrl) { 345 for (i = 0; i < info->num_cpus; i++) { 346 char *name = g_strdup_printf("cachectrl%d", i); 347 348 sysbus_init_child_obj(obj, name, &s->cachectrl[i], 349 sizeof(s->cachectrl[i]), 350 TYPE_UNIMPLEMENTED_DEVICE); 351 g_free(name); 352 } 353 } 354 if (info->has_cpusecctrl) { 355 for (i = 0; i < info->num_cpus; i++) { 356 char *name = g_strdup_printf("cpusecctrl%d", i); 357 358 sysbus_init_child_obj(obj, name, &s->cpusecctrl[i], 359 sizeof(s->cpusecctrl[i]), 360 TYPE_UNIMPLEMENTED_DEVICE); 361 g_free(name); 362 } 363 } 364 if (info->has_cpuid) { 365 for (i = 0; i < info->num_cpus; i++) { 366 char *name = g_strdup_printf("cpuid%d", i); 367 368 sysbus_init_child_obj(obj, name, &s->cpuid[i], 369 sizeof(s->cpuid[i]), 370 TYPE_ARMSSE_CPUID); 371 g_free(name); 372 } 373 } 374 object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ); 375 object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, 376 TYPE_OR_IRQ); 377 object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter, 378 TYPE_SPLIT_IRQ); 379 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 380 char *name = g_strdup_printf("ppc-irq-splitter-%d", i); 381 SplitIRQ *splitter = &s->ppc_irq_splitter[i]; 382 383 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 384 g_free(name); 385 } 386 if (info->num_cpus > 1) { 387 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 388 if (irq_is_common[i]) { 389 char *name = g_strdup_printf("cpu-irq-splitter%d", i); 390 SplitIRQ *splitter = &s->cpu_irq_splitter[i]; 391 392 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 393 g_free(name); 394 } 395 } 396 } 397 } 398 399 static void armsse_exp_irq(void *opaque, int n, int level) 400 { 401 qemu_irq *irqarray = opaque; 402 403 qemu_set_irq(irqarray[n], level); 404 } 405 406 static void armsse_mpcexp_status(void *opaque, int n, int level) 407 { 408 ARMSSE *s = ARMSSE(opaque); 409 qemu_set_irq(s->mpcexp_status_in[n], level); 410 } 411 412 static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno) 413 { 414 /* 415 * Return a qemu_irq which can be used to signal IRQ n to 416 * all CPUs in the SSE. 417 */ 418 ARMSSEClass *asc = ARMSSE_GET_CLASS(s); 419 const ARMSSEInfo *info = asc->info; 420 421 assert(irq_is_common[irqno]); 422 423 if (info->num_cpus == 1) { 424 /* Only one CPU -- just connect directly to it */ 425 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); 426 } else { 427 /* Connect to the splitter which feeds all CPUs */ 428 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); 429 } 430 } 431 432 static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) 433 { 434 /* Map a PPU unimplemented device stub */ 435 DeviceState *dev = DEVICE(&s->ppu[ppuidx]); 436 437 qdev_prop_set_string(dev, "name", name); 438 qdev_prop_set_uint64(dev, "size", 0x1000); 439 qdev_init_nofail(dev); 440 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); 441 } 442 443 static void armsse_realize(DeviceState *dev, Error **errp) 444 { 445 ARMSSE *s = ARMSSE(dev); 446 ARMSSEClass *asc = ARMSSE_GET_CLASS(dev); 447 const ARMSSEInfo *info = asc->info; 448 int i; 449 MemoryRegion *mr; 450 Error *err = NULL; 451 SysBusDevice *sbd_apb_ppc0; 452 SysBusDevice *sbd_secctl; 453 DeviceState *dev_apb_ppc0; 454 DeviceState *dev_apb_ppc1; 455 DeviceState *dev_secctl; 456 DeviceState *dev_splitter; 457 uint32_t addr_width_max; 458 459 if (!s->board_memory) { 460 error_setg(errp, "memory property was not set"); 461 return; 462 } 463 464 if (!s->mainclk_frq) { 465 error_setg(errp, "MAINCLK property was not set"); 466 return; 467 } 468 469 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ 470 assert(is_power_of_2(info->sram_banks)); 471 addr_width_max = 24 - ctz32(info->sram_banks); 472 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { 473 error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d", 474 addr_width_max); 475 return; 476 } 477 478 /* Handling of which devices should be available only to secure 479 * code is usually done differently for M profile than for A profile. 480 * Instead of putting some devices only into the secure address space, 481 * devices exist in both address spaces but with hard-wired security 482 * permissions that will cause the CPU to fault for non-secure accesses. 483 * 484 * The ARMSSE has an IDAU (Implementation Defined Access Unit), 485 * which specifies hard-wired security permissions for different 486 * areas of the physical address space. For the ARMSSE IDAU, the 487 * top 4 bits of the physical address are the IDAU region ID, and 488 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS 489 * region, otherwise it is an S region. 490 * 491 * The various devices and RAMs are generally all mapped twice, 492 * once into a region that the IDAU defines as secure and once 493 * into a non-secure region. They sit behind either a Memory 494 * Protection Controller (for RAM) or a Peripheral Protection 495 * Controller (for devices), which allow a more fine grained 496 * configuration of whether non-secure accesses are permitted. 497 * 498 * (The other place that guest software can configure security 499 * permissions is in the architected SAU (Security Attribution 500 * Unit), which is entirely inside the CPU. The IDAU can upgrade 501 * the security attributes for a region to more restrictive than 502 * the SAU specifies, but cannot downgrade them.) 503 * 504 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff 505 * 0x20000000..0x2007ffff 32KB FPGA block RAM 506 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff 507 * 0x40000000..0x4000ffff base peripheral region 1 508 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) 509 * 0x40020000..0x4002ffff system control element peripherals 510 * 0x40080000..0x400fffff base peripheral region 2 511 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff 512 */ 513 514 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); 515 516 for (i = 0; i < info->num_cpus; i++) { 517 DeviceState *cpudev = DEVICE(&s->armv7m[i]); 518 Object *cpuobj = OBJECT(&s->armv7m[i]); 519 int j; 520 char *gpioname; 521 522 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32); 523 /* 524 * In real hardware the initial Secure VTOR is set from the INITSVTOR* 525 * registers in the IoT Kit System Control Register block. In QEMU 526 * we set the initial value here, and also the reset value of the 527 * sysctl register, from this object's QOM init-svtor property. 528 * If the guest changes the INITSVTOR* registers at runtime then the 529 * code in iotkit-sysctl.c will update the CPU init-svtor property 530 * (which will then take effect on the next CPU warm-reset). 531 * 532 * Note that typically a board using the SSE-200 will have a system 533 * control processor whose boot firmware initializes the INITSVTOR* 534 * registers before powering up the CPUs. QEMU doesn't emulate 535 * the control processor, so instead we behave in the way that the 536 * firmware does: the initial value should be set by the board code 537 * (using the init-svtor property on the ARMSSE object) to match 538 * whatever its firmware does. 539 */ 540 qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); 541 /* 542 * CPUs start powered down if the corresponding bit in the CPUWAIT 543 * register is 1. In real hardware the CPUWAIT register reset value is 544 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and 545 * CPUWAIT1_RST parameters), but since all the boards we care about 546 * start CPU0 and leave CPU1 powered off, we hard-code that in 547 * info->cpuwait_rst for now. We can add QOM properties for this 548 * later if necessary. 549 */ 550 if (extract32(info->cpuwait_rst, i, 1)) { 551 object_property_set_bool(cpuobj, true, "start-powered-off", &err); 552 if (err) { 553 error_propagate(errp, err); 554 return; 555 } 556 } 557 if (!s->cpu_fpu[i]) { 558 object_property_set_bool(cpuobj, false, "vfp", &err); 559 if (err) { 560 error_propagate(errp, err); 561 return; 562 } 563 } 564 if (!s->cpu_dsp[i]) { 565 object_property_set_bool(cpuobj, false, "dsp", &err); 566 if (err) { 567 error_propagate(errp, err); 568 return; 569 } 570 } 571 572 if (i > 0) { 573 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 574 &s->container_alias[i - 1], -1); 575 } else { 576 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 577 &s->container, -1); 578 } 579 object_property_set_link(cpuobj, OBJECT(&s->cpu_container[i]), 580 "memory", &err); 581 if (err) { 582 error_propagate(errp, err); 583 return; 584 } 585 object_property_set_link(cpuobj, OBJECT(s), "idau", &err); 586 if (err) { 587 error_propagate(errp, err); 588 return; 589 } 590 object_property_set_bool(cpuobj, true, "realized", &err); 591 if (err) { 592 error_propagate(errp, err); 593 return; 594 } 595 /* 596 * The cluster must be realized after the armv7m container, as 597 * the container's CPU object is only created on realize, and the 598 * CPU must exist and have been parented into the cluster before 599 * the cluster is realized. 600 */ 601 object_property_set_bool(OBJECT(&s->cluster[i]), 602 true, "realized", &err); 603 if (err) { 604 error_propagate(errp, err); 605 return; 606 } 607 608 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ 609 s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); 610 for (j = 0; j < s->exp_numirq; j++) { 611 s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32); 612 } 613 if (i == 0) { 614 gpioname = g_strdup("EXP_IRQ"); 615 } else { 616 gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i); 617 } 618 qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq, 619 s->exp_irqs[i], 620 gpioname, s->exp_numirq); 621 g_free(gpioname); 622 } 623 624 /* Wire up the splitters that connect common IRQs to all CPUs */ 625 if (info->num_cpus > 1) { 626 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 627 if (irq_is_common[i]) { 628 Object *splitter = OBJECT(&s->cpu_irq_splitter[i]); 629 DeviceState *devs = DEVICE(splitter); 630 int cpunum; 631 632 object_property_set_int(splitter, info->num_cpus, 633 "num-lines", &err); 634 if (err) { 635 error_propagate(errp, err); 636 return; 637 } 638 object_property_set_bool(splitter, true, "realized", &err); 639 if (err) { 640 error_propagate(errp, err); 641 return; 642 } 643 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 644 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 645 646 qdev_connect_gpio_out(devs, cpunum, 647 qdev_get_gpio_in(cpudev, i)); 648 } 649 } 650 } 651 } 652 653 /* Set up the big aliases first */ 654 make_alias(s, &s->alias1, &s->container, "alias 1", 655 0x10000000, 0x10000000, 0x00000000); 656 make_alias(s, &s->alias2, &s->container, 657 "alias 2", 0x30000000, 0x10000000, 0x20000000); 658 /* The 0x50000000..0x5fffffff region is not a pure alias: it has 659 * a few extra devices that only appear there (generally the 660 * control interfaces for the protection controllers). 661 * We implement this by mapping those devices over the top of this 662 * alias MR at a higher priority. Some of the devices in this range 663 * are per-CPU, so we must put this alias in the per-cpu containers. 664 */ 665 for (i = 0; i < info->num_cpus; i++) { 666 make_alias(s, &s->alias3[i], &s->cpu_container[i], 667 "alias 3", 0x50000000, 0x10000000, 0x40000000); 668 } 669 670 /* Security controller */ 671 object_property_set_bool(OBJECT(&s->secctl), true, "realized", &err); 672 if (err) { 673 error_propagate(errp, err); 674 return; 675 } 676 sbd_secctl = SYS_BUS_DEVICE(&s->secctl); 677 dev_secctl = DEVICE(&s->secctl); 678 sysbus_mmio_map(sbd_secctl, 0, 0x50080000); 679 sysbus_mmio_map(sbd_secctl, 1, 0x40080000); 680 681 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); 682 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); 683 684 /* The sec_resp_cfg output from the security controller must be split into 685 * multiple lines, one for each of the PPCs within the ARMSSE and one 686 * that will be an output from the ARMSSE to the system. 687 */ 688 object_property_set_int(OBJECT(&s->sec_resp_splitter), 3, 689 "num-lines", &err); 690 if (err) { 691 error_propagate(errp, err); 692 return; 693 } 694 object_property_set_bool(OBJECT(&s->sec_resp_splitter), true, 695 "realized", &err); 696 if (err) { 697 error_propagate(errp, err); 698 return; 699 } 700 dev_splitter = DEVICE(&s->sec_resp_splitter); 701 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, 702 qdev_get_gpio_in(dev_splitter, 0)); 703 704 /* Each SRAM bank lives behind its own Memory Protection Controller */ 705 for (i = 0; i < info->sram_banks; i++) { 706 char *ramname = g_strdup_printf("armsse.sram%d", i); 707 SysBusDevice *sbd_mpc; 708 uint32_t sram_bank_size = 1 << s->sram_addr_width; 709 710 memory_region_init_ram(&s->sram[i], NULL, ramname, 711 sram_bank_size, &err); 712 g_free(ramname); 713 if (err) { 714 error_propagate(errp, err); 715 return; 716 } 717 object_property_set_link(OBJECT(&s->mpc[i]), OBJECT(&s->sram[i]), 718 "downstream", &err); 719 if (err) { 720 error_propagate(errp, err); 721 return; 722 } 723 object_property_set_bool(OBJECT(&s->mpc[i]), true, "realized", &err); 724 if (err) { 725 error_propagate(errp, err); 726 return; 727 } 728 /* Map the upstream end of the MPC into the right place... */ 729 sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); 730 memory_region_add_subregion(&s->container, 731 0x20000000 + i * sram_bank_size, 732 sysbus_mmio_get_region(sbd_mpc, 1)); 733 /* ...and its register interface */ 734 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, 735 sysbus_mmio_get_region(sbd_mpc, 0)); 736 } 737 738 /* We must OR together lines from the MPC splitters to go to the NVIC */ 739 object_property_set_int(OBJECT(&s->mpc_irq_orgate), 740 IOTS_NUM_EXP_MPC + info->sram_banks, 741 "num-lines", &err); 742 if (err) { 743 error_propagate(errp, err); 744 return; 745 } 746 object_property_set_bool(OBJECT(&s->mpc_irq_orgate), true, 747 "realized", &err); 748 if (err) { 749 error_propagate(errp, err); 750 return; 751 } 752 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, 753 armsse_get_common_irq_in(s, 9)); 754 755 /* Devices behind APB PPC0: 756 * 0x40000000: timer0 757 * 0x40001000: timer1 758 * 0x40002000: dual timer 759 * 0x40003000: MHU0 (SSE-200 only) 760 * 0x40004000: MHU1 (SSE-200 only) 761 * We must configure and realize each downstream device and connect 762 * it to the appropriate PPC port; then we can realize the PPC and 763 * map its upstream ends to the right place in the container. 764 */ 765 qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); 766 object_property_set_bool(OBJECT(&s->timer0), true, "realized", &err); 767 if (err) { 768 error_propagate(errp, err); 769 return; 770 } 771 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, 772 armsse_get_common_irq_in(s, 3)); 773 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); 774 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[0]", &err); 775 if (err) { 776 error_propagate(errp, err); 777 return; 778 } 779 780 qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); 781 object_property_set_bool(OBJECT(&s->timer1), true, "realized", &err); 782 if (err) { 783 error_propagate(errp, err); 784 return; 785 } 786 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, 787 armsse_get_common_irq_in(s, 4)); 788 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); 789 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[1]", &err); 790 if (err) { 791 error_propagate(errp, err); 792 return; 793 } 794 795 796 qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); 797 object_property_set_bool(OBJECT(&s->dualtimer), true, "realized", &err); 798 if (err) { 799 error_propagate(errp, err); 800 return; 801 } 802 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dualtimer), 0, 803 armsse_get_common_irq_in(s, 5)); 804 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); 805 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[2]", &err); 806 if (err) { 807 error_propagate(errp, err); 808 return; 809 } 810 811 if (info->has_mhus) { 812 /* 813 * An SSE-200 with only one CPU should have only one MHU created, 814 * with the region where the second MHU usually is being RAZ/WI. 815 * We don't implement that SSE-200 config; if we want to support 816 * it then this code needs to be enhanced to handle creating the 817 * RAZ/WI region instead of the second MHU. 818 */ 819 assert(info->num_cpus == ARRAY_SIZE(s->mhu)); 820 821 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { 822 char *port; 823 int cpunum; 824 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]); 825 826 object_property_set_bool(OBJECT(&s->mhu[i]), true, 827 "realized", &err); 828 if (err) { 829 error_propagate(errp, err); 830 return; 831 } 832 port = g_strdup_printf("port[%d]", i + 3); 833 mr = sysbus_mmio_get_region(mhu_sbd, 0); 834 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), 835 port, &err); 836 g_free(port); 837 if (err) { 838 error_propagate(errp, err); 839 return; 840 } 841 842 /* 843 * Each MHU has an irq line for each CPU: 844 * MHU 0 irq line 0 -> CPU 0 IRQ 6 845 * MHU 0 irq line 1 -> CPU 1 IRQ 6 846 * MHU 1 irq line 0 -> CPU 0 IRQ 7 847 * MHU 1 irq line 1 -> CPU 1 IRQ 7 848 */ 849 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 850 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 851 852 sysbus_connect_irq(mhu_sbd, cpunum, 853 qdev_get_gpio_in(cpudev, 6 + i)); 854 } 855 } 856 } 857 858 object_property_set_bool(OBJECT(&s->apb_ppc0), true, "realized", &err); 859 if (err) { 860 error_propagate(errp, err); 861 return; 862 } 863 864 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); 865 dev_apb_ppc0 = DEVICE(&s->apb_ppc0); 866 867 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); 868 memory_region_add_subregion(&s->container, 0x40000000, mr); 869 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); 870 memory_region_add_subregion(&s->container, 0x40001000, mr); 871 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); 872 memory_region_add_subregion(&s->container, 0x40002000, mr); 873 if (info->has_mhus) { 874 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3); 875 memory_region_add_subregion(&s->container, 0x40003000, mr); 876 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4); 877 memory_region_add_subregion(&s->container, 0x40004000, mr); 878 } 879 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { 880 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, 881 qdev_get_gpio_in_named(dev_apb_ppc0, 882 "cfg_nonsec", i)); 883 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, 884 qdev_get_gpio_in_named(dev_apb_ppc0, 885 "cfg_ap", i)); 886 } 887 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, 888 qdev_get_gpio_in_named(dev_apb_ppc0, 889 "irq_enable", 0)); 890 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, 891 qdev_get_gpio_in_named(dev_apb_ppc0, 892 "irq_clear", 0)); 893 qdev_connect_gpio_out(dev_splitter, 0, 894 qdev_get_gpio_in_named(dev_apb_ppc0, 895 "cfg_sec_resp", 0)); 896 897 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external 898 * ones) are sent individually to the security controller, and also 899 * ORed together to give a single combined PPC interrupt to the NVIC. 900 */ 901 object_property_set_int(OBJECT(&s->ppc_irq_orgate), 902 NUM_PPCS, "num-lines", &err); 903 if (err) { 904 error_propagate(errp, err); 905 return; 906 } 907 object_property_set_bool(OBJECT(&s->ppc_irq_orgate), true, 908 "realized", &err); 909 if (err) { 910 error_propagate(errp, err); 911 return; 912 } 913 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, 914 armsse_get_common_irq_in(s, 10)); 915 916 /* 917 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): 918 * private per-CPU region (all these devices are SSE-200 only): 919 * 0x50010000: L1 icache control registers 920 * 0x50011000: CPUSECCTRL (CPU local security control registers) 921 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block 922 */ 923 if (info->has_cachectrl) { 924 for (i = 0; i < info->num_cpus; i++) { 925 char *name = g_strdup_printf("cachectrl%d", i); 926 MemoryRegion *mr; 927 928 qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); 929 g_free(name); 930 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); 931 object_property_set_bool(OBJECT(&s->cachectrl[i]), true, 932 "realized", &err); 933 if (err) { 934 error_propagate(errp, err); 935 return; 936 } 937 938 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); 939 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); 940 } 941 } 942 if (info->has_cpusecctrl) { 943 for (i = 0; i < info->num_cpus; i++) { 944 char *name = g_strdup_printf("CPUSECCTRL%d", i); 945 MemoryRegion *mr; 946 947 qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); 948 g_free(name); 949 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); 950 object_property_set_bool(OBJECT(&s->cpusecctrl[i]), true, 951 "realized", &err); 952 if (err) { 953 error_propagate(errp, err); 954 return; 955 } 956 957 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); 958 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); 959 } 960 } 961 if (info->has_cpuid) { 962 for (i = 0; i < info->num_cpus; i++) { 963 MemoryRegion *mr; 964 965 qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); 966 object_property_set_bool(OBJECT(&s->cpuid[i]), true, 967 "realized", &err); 968 if (err) { 969 error_propagate(errp, err); 970 return; 971 } 972 973 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); 974 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); 975 } 976 } 977 978 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */ 979 /* Devices behind APB PPC1: 980 * 0x4002f000: S32K timer 981 */ 982 qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); 983 object_property_set_bool(OBJECT(&s->s32ktimer), true, "realized", &err); 984 if (err) { 985 error_propagate(errp, err); 986 return; 987 } 988 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, 989 armsse_get_common_irq_in(s, 2)); 990 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); 991 object_property_set_link(OBJECT(&s->apb_ppc1), OBJECT(mr), "port[0]", &err); 992 if (err) { 993 error_propagate(errp, err); 994 return; 995 } 996 997 object_property_set_bool(OBJECT(&s->apb_ppc1), true, "realized", &err); 998 if (err) { 999 error_propagate(errp, err); 1000 return; 1001 } 1002 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); 1003 memory_region_add_subregion(&s->container, 0x4002f000, mr); 1004 1005 dev_apb_ppc1 = DEVICE(&s->apb_ppc1); 1006 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, 1007 qdev_get_gpio_in_named(dev_apb_ppc1, 1008 "cfg_nonsec", 0)); 1009 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, 1010 qdev_get_gpio_in_named(dev_apb_ppc1, 1011 "cfg_ap", 0)); 1012 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, 1013 qdev_get_gpio_in_named(dev_apb_ppc1, 1014 "irq_enable", 0)); 1015 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, 1016 qdev_get_gpio_in_named(dev_apb_ppc1, 1017 "irq_clear", 0)); 1018 qdev_connect_gpio_out(dev_splitter, 1, 1019 qdev_get_gpio_in_named(dev_apb_ppc1, 1020 "cfg_sec_resp", 0)); 1021 1022 object_property_set_int(OBJECT(&s->sysinfo), info->sys_version, 1023 "SYS_VERSION", &err); 1024 if (err) { 1025 error_propagate(errp, err); 1026 return; 1027 } 1028 object_property_set_int(OBJECT(&s->sysinfo), 1029 armsse_sys_config_value(s, info), 1030 "SYS_CONFIG", &err); 1031 if (err) { 1032 error_propagate(errp, err); 1033 return; 1034 } 1035 object_property_set_bool(OBJECT(&s->sysinfo), true, "realized", &err); 1036 if (err) { 1037 error_propagate(errp, err); 1038 return; 1039 } 1040 /* System information registers */ 1041 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); 1042 /* System control registers */ 1043 object_property_set_int(OBJECT(&s->sysctl), info->sys_version, 1044 "SYS_VERSION", &err); 1045 object_property_set_int(OBJECT(&s->sysctl), info->cpuwait_rst, 1046 "CPUWAIT_RST", &err); 1047 object_property_set_int(OBJECT(&s->sysctl), s->init_svtor, 1048 "INITSVTOR0_RST", &err); 1049 object_property_set_int(OBJECT(&s->sysctl), s->init_svtor, 1050 "INITSVTOR1_RST", &err); 1051 object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err); 1052 if (err) { 1053 error_propagate(errp, err); 1054 return; 1055 } 1056 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); 1057 1058 if (info->has_ppus) { 1059 /* CPUnCORE_PPU for each CPU */ 1060 for (i = 0; i < info->num_cpus; i++) { 1061 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 1062 1063 map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); 1064 /* 1065 * We don't support CPU debug so don't create the 1066 * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. 1067 */ 1068 g_free(name); 1069 } 1070 map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); 1071 1072 for (i = 0; i < info->sram_banks; i++) { 1073 char *name = g_strdup_printf("RAM%d_PPU", i); 1074 1075 map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); 1076 g_free(name); 1077 } 1078 } 1079 1080 /* This OR gate wires together outputs from the secure watchdogs to NMI */ 1081 object_property_set_int(OBJECT(&s->nmi_orgate), 2, "num-lines", &err); 1082 if (err) { 1083 error_propagate(errp, err); 1084 return; 1085 } 1086 object_property_set_bool(OBJECT(&s->nmi_orgate), true, "realized", &err); 1087 if (err) { 1088 error_propagate(errp, err); 1089 return; 1090 } 1091 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, 1092 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); 1093 1094 qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); 1095 object_property_set_bool(OBJECT(&s->s32kwatchdog), true, "realized", &err); 1096 if (err) { 1097 error_propagate(errp, err); 1098 return; 1099 } 1100 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 1101 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 0)); 1102 sysbus_mmio_map(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 0x5002e000); 1103 1104 /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ 1105 1106 qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); 1107 object_property_set_bool(OBJECT(&s->nswatchdog), true, "realized", &err); 1108 if (err) { 1109 error_propagate(errp, err); 1110 return; 1111 } 1112 sysbus_connect_irq(SYS_BUS_DEVICE(&s->nswatchdog), 0, 1113 armsse_get_common_irq_in(s, 1)); 1114 sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); 1115 1116 qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); 1117 object_property_set_bool(OBJECT(&s->swatchdog), true, "realized", &err); 1118 if (err) { 1119 error_propagate(errp, err); 1120 return; 1121 } 1122 sysbus_connect_irq(SYS_BUS_DEVICE(&s->swatchdog), 0, 1123 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 1)); 1124 sysbus_mmio_map(SYS_BUS_DEVICE(&s->swatchdog), 0, 0x50081000); 1125 1126 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 1127 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); 1128 1129 object_property_set_int(splitter, 2, "num-lines", &err); 1130 if (err) { 1131 error_propagate(errp, err); 1132 return; 1133 } 1134 object_property_set_bool(splitter, true, "realized", &err); 1135 if (err) { 1136 error_propagate(errp, err); 1137 return; 1138 } 1139 } 1140 1141 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { 1142 char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); 1143 1144 armsse_forward_ppc(s, ppcname, i); 1145 g_free(ppcname); 1146 } 1147 1148 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { 1149 char *ppcname = g_strdup_printf("apb_ppcexp%d", i); 1150 1151 armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); 1152 g_free(ppcname); 1153 } 1154 1155 for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { 1156 /* Wire up IRQ splitter for internal PPCs */ 1157 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); 1158 char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", 1159 i - NUM_EXTERNAL_PPCS); 1160 TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; 1161 1162 qdev_connect_gpio_out(devs, 0, 1163 qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); 1164 qdev_connect_gpio_out(devs, 1, 1165 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); 1166 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, 1167 qdev_get_gpio_in(devs, 0)); 1168 g_free(gpioname); 1169 } 1170 1171 /* Wire up the splitters for the MPC IRQs */ 1172 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 1173 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 1174 DeviceState *dev_splitter = DEVICE(splitter); 1175 1176 object_property_set_int(OBJECT(splitter), 2, "num-lines", &err); 1177 if (err) { 1178 error_propagate(errp, err); 1179 return; 1180 } 1181 object_property_set_bool(OBJECT(splitter), true, "realized", &err); 1182 if (err) { 1183 error_propagate(errp, err); 1184 return; 1185 } 1186 1187 if (i < IOTS_NUM_EXP_MPC) { 1188 /* Splitter input is from GPIO input line */ 1189 s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0); 1190 qdev_connect_gpio_out(dev_splitter, 0, 1191 qdev_get_gpio_in_named(dev_secctl, 1192 "mpcexp_status", i)); 1193 } else { 1194 /* Splitter input is from our own MPC */ 1195 qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]), 1196 "irq", 0, 1197 qdev_get_gpio_in(dev_splitter, 0)); 1198 qdev_connect_gpio_out(dev_splitter, 0, 1199 qdev_get_gpio_in_named(dev_secctl, 1200 "mpc_status", 0)); 1201 } 1202 1203 qdev_connect_gpio_out(dev_splitter, 1, 1204 qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i)); 1205 } 1206 /* Create GPIO inputs which will pass the line state for our 1207 * mpcexp_irq inputs to the correct splitter devices. 1208 */ 1209 qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status", 1210 IOTS_NUM_EXP_MPC); 1211 1212 armsse_forward_sec_resp_cfg(s); 1213 1214 /* Forward the MSC related signals */ 1215 qdev_pass_gpios(dev_secctl, dev, "mscexp_status"); 1216 qdev_pass_gpios(dev_secctl, dev, "mscexp_clear"); 1217 qdev_pass_gpios(dev_secctl, dev, "mscexp_ns"); 1218 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, 1219 armsse_get_common_irq_in(s, 11)); 1220 1221 /* 1222 * Expose our container region to the board model; this corresponds 1223 * to the AHB Slave Expansion ports which allow bus master devices 1224 * (eg DMA controllers) in the board model to make transactions into 1225 * devices in the ARMSSE. 1226 */ 1227 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); 1228 1229 system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; 1230 } 1231 1232 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, 1233 int *iregion, bool *exempt, bool *ns, bool *nsc) 1234 { 1235 /* 1236 * For ARMSSE systems the IDAU responses are simple logical functions 1237 * of the address bits. The NSC attribute is guest-adjustable via the 1238 * NSCCFG register in the security controller. 1239 */ 1240 ARMSSE *s = ARMSSE(ii); 1241 int region = extract32(address, 28, 4); 1242 1243 *ns = !(region & 1); 1244 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); 1245 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1246 *exempt = (address & 0xeff00000) == 0xe0000000; 1247 *iregion = region; 1248 } 1249 1250 static const VMStateDescription armsse_vmstate = { 1251 .name = "iotkit", 1252 .version_id = 1, 1253 .minimum_version_id = 1, 1254 .fields = (VMStateField[]) { 1255 VMSTATE_UINT32(nsccfg, ARMSSE), 1256 VMSTATE_END_OF_LIST() 1257 } 1258 }; 1259 1260 static void armsse_reset(DeviceState *dev) 1261 { 1262 ARMSSE *s = ARMSSE(dev); 1263 1264 s->nsccfg = 0; 1265 } 1266 1267 static void armsse_class_init(ObjectClass *klass, void *data) 1268 { 1269 DeviceClass *dc = DEVICE_CLASS(klass); 1270 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); 1271 ARMSSEClass *asc = ARMSSE_CLASS(klass); 1272 const ARMSSEInfo *info = data; 1273 1274 dc->realize = armsse_realize; 1275 dc->vmsd = &armsse_vmstate; 1276 device_class_set_props(dc, info->props); 1277 dc->reset = armsse_reset; 1278 iic->check = armsse_idau_check; 1279 asc->info = info; 1280 } 1281 1282 static const TypeInfo armsse_info = { 1283 .name = TYPE_ARMSSE, 1284 .parent = TYPE_SYS_BUS_DEVICE, 1285 .instance_size = sizeof(ARMSSE), 1286 .instance_init = armsse_init, 1287 .abstract = true, 1288 .interfaces = (InterfaceInfo[]) { 1289 { TYPE_IDAU_INTERFACE }, 1290 { } 1291 } 1292 }; 1293 1294 static void armsse_register_types(void) 1295 { 1296 int i; 1297 1298 type_register_static(&armsse_info); 1299 1300 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) { 1301 TypeInfo ti = { 1302 .name = armsse_variants[i].name, 1303 .parent = TYPE_ARMSSE, 1304 .class_init = armsse_class_init, 1305 .class_data = (void *)&armsse_variants[i], 1306 }; 1307 type_register(&ti); 1308 } 1309 } 1310 1311 type_init(armsse_register_types); 1312