1 /* 2 * Arm SSE (Subsystems for Embedded): IoTKit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qemu/bitops.h" 16 #include "qapi/error.h" 17 #include "trace.h" 18 #include "hw/sysbus.h" 19 #include "migration/vmstate.h" 20 #include "hw/registerfields.h" 21 #include "hw/arm/armsse.h" 22 #include "hw/arm/armsse-version.h" 23 #include "hw/arm/boot.h" 24 #include "hw/irq.h" 25 #include "hw/qdev-clock.h" 26 27 /* 28 * The SSE-300 puts some devices in different places to the 29 * SSE-200 (and original IoTKit). We use an array of these structs 30 * to define how each variant lays out these devices. (Parts of the 31 * SoC that are the same for all variants aren't handled via these 32 * data structures.) 33 */ 34 35 #define NO_IRQ -1 36 #define NO_PPC -1 37 /* 38 * Special values for ARMSSEDeviceInfo::irq to indicate that this 39 * device uses one of the inputs to the OR gate that feeds into the 40 * CPU NMI input. 41 */ 42 #define NMI_0 10000 43 #define NMI_1 10001 44 45 typedef struct ARMSSEDeviceInfo { 46 const char *name; /* name to use for the QOM object; NULL terminates list */ 47 const char *type; /* QOM type name */ 48 unsigned int index; /* Which of the N devices of this type is this ? */ 49 hwaddr addr; 50 hwaddr size; /* only needed for TYPE_UNIMPLEMENTED_DEVICE */ 51 int ppc; /* Index of APB PPC this device is wired up to, or NO_PPC */ 52 int ppc_port; /* Port number of this device on the PPC */ 53 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */ 54 bool slowclk; /* true if device uses the slow 32KHz clock */ 55 } ARMSSEDeviceInfo; 56 57 struct ARMSSEInfo { 58 const char *name; 59 uint32_t sse_version; 60 int sram_banks; 61 int num_cpus; 62 uint32_t sys_version; 63 uint32_t iidr; 64 uint32_t cpuwait_rst; 65 bool has_mhus; 66 bool has_cachectrl; 67 bool has_cpusecctrl; 68 bool has_cpuid; 69 Property *props; 70 const ARMSSEDeviceInfo *devinfo; 71 }; 72 73 static Property iotkit_properties[] = { 74 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 75 MemoryRegion *), 76 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 77 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 78 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 79 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), 80 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), 81 DEFINE_PROP_END_OF_LIST() 82 }; 83 84 static Property armsse_properties[] = { 85 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 86 MemoryRegion *), 87 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 88 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 89 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 90 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), 91 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), 92 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), 93 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), 94 DEFINE_PROP_END_OF_LIST() 95 }; 96 97 static const ARMSSEDeviceInfo iotkit_devices[] = { 98 { 99 .name = "timer0", 100 .type = TYPE_CMSDK_APB_TIMER, 101 .index = 0, 102 .addr = 0x40000000, 103 .ppc = 0, 104 .ppc_port = 0, 105 .irq = 3, 106 }, 107 { 108 .name = "timer1", 109 .type = TYPE_CMSDK_APB_TIMER, 110 .index = 1, 111 .addr = 0x40001000, 112 .ppc = 0, 113 .ppc_port = 1, 114 .irq = 4, 115 }, 116 { 117 .name = "s32ktimer", 118 .type = TYPE_CMSDK_APB_TIMER, 119 .index = 2, 120 .addr = 0x4002f000, 121 .ppc = 1, 122 .ppc_port = 0, 123 .irq = 2, 124 .slowclk = true, 125 }, 126 { 127 .name = "dualtimer", 128 .type = TYPE_CMSDK_APB_DUALTIMER, 129 .index = 0, 130 .addr = 0x40002000, 131 .ppc = 0, 132 .ppc_port = 2, 133 .irq = 5, 134 }, 135 { 136 .name = "s32kwatchdog", 137 .type = TYPE_CMSDK_APB_WATCHDOG, 138 .index = 0, 139 .addr = 0x5002e000, 140 .ppc = NO_PPC, 141 .irq = NMI_0, 142 .slowclk = true, 143 }, 144 { 145 .name = "nswatchdog", 146 .type = TYPE_CMSDK_APB_WATCHDOG, 147 .index = 1, 148 .addr = 0x40081000, 149 .ppc = NO_PPC, 150 .irq = 1, 151 }, 152 { 153 .name = "swatchdog", 154 .type = TYPE_CMSDK_APB_WATCHDOG, 155 .index = 2, 156 .addr = 0x50081000, 157 .ppc = NO_PPC, 158 .irq = NMI_1, 159 }, 160 { 161 .name = "armsse-sysinfo", 162 .type = TYPE_IOTKIT_SYSINFO, 163 .index = 0, 164 .addr = 0x40020000, 165 .ppc = NO_PPC, 166 .irq = NO_IRQ, 167 }, 168 { 169 .name = "armsse-sysctl", 170 .type = TYPE_IOTKIT_SYSCTL, 171 .index = 0, 172 .addr = 0x50021000, 173 .ppc = NO_PPC, 174 .irq = NO_IRQ, 175 }, 176 { 177 .name = NULL, 178 } 179 }; 180 181 static const ARMSSEDeviceInfo sse200_devices[] = { 182 { 183 .name = "timer0", 184 .type = TYPE_CMSDK_APB_TIMER, 185 .index = 0, 186 .addr = 0x40000000, 187 .ppc = 0, 188 .ppc_port = 0, 189 .irq = 3, 190 }, 191 { 192 .name = "timer1", 193 .type = TYPE_CMSDK_APB_TIMER, 194 .index = 1, 195 .addr = 0x40001000, 196 .ppc = 0, 197 .ppc_port = 1, 198 .irq = 4, 199 }, 200 { 201 .name = "s32ktimer", 202 .type = TYPE_CMSDK_APB_TIMER, 203 .index = 2, 204 .addr = 0x4002f000, 205 .ppc = 1, 206 .ppc_port = 0, 207 .irq = 2, 208 .slowclk = true, 209 }, 210 { 211 .name = "dualtimer", 212 .type = TYPE_CMSDK_APB_DUALTIMER, 213 .index = 0, 214 .addr = 0x40002000, 215 .ppc = 0, 216 .ppc_port = 2, 217 .irq = 5, 218 }, 219 { 220 .name = "s32kwatchdog", 221 .type = TYPE_CMSDK_APB_WATCHDOG, 222 .index = 0, 223 .addr = 0x5002e000, 224 .ppc = NO_PPC, 225 .irq = NMI_0, 226 .slowclk = true, 227 }, 228 { 229 .name = "nswatchdog", 230 .type = TYPE_CMSDK_APB_WATCHDOG, 231 .index = 1, 232 .addr = 0x40081000, 233 .ppc = NO_PPC, 234 .irq = 1, 235 }, 236 { 237 .name = "swatchdog", 238 .type = TYPE_CMSDK_APB_WATCHDOG, 239 .index = 2, 240 .addr = 0x50081000, 241 .ppc = NO_PPC, 242 .irq = NMI_1, 243 }, 244 { 245 .name = "armsse-sysinfo", 246 .type = TYPE_IOTKIT_SYSINFO, 247 .index = 0, 248 .addr = 0x40020000, 249 .ppc = NO_PPC, 250 .irq = NO_IRQ, 251 }, 252 { 253 .name = "armsse-sysctl", 254 .type = TYPE_IOTKIT_SYSCTL, 255 .index = 0, 256 .addr = 0x50021000, 257 .ppc = NO_PPC, 258 .irq = NO_IRQ, 259 }, 260 { 261 .name = "CPU0CORE_PPU", 262 .type = TYPE_UNIMPLEMENTED_DEVICE, 263 .index = 0, 264 .addr = 0x50023000, 265 .size = 0x1000, 266 .ppc = NO_PPC, 267 .irq = NO_IRQ, 268 }, 269 { 270 .name = "CPU1CORE_PPU", 271 .type = TYPE_UNIMPLEMENTED_DEVICE, 272 .index = 1, 273 .addr = 0x50025000, 274 .size = 0x1000, 275 .ppc = NO_PPC, 276 .irq = NO_IRQ, 277 }, 278 { 279 .name = "DBG_PPU", 280 .type = TYPE_UNIMPLEMENTED_DEVICE, 281 .index = 2, 282 .addr = 0x50029000, 283 .size = 0x1000, 284 .ppc = NO_PPC, 285 .irq = NO_IRQ, 286 }, 287 { 288 .name = "RAM0_PPU", 289 .type = TYPE_UNIMPLEMENTED_DEVICE, 290 .index = 3, 291 .addr = 0x5002a000, 292 .size = 0x1000, 293 .ppc = NO_PPC, 294 .irq = NO_IRQ, 295 }, 296 { 297 .name = "RAM1_PPU", 298 .type = TYPE_UNIMPLEMENTED_DEVICE, 299 .index = 4, 300 .addr = 0x5002b000, 301 .size = 0x1000, 302 .ppc = NO_PPC, 303 .irq = NO_IRQ, 304 }, 305 { 306 .name = "RAM2_PPU", 307 .type = TYPE_UNIMPLEMENTED_DEVICE, 308 .index = 5, 309 .addr = 0x5002c000, 310 .size = 0x1000, 311 .ppc = NO_PPC, 312 .irq = NO_IRQ, 313 }, 314 { 315 .name = "RAM3_PPU", 316 .type = TYPE_UNIMPLEMENTED_DEVICE, 317 .index = 6, 318 .addr = 0x5002d000, 319 .size = 0x1000, 320 .ppc = NO_PPC, 321 .irq = NO_IRQ, 322 }, 323 { 324 .name = "SYS_PPU", 325 .type = TYPE_UNIMPLEMENTED_DEVICE, 326 .index = 7, 327 .addr = 0x50022000, 328 .size = 0x1000, 329 .ppc = NO_PPC, 330 .irq = NO_IRQ, 331 }, 332 { 333 .name = NULL, 334 } 335 }; 336 337 static const ARMSSEInfo armsse_variants[] = { 338 { 339 .name = TYPE_IOTKIT, 340 .sse_version = ARMSSE_IOTKIT, 341 .sram_banks = 1, 342 .num_cpus = 1, 343 .sys_version = 0x41743, 344 .iidr = 0, 345 .cpuwait_rst = 0, 346 .has_mhus = false, 347 .has_cachectrl = false, 348 .has_cpusecctrl = false, 349 .has_cpuid = false, 350 .props = iotkit_properties, 351 .devinfo = iotkit_devices, 352 }, 353 { 354 .name = TYPE_SSE200, 355 .sse_version = ARMSSE_SSE200, 356 .sram_banks = 4, 357 .num_cpus = 2, 358 .sys_version = 0x22041743, 359 .iidr = 0, 360 .cpuwait_rst = 2, 361 .has_mhus = true, 362 .has_cachectrl = true, 363 .has_cpusecctrl = true, 364 .has_cpuid = true, 365 .props = armsse_properties, 366 .devinfo = sse200_devices, 367 }, 368 }; 369 370 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) 371 { 372 /* Return the SYS_CONFIG value for this SSE */ 373 uint32_t sys_config; 374 375 switch (info->sse_version) { 376 case ARMSSE_IOTKIT: 377 sys_config = 0; 378 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 379 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); 380 break; 381 case ARMSSE_SSE200: 382 sys_config = 0; 383 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 384 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 385 sys_config = deposit32(sys_config, 24, 4, 2); 386 if (info->num_cpus > 1) { 387 sys_config = deposit32(sys_config, 10, 1, 1); 388 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1); 389 sys_config = deposit32(sys_config, 28, 4, 2); 390 } 391 break; 392 case ARMSSE_SSE300: 393 sys_config = 0; 394 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 395 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 396 sys_config = deposit32(sys_config, 16, 3, 3); /* CPU0 = Cortex-M55 */ 397 break; 398 default: 399 g_assert_not_reached(); 400 } 401 return sys_config; 402 } 403 404 /* Clock frequency in HZ of the 32KHz "slow clock" */ 405 #define S32KCLK (32 * 1000) 406 407 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ 408 static bool irq_is_common[32] = { 409 [0 ... 5] = true, 410 /* 6, 7: per-CPU MHU interrupts */ 411 [8 ... 12] = true, 412 /* 13: per-CPU icache interrupt */ 413 /* 14: reserved */ 414 [15 ... 20] = true, 415 /* 21: reserved */ 416 [22 ... 26] = true, 417 /* 27: reserved */ 418 /* 28, 29: per-CPU CTI interrupts */ 419 /* 30, 31: reserved */ 420 }; 421 422 /* 423 * Create an alias region in @container of @size bytes starting at @base 424 * which mirrors the memory starting at @orig. 425 */ 426 static void make_alias(ARMSSE *s, MemoryRegion *mr, MemoryRegion *container, 427 const char *name, hwaddr base, hwaddr size, hwaddr orig) 428 { 429 memory_region_init_alias(mr, NULL, name, container, orig, size); 430 /* The alias is even lower priority than unimplemented_device regions */ 431 memory_region_add_subregion_overlap(container, base, mr, -1500); 432 } 433 434 static void irq_status_forwarder(void *opaque, int n, int level) 435 { 436 qemu_irq destirq = opaque; 437 438 qemu_set_irq(destirq, level); 439 } 440 441 static void nsccfg_handler(void *opaque, int n, int level) 442 { 443 ARMSSE *s = ARM_SSE(opaque); 444 445 s->nsccfg = level; 446 } 447 448 static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) 449 { 450 /* Each of the 4 AHB and 4 APB PPCs that might be present in a 451 * system using the ARMSSE has a collection of control lines which 452 * are provided by the security controller and which we want to 453 * expose as control lines on the ARMSSE device itself, so the 454 * code using the ARMSSE can wire them up to the PPCs. 455 */ 456 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; 457 DeviceState *armssedev = DEVICE(s); 458 DeviceState *dev_secctl = DEVICE(&s->secctl); 459 DeviceState *dev_splitter = DEVICE(splitter); 460 char *name; 461 462 name = g_strdup_printf("%s_nonsec", ppcname); 463 qdev_pass_gpios(dev_secctl, armssedev, name); 464 g_free(name); 465 name = g_strdup_printf("%s_ap", ppcname); 466 qdev_pass_gpios(dev_secctl, armssedev, name); 467 g_free(name); 468 name = g_strdup_printf("%s_irq_enable", ppcname); 469 qdev_pass_gpios(dev_secctl, armssedev, name); 470 g_free(name); 471 name = g_strdup_printf("%s_irq_clear", ppcname); 472 qdev_pass_gpios(dev_secctl, armssedev, name); 473 g_free(name); 474 475 /* irq_status is a little more tricky, because we need to 476 * split it so we can send it both to the security controller 477 * and to our OR gate for the NVIC interrupt line. 478 * Connect up the splitter's outputs, and create a GPIO input 479 * which will pass the line state to the input splitter. 480 */ 481 name = g_strdup_printf("%s_irq_status", ppcname); 482 qdev_connect_gpio_out(dev_splitter, 0, 483 qdev_get_gpio_in_named(dev_secctl, 484 name, 0)); 485 qdev_connect_gpio_out(dev_splitter, 1, 486 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); 487 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); 488 qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder, 489 s->irq_status_in[ppcnum], name, 1); 490 g_free(name); 491 } 492 493 static void armsse_forward_sec_resp_cfg(ARMSSE *s) 494 { 495 /* Forward the 3rd output from the splitter device as a 496 * named GPIO output of the armsse object. 497 */ 498 DeviceState *dev = DEVICE(s); 499 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); 500 501 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); 502 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, 503 s->sec_resp_cfg, 1); 504 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); 505 } 506 507 static void armsse_mainclk_update(void *opaque, ClockEvent event) 508 { 509 ARMSSE *s = ARM_SSE(opaque); 510 511 /* 512 * Set system_clock_scale from our Clock input; this is what 513 * controls the tick rate of the CPU SysTick timer. 514 */ 515 system_clock_scale = clock_ticks_to_ns(s->mainclk, 1); 516 } 517 518 static void armsse_init(Object *obj) 519 { 520 ARMSSE *s = ARM_SSE(obj); 521 ARMSSEClass *asc = ARM_SSE_GET_CLASS(obj); 522 const ARMSSEInfo *info = asc->info; 523 const ARMSSEDeviceInfo *devinfo; 524 int i; 525 526 assert(info->sram_banks <= MAX_SRAM_BANKS); 527 assert(info->num_cpus <= SSE_MAX_CPUS); 528 529 s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", 530 armsse_mainclk_update, s, ClockUpdate); 531 s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0); 532 533 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); 534 535 for (i = 0; i < info->num_cpus; i++) { 536 /* 537 * We put each CPU in its own cluster as they are logically 538 * distinct and may be configured differently. 539 */ 540 char *name; 541 542 name = g_strdup_printf("cluster%d", i); 543 object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER); 544 qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); 545 g_free(name); 546 547 name = g_strdup_printf("armv7m%d", i); 548 object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i], 549 TYPE_ARMV7M); 550 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", 551 ARM_CPU_TYPE_NAME("cortex-m33")); 552 g_free(name); 553 name = g_strdup_printf("arm-sse-cpu-container%d", i); 554 memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); 555 g_free(name); 556 if (i > 0) { 557 name = g_strdup_printf("arm-sse-container-alias%d", i); 558 memory_region_init_alias(&s->container_alias[i - 1], obj, 559 name, &s->container, 0, UINT64_MAX); 560 g_free(name); 561 } 562 } 563 564 for (devinfo = info->devinfo; devinfo->name; devinfo++) { 565 assert(devinfo->ppc == NO_PPC || devinfo->ppc < ARRAY_SIZE(s->apb_ppc)); 566 if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) { 567 assert(devinfo->index < ARRAY_SIZE(s->timer)); 568 object_initialize_child(obj, devinfo->name, 569 &s->timer[devinfo->index], 570 TYPE_CMSDK_APB_TIMER); 571 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_DUALTIMER)) { 572 assert(devinfo->index == 0); 573 object_initialize_child(obj, devinfo->name, &s->dualtimer, 574 TYPE_CMSDK_APB_DUALTIMER); 575 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) { 576 assert(devinfo->index < ARRAY_SIZE(s->cmsdk_watchdog)); 577 object_initialize_child(obj, devinfo->name, 578 &s->cmsdk_watchdog[devinfo->index], 579 TYPE_CMSDK_APB_WATCHDOG); 580 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSINFO)) { 581 assert(devinfo->index == 0); 582 object_initialize_child(obj, devinfo->name, &s->sysinfo, 583 TYPE_IOTKIT_SYSINFO); 584 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSCTL)) { 585 assert(devinfo->index == 0); 586 object_initialize_child(obj, devinfo->name, &s->sysctl, 587 TYPE_IOTKIT_SYSCTL); 588 } else if (!strcmp(devinfo->type, TYPE_UNIMPLEMENTED_DEVICE)) { 589 assert(devinfo->index < ARRAY_SIZE(s->unimp)); 590 object_initialize_child(obj, devinfo->name, 591 &s->unimp[devinfo->index], 592 TYPE_UNIMPLEMENTED_DEVICE); 593 } else { 594 g_assert_not_reached(); 595 } 596 } 597 598 object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL); 599 600 for (i = 0; i < ARRAY_SIZE(s->apb_ppc); i++) { 601 g_autofree char *name = g_strdup_printf("apb-ppc%d", i); 602 object_initialize_child(obj, name, &s->apb_ppc[i], TYPE_TZ_PPC); 603 } 604 605 for (i = 0; i < info->sram_banks; i++) { 606 char *name = g_strdup_printf("mpc%d", i); 607 object_initialize_child(obj, name, &s->mpc[i], TYPE_TZ_MPC); 608 g_free(name); 609 } 610 object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate, 611 TYPE_OR_IRQ); 612 613 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 614 char *name = g_strdup_printf("mpc-irq-splitter-%d", i); 615 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 616 617 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 618 g_free(name); 619 } 620 621 if (info->has_mhus) { 622 object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); 623 object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); 624 } 625 if (info->has_cachectrl) { 626 for (i = 0; i < info->num_cpus; i++) { 627 char *name = g_strdup_printf("cachectrl%d", i); 628 629 object_initialize_child(obj, name, &s->cachectrl[i], 630 TYPE_UNIMPLEMENTED_DEVICE); 631 g_free(name); 632 } 633 } 634 if (info->has_cpusecctrl) { 635 for (i = 0; i < info->num_cpus; i++) { 636 char *name = g_strdup_printf("cpusecctrl%d", i); 637 638 object_initialize_child(obj, name, &s->cpusecctrl[i], 639 TYPE_UNIMPLEMENTED_DEVICE); 640 g_free(name); 641 } 642 } 643 if (info->has_cpuid) { 644 for (i = 0; i < info->num_cpus; i++) { 645 char *name = g_strdup_printf("cpuid%d", i); 646 647 object_initialize_child(obj, name, &s->cpuid[i], 648 TYPE_ARMSSE_CPUID); 649 g_free(name); 650 } 651 } 652 object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ); 653 object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, 654 TYPE_OR_IRQ); 655 object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter, 656 TYPE_SPLIT_IRQ); 657 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 658 char *name = g_strdup_printf("ppc-irq-splitter-%d", i); 659 SplitIRQ *splitter = &s->ppc_irq_splitter[i]; 660 661 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 662 g_free(name); 663 } 664 if (info->num_cpus > 1) { 665 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 666 if (irq_is_common[i]) { 667 char *name = g_strdup_printf("cpu-irq-splitter%d", i); 668 SplitIRQ *splitter = &s->cpu_irq_splitter[i]; 669 670 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 671 g_free(name); 672 } 673 } 674 } 675 } 676 677 static void armsse_exp_irq(void *opaque, int n, int level) 678 { 679 qemu_irq *irqarray = opaque; 680 681 qemu_set_irq(irqarray[n], level); 682 } 683 684 static void armsse_mpcexp_status(void *opaque, int n, int level) 685 { 686 ARMSSE *s = ARM_SSE(opaque); 687 qemu_set_irq(s->mpcexp_status_in[n], level); 688 } 689 690 static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno) 691 { 692 /* 693 * Return a qemu_irq which can be used to signal IRQ n to 694 * all CPUs in the SSE. 695 */ 696 ARMSSEClass *asc = ARM_SSE_GET_CLASS(s); 697 const ARMSSEInfo *info = asc->info; 698 699 assert(irq_is_common[irqno]); 700 701 if (info->num_cpus == 1) { 702 /* Only one CPU -- just connect directly to it */ 703 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); 704 } else { 705 /* Connect to the splitter which feeds all CPUs */ 706 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); 707 } 708 } 709 710 static void armsse_realize(DeviceState *dev, Error **errp) 711 { 712 ARMSSE *s = ARM_SSE(dev); 713 ARMSSEClass *asc = ARM_SSE_GET_CLASS(dev); 714 const ARMSSEInfo *info = asc->info; 715 const ARMSSEDeviceInfo *devinfo; 716 int i; 717 MemoryRegion *mr; 718 Error *err = NULL; 719 SysBusDevice *sbd_apb_ppc0; 720 SysBusDevice *sbd_secctl; 721 DeviceState *dev_apb_ppc0; 722 DeviceState *dev_apb_ppc1; 723 DeviceState *dev_secctl; 724 DeviceState *dev_splitter; 725 uint32_t addr_width_max; 726 727 if (!s->board_memory) { 728 error_setg(errp, "memory property was not set"); 729 return; 730 } 731 732 if (!clock_has_source(s->mainclk)) { 733 error_setg(errp, "MAINCLK clock was not connected"); 734 } 735 if (!clock_has_source(s->s32kclk)) { 736 error_setg(errp, "S32KCLK clock was not connected"); 737 } 738 739 assert(info->num_cpus <= SSE_MAX_CPUS); 740 741 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ 742 assert(is_power_of_2(info->sram_banks)); 743 addr_width_max = 24 - ctz32(info->sram_banks); 744 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { 745 error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d", 746 addr_width_max); 747 return; 748 } 749 750 /* Handling of which devices should be available only to secure 751 * code is usually done differently for M profile than for A profile. 752 * Instead of putting some devices only into the secure address space, 753 * devices exist in both address spaces but with hard-wired security 754 * permissions that will cause the CPU to fault for non-secure accesses. 755 * 756 * The ARMSSE has an IDAU (Implementation Defined Access Unit), 757 * which specifies hard-wired security permissions for different 758 * areas of the physical address space. For the ARMSSE IDAU, the 759 * top 4 bits of the physical address are the IDAU region ID, and 760 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS 761 * region, otherwise it is an S region. 762 * 763 * The various devices and RAMs are generally all mapped twice, 764 * once into a region that the IDAU defines as secure and once 765 * into a non-secure region. They sit behind either a Memory 766 * Protection Controller (for RAM) or a Peripheral Protection 767 * Controller (for devices), which allow a more fine grained 768 * configuration of whether non-secure accesses are permitted. 769 * 770 * (The other place that guest software can configure security 771 * permissions is in the architected SAU (Security Attribution 772 * Unit), which is entirely inside the CPU. The IDAU can upgrade 773 * the security attributes for a region to more restrictive than 774 * the SAU specifies, but cannot downgrade them.) 775 * 776 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff 777 * 0x20000000..0x2007ffff 32KB FPGA block RAM 778 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff 779 * 0x40000000..0x4000ffff base peripheral region 1 780 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) 781 * 0x40020000..0x4002ffff system control element peripherals 782 * 0x40080000..0x400fffff base peripheral region 2 783 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff 784 */ 785 786 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); 787 788 for (i = 0; i < info->num_cpus; i++) { 789 DeviceState *cpudev = DEVICE(&s->armv7m[i]); 790 Object *cpuobj = OBJECT(&s->armv7m[i]); 791 int j; 792 char *gpioname; 793 794 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IRQS); 795 /* 796 * In real hardware the initial Secure VTOR is set from the INITSVTOR* 797 * registers in the IoT Kit System Control Register block. In QEMU 798 * we set the initial value here, and also the reset value of the 799 * sysctl register, from this object's QOM init-svtor property. 800 * If the guest changes the INITSVTOR* registers at runtime then the 801 * code in iotkit-sysctl.c will update the CPU init-svtor property 802 * (which will then take effect on the next CPU warm-reset). 803 * 804 * Note that typically a board using the SSE-200 will have a system 805 * control processor whose boot firmware initializes the INITSVTOR* 806 * registers before powering up the CPUs. QEMU doesn't emulate 807 * the control processor, so instead we behave in the way that the 808 * firmware does: the initial value should be set by the board code 809 * (using the init-svtor property on the ARMSSE object) to match 810 * whatever its firmware does. 811 */ 812 qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); 813 /* 814 * CPUs start powered down if the corresponding bit in the CPUWAIT 815 * register is 1. In real hardware the CPUWAIT register reset value is 816 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and 817 * CPUWAIT1_RST parameters), but since all the boards we care about 818 * start CPU0 and leave CPU1 powered off, we hard-code that in 819 * info->cpuwait_rst for now. We can add QOM properties for this 820 * later if necessary. 821 */ 822 if (extract32(info->cpuwait_rst, i, 1)) { 823 if (!object_property_set_bool(cpuobj, "start-powered-off", true, 824 errp)) { 825 return; 826 } 827 } 828 if (!s->cpu_fpu[i]) { 829 if (!object_property_set_bool(cpuobj, "vfp", false, errp)) { 830 return; 831 } 832 } 833 if (!s->cpu_dsp[i]) { 834 if (!object_property_set_bool(cpuobj, "dsp", false, errp)) { 835 return; 836 } 837 } 838 839 if (i > 0) { 840 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 841 &s->container_alias[i - 1], -1); 842 } else { 843 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 844 &s->container, -1); 845 } 846 object_property_set_link(cpuobj, "memory", 847 OBJECT(&s->cpu_container[i]), &error_abort); 848 object_property_set_link(cpuobj, "idau", OBJECT(s), &error_abort); 849 if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj), errp)) { 850 return; 851 } 852 /* 853 * The cluster must be realized after the armv7m container, as 854 * the container's CPU object is only created on realize, and the 855 * CPU must exist and have been parented into the cluster before 856 * the cluster is realized. 857 */ 858 if (!qdev_realize(DEVICE(&s->cluster[i]), NULL, errp)) { 859 return; 860 } 861 862 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ 863 s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); 864 for (j = 0; j < s->exp_numirq; j++) { 865 s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + NUM_SSE_IRQS); 866 } 867 if (i == 0) { 868 gpioname = g_strdup("EXP_IRQ"); 869 } else { 870 gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i); 871 } 872 qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq, 873 s->exp_irqs[i], 874 gpioname, s->exp_numirq); 875 g_free(gpioname); 876 } 877 878 /* Wire up the splitters that connect common IRQs to all CPUs */ 879 if (info->num_cpus > 1) { 880 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 881 if (irq_is_common[i]) { 882 Object *splitter = OBJECT(&s->cpu_irq_splitter[i]); 883 DeviceState *devs = DEVICE(splitter); 884 int cpunum; 885 886 if (!object_property_set_int(splitter, "num-lines", 887 info->num_cpus, errp)) { 888 return; 889 } 890 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 891 return; 892 } 893 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 894 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 895 896 qdev_connect_gpio_out(devs, cpunum, 897 qdev_get_gpio_in(cpudev, i)); 898 } 899 } 900 } 901 } 902 903 /* Set up the big aliases first */ 904 make_alias(s, &s->alias1, &s->container, "alias 1", 905 0x10000000, 0x10000000, 0x00000000); 906 make_alias(s, &s->alias2, &s->container, 907 "alias 2", 0x30000000, 0x10000000, 0x20000000); 908 /* The 0x50000000..0x5fffffff region is not a pure alias: it has 909 * a few extra devices that only appear there (generally the 910 * control interfaces for the protection controllers). 911 * We implement this by mapping those devices over the top of this 912 * alias MR at a higher priority. Some of the devices in this range 913 * are per-CPU, so we must put this alias in the per-cpu containers. 914 */ 915 for (i = 0; i < info->num_cpus; i++) { 916 make_alias(s, &s->alias3[i], &s->cpu_container[i], 917 "alias 3", 0x50000000, 0x10000000, 0x40000000); 918 } 919 920 /* Security controller */ 921 object_property_set_int(OBJECT(&s->secctl), "sse-version", 922 info->sse_version, &error_abort); 923 if (!sysbus_realize(SYS_BUS_DEVICE(&s->secctl), errp)) { 924 return; 925 } 926 sbd_secctl = SYS_BUS_DEVICE(&s->secctl); 927 dev_secctl = DEVICE(&s->secctl); 928 sysbus_mmio_map(sbd_secctl, 0, 0x50080000); 929 sysbus_mmio_map(sbd_secctl, 1, 0x40080000); 930 931 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); 932 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); 933 934 /* The sec_resp_cfg output from the security controller must be split into 935 * multiple lines, one for each of the PPCs within the ARMSSE and one 936 * that will be an output from the ARMSSE to the system. 937 */ 938 if (!object_property_set_int(OBJECT(&s->sec_resp_splitter), 939 "num-lines", 3, errp)) { 940 return; 941 } 942 if (!qdev_realize(DEVICE(&s->sec_resp_splitter), NULL, errp)) { 943 return; 944 } 945 dev_splitter = DEVICE(&s->sec_resp_splitter); 946 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, 947 qdev_get_gpio_in(dev_splitter, 0)); 948 949 /* Each SRAM bank lives behind its own Memory Protection Controller */ 950 for (i = 0; i < info->sram_banks; i++) { 951 char *ramname = g_strdup_printf("armsse.sram%d", i); 952 SysBusDevice *sbd_mpc; 953 uint32_t sram_bank_size = 1 << s->sram_addr_width; 954 955 memory_region_init_ram(&s->sram[i], NULL, ramname, 956 sram_bank_size, &err); 957 g_free(ramname); 958 if (err) { 959 error_propagate(errp, err); 960 return; 961 } 962 object_property_set_link(OBJECT(&s->mpc[i]), "downstream", 963 OBJECT(&s->sram[i]), &error_abort); 964 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mpc[i]), errp)) { 965 return; 966 } 967 /* Map the upstream end of the MPC into the right place... */ 968 sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); 969 memory_region_add_subregion(&s->container, 970 0x20000000 + i * sram_bank_size, 971 sysbus_mmio_get_region(sbd_mpc, 1)); 972 /* ...and its register interface */ 973 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, 974 sysbus_mmio_get_region(sbd_mpc, 0)); 975 } 976 977 /* We must OR together lines from the MPC splitters to go to the NVIC */ 978 if (!object_property_set_int(OBJECT(&s->mpc_irq_orgate), "num-lines", 979 IOTS_NUM_EXP_MPC + info->sram_banks, 980 errp)) { 981 return; 982 } 983 if (!qdev_realize(DEVICE(&s->mpc_irq_orgate), NULL, errp)) { 984 return; 985 } 986 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, 987 armsse_get_common_irq_in(s, 9)); 988 989 /* This OR gate wires together outputs from the secure watchdogs to NMI */ 990 if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2, 991 errp)) { 992 return; 993 } 994 if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) { 995 return; 996 } 997 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, 998 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); 999 1000 /* Devices behind APB PPC0: 1001 * 0x40000000: timer0 1002 * 0x40001000: timer1 1003 * 0x40002000: dual timer 1004 * 0x40003000: MHU0 (SSE-200 only) 1005 * 0x40004000: MHU1 (SSE-200 only) 1006 * We must configure and realize each downstream device and connect 1007 * it to the appropriate PPC port; then we can realize the PPC and 1008 * map its upstream ends to the right place in the container. 1009 */ 1010 for (devinfo = info->devinfo; devinfo->name; devinfo++) { 1011 SysBusDevice *sbd; 1012 qemu_irq irq; 1013 1014 if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) { 1015 sbd = SYS_BUS_DEVICE(&s->timer[devinfo->index]); 1016 1017 qdev_connect_clock_in(DEVICE(sbd), "pclk", 1018 devinfo->slowclk ? s->s32kclk : s->mainclk); 1019 if (!sysbus_realize(sbd, errp)) { 1020 return; 1021 } 1022 mr = sysbus_mmio_get_region(sbd, 0); 1023 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_DUALTIMER)) { 1024 sbd = SYS_BUS_DEVICE(&s->dualtimer); 1025 1026 qdev_connect_clock_in(DEVICE(sbd), "TIMCLK", s->mainclk); 1027 if (!sysbus_realize(sbd, errp)) { 1028 return; 1029 } 1030 mr = sysbus_mmio_get_region(sbd, 0); 1031 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) { 1032 sbd = SYS_BUS_DEVICE(&s->cmsdk_watchdog[devinfo->index]); 1033 1034 qdev_connect_clock_in(DEVICE(sbd), "WDOGCLK", 1035 devinfo->slowclk ? s->s32kclk : s->mainclk); 1036 if (!sysbus_realize(sbd, errp)) { 1037 return; 1038 } 1039 mr = sysbus_mmio_get_region(sbd, 0); 1040 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSINFO)) { 1041 sbd = SYS_BUS_DEVICE(&s->sysinfo); 1042 1043 object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION", 1044 info->sys_version, &error_abort); 1045 object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG", 1046 armsse_sys_config_value(s, info), 1047 &error_abort); 1048 object_property_set_int(OBJECT(&s->sysinfo), "sse-version", 1049 info->sse_version, &error_abort); 1050 object_property_set_int(OBJECT(&s->sysinfo), "IIDR", 1051 info->iidr, &error_abort); 1052 if (!sysbus_realize(sbd, errp)) { 1053 return; 1054 } 1055 mr = sysbus_mmio_get_region(sbd, 0); 1056 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSCTL)) { 1057 /* System control registers */ 1058 sbd = SYS_BUS_DEVICE(&s->sysctl); 1059 1060 object_property_set_int(OBJECT(&s->sysctl), "sse-version", 1061 info->sse_version, &error_abort); 1062 object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST", 1063 info->cpuwait_rst, &error_abort); 1064 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST", 1065 s->init_svtor, &error_abort); 1066 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST", 1067 s->init_svtor, &error_abort); 1068 if (!sysbus_realize(sbd, errp)) { 1069 return; 1070 } 1071 mr = sysbus_mmio_get_region(sbd, 0); 1072 } else if (!strcmp(devinfo->type, TYPE_UNIMPLEMENTED_DEVICE)) { 1073 sbd = SYS_BUS_DEVICE(&s->unimp[devinfo->index]); 1074 1075 qdev_prop_set_string(DEVICE(sbd), "name", devinfo->name); 1076 qdev_prop_set_uint64(DEVICE(sbd), "size", devinfo->size); 1077 if (!sysbus_realize(sbd, errp)) { 1078 return; 1079 } 1080 mr = sysbus_mmio_get_region(sbd, 0); 1081 } else { 1082 g_assert_not_reached(); 1083 } 1084 1085 switch (devinfo->irq) { 1086 case NO_IRQ: 1087 irq = NULL; 1088 break; 1089 case 0 ... NUM_SSE_IRQS - 1: 1090 irq = armsse_get_common_irq_in(s, devinfo->irq); 1091 break; 1092 case NMI_0: 1093 case NMI_1: 1094 irq = qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 1095 devinfo->irq - NMI_0); 1096 break; 1097 default: 1098 g_assert_not_reached(); 1099 } 1100 1101 if (irq) { 1102 sysbus_connect_irq(sbd, 0, irq); 1103 } 1104 1105 /* 1106 * Devices connected to a PPC are connected to the port here; 1107 * we will map the upstream end of that port to the right address 1108 * in the container later after the PPC has been realized. 1109 * Devices not connected to a PPC can be mapped immediately. 1110 */ 1111 if (devinfo->ppc != NO_PPC) { 1112 TZPPC *ppc = &s->apb_ppc[devinfo->ppc]; 1113 g_autofree char *portname = g_strdup_printf("port[%d]", 1114 devinfo->ppc_port); 1115 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), 1116 &error_abort); 1117 } else { 1118 memory_region_add_subregion(&s->container, devinfo->addr, mr); 1119 } 1120 } 1121 1122 if (info->has_mhus) { 1123 /* 1124 * An SSE-200 with only one CPU should have only one MHU created, 1125 * with the region where the second MHU usually is being RAZ/WI. 1126 * We don't implement that SSE-200 config; if we want to support 1127 * it then this code needs to be enhanced to handle creating the 1128 * RAZ/WI region instead of the second MHU. 1129 */ 1130 assert(info->num_cpus == ARRAY_SIZE(s->mhu)); 1131 1132 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { 1133 char *port; 1134 int cpunum; 1135 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]); 1136 1137 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mhu[i]), errp)) { 1138 return; 1139 } 1140 port = g_strdup_printf("port[%d]", i + 3); 1141 mr = sysbus_mmio_get_region(mhu_sbd, 0); 1142 object_property_set_link(OBJECT(&s->apb_ppc[0]), port, OBJECT(mr), 1143 &error_abort); 1144 g_free(port); 1145 1146 /* 1147 * Each MHU has an irq line for each CPU: 1148 * MHU 0 irq line 0 -> CPU 0 IRQ 6 1149 * MHU 0 irq line 1 -> CPU 1 IRQ 6 1150 * MHU 1 irq line 0 -> CPU 0 IRQ 7 1151 * MHU 1 irq line 1 -> CPU 1 IRQ 7 1152 */ 1153 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 1154 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 1155 1156 sysbus_connect_irq(mhu_sbd, cpunum, 1157 qdev_get_gpio_in(cpudev, 6 + i)); 1158 } 1159 } 1160 } 1161 1162 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[0]), errp)) { 1163 return; 1164 } 1165 1166 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc[0]); 1167 dev_apb_ppc0 = DEVICE(&s->apb_ppc[0]); 1168 1169 if (info->has_mhus) { 1170 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3); 1171 memory_region_add_subregion(&s->container, 0x40003000, mr); 1172 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4); 1173 memory_region_add_subregion(&s->container, 0x40004000, mr); 1174 } 1175 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { 1176 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, 1177 qdev_get_gpio_in_named(dev_apb_ppc0, 1178 "cfg_nonsec", i)); 1179 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, 1180 qdev_get_gpio_in_named(dev_apb_ppc0, 1181 "cfg_ap", i)); 1182 } 1183 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, 1184 qdev_get_gpio_in_named(dev_apb_ppc0, 1185 "irq_enable", 0)); 1186 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, 1187 qdev_get_gpio_in_named(dev_apb_ppc0, 1188 "irq_clear", 0)); 1189 qdev_connect_gpio_out(dev_splitter, 0, 1190 qdev_get_gpio_in_named(dev_apb_ppc0, 1191 "cfg_sec_resp", 0)); 1192 1193 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external 1194 * ones) are sent individually to the security controller, and also 1195 * ORed together to give a single combined PPC interrupt to the NVIC. 1196 */ 1197 if (!object_property_set_int(OBJECT(&s->ppc_irq_orgate), 1198 "num-lines", NUM_PPCS, errp)) { 1199 return; 1200 } 1201 if (!qdev_realize(DEVICE(&s->ppc_irq_orgate), NULL, errp)) { 1202 return; 1203 } 1204 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, 1205 armsse_get_common_irq_in(s, 10)); 1206 1207 /* 1208 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): 1209 * private per-CPU region (all these devices are SSE-200 only): 1210 * 0x50010000: L1 icache control registers 1211 * 0x50011000: CPUSECCTRL (CPU local security control registers) 1212 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block 1213 */ 1214 if (info->has_cachectrl) { 1215 for (i = 0; i < info->num_cpus; i++) { 1216 char *name = g_strdup_printf("cachectrl%d", i); 1217 MemoryRegion *mr; 1218 1219 qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); 1220 g_free(name); 1221 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); 1222 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cachectrl[i]), errp)) { 1223 return; 1224 } 1225 1226 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); 1227 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); 1228 } 1229 } 1230 if (info->has_cpusecctrl) { 1231 for (i = 0; i < info->num_cpus; i++) { 1232 char *name = g_strdup_printf("CPUSECCTRL%d", i); 1233 MemoryRegion *mr; 1234 1235 qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); 1236 g_free(name); 1237 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); 1238 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpusecctrl[i]), errp)) { 1239 return; 1240 } 1241 1242 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); 1243 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); 1244 } 1245 } 1246 if (info->has_cpuid) { 1247 for (i = 0; i < info->num_cpus; i++) { 1248 MemoryRegion *mr; 1249 1250 qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); 1251 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpuid[i]), errp)) { 1252 return; 1253 } 1254 1255 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); 1256 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); 1257 } 1258 } 1259 1260 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[1]), errp)) { 1261 return; 1262 } 1263 1264 dev_apb_ppc1 = DEVICE(&s->apb_ppc[1]); 1265 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, 1266 qdev_get_gpio_in_named(dev_apb_ppc1, 1267 "cfg_nonsec", 0)); 1268 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, 1269 qdev_get_gpio_in_named(dev_apb_ppc1, 1270 "cfg_ap", 0)); 1271 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, 1272 qdev_get_gpio_in_named(dev_apb_ppc1, 1273 "irq_enable", 0)); 1274 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, 1275 qdev_get_gpio_in_named(dev_apb_ppc1, 1276 "irq_clear", 0)); 1277 qdev_connect_gpio_out(dev_splitter, 1, 1278 qdev_get_gpio_in_named(dev_apb_ppc1, 1279 "cfg_sec_resp", 0)); 1280 1281 /* 1282 * Now both PPCs are realized we can map the upstream ends of 1283 * ports which correspond to entries in the devinfo array. 1284 * The ports which are connected to non-devinfo devices have 1285 * already been mapped. 1286 */ 1287 for (devinfo = info->devinfo; devinfo->name; devinfo++) { 1288 SysBusDevice *ppc_sbd; 1289 1290 if (devinfo->ppc == NO_PPC) { 1291 continue; 1292 } 1293 ppc_sbd = SYS_BUS_DEVICE(&s->apb_ppc[devinfo->ppc]); 1294 mr = sysbus_mmio_get_region(ppc_sbd, devinfo->ppc_port); 1295 memory_region_add_subregion(&s->container, devinfo->addr, mr); 1296 } 1297 1298 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 1299 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); 1300 1301 if (!object_property_set_int(splitter, "num-lines", 2, errp)) { 1302 return; 1303 } 1304 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1305 return; 1306 } 1307 } 1308 1309 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { 1310 char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); 1311 1312 armsse_forward_ppc(s, ppcname, i); 1313 g_free(ppcname); 1314 } 1315 1316 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { 1317 char *ppcname = g_strdup_printf("apb_ppcexp%d", i); 1318 1319 armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); 1320 g_free(ppcname); 1321 } 1322 1323 for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { 1324 /* Wire up IRQ splitter for internal PPCs */ 1325 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); 1326 char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", 1327 i - NUM_EXTERNAL_PPCS); 1328 TZPPC *ppc = &s->apb_ppc[i - NUM_EXTERNAL_PPCS]; 1329 1330 qdev_connect_gpio_out(devs, 0, 1331 qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); 1332 qdev_connect_gpio_out(devs, 1, 1333 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); 1334 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, 1335 qdev_get_gpio_in(devs, 0)); 1336 g_free(gpioname); 1337 } 1338 1339 /* Wire up the splitters for the MPC IRQs */ 1340 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 1341 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 1342 DeviceState *dev_splitter = DEVICE(splitter); 1343 1344 if (!object_property_set_int(OBJECT(splitter), "num-lines", 2, 1345 errp)) { 1346 return; 1347 } 1348 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1349 return; 1350 } 1351 1352 if (i < IOTS_NUM_EXP_MPC) { 1353 /* Splitter input is from GPIO input line */ 1354 s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0); 1355 qdev_connect_gpio_out(dev_splitter, 0, 1356 qdev_get_gpio_in_named(dev_secctl, 1357 "mpcexp_status", i)); 1358 } else { 1359 /* Splitter input is from our own MPC */ 1360 qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]), 1361 "irq", 0, 1362 qdev_get_gpio_in(dev_splitter, 0)); 1363 qdev_connect_gpio_out(dev_splitter, 0, 1364 qdev_get_gpio_in_named(dev_secctl, 1365 "mpc_status", 1366 i - IOTS_NUM_EXP_MPC)); 1367 } 1368 1369 qdev_connect_gpio_out(dev_splitter, 1, 1370 qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i)); 1371 } 1372 /* Create GPIO inputs which will pass the line state for our 1373 * mpcexp_irq inputs to the correct splitter devices. 1374 */ 1375 qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status", 1376 IOTS_NUM_EXP_MPC); 1377 1378 armsse_forward_sec_resp_cfg(s); 1379 1380 /* Forward the MSC related signals */ 1381 qdev_pass_gpios(dev_secctl, dev, "mscexp_status"); 1382 qdev_pass_gpios(dev_secctl, dev, "mscexp_clear"); 1383 qdev_pass_gpios(dev_secctl, dev, "mscexp_ns"); 1384 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, 1385 armsse_get_common_irq_in(s, 11)); 1386 1387 /* 1388 * Expose our container region to the board model; this corresponds 1389 * to the AHB Slave Expansion ports which allow bus master devices 1390 * (eg DMA controllers) in the board model to make transactions into 1391 * devices in the ARMSSE. 1392 */ 1393 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); 1394 1395 /* Set initial system_clock_scale from MAINCLK */ 1396 armsse_mainclk_update(s, ClockUpdate); 1397 } 1398 1399 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, 1400 int *iregion, bool *exempt, bool *ns, bool *nsc) 1401 { 1402 /* 1403 * For ARMSSE systems the IDAU responses are simple logical functions 1404 * of the address bits. The NSC attribute is guest-adjustable via the 1405 * NSCCFG register in the security controller. 1406 */ 1407 ARMSSE *s = ARM_SSE(ii); 1408 int region = extract32(address, 28, 4); 1409 1410 *ns = !(region & 1); 1411 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); 1412 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1413 *exempt = (address & 0xeff00000) == 0xe0000000; 1414 *iregion = region; 1415 } 1416 1417 static const VMStateDescription armsse_vmstate = { 1418 .name = "iotkit", 1419 .version_id = 2, 1420 .minimum_version_id = 2, 1421 .fields = (VMStateField[]) { 1422 VMSTATE_CLOCK(mainclk, ARMSSE), 1423 VMSTATE_CLOCK(s32kclk, ARMSSE), 1424 VMSTATE_UINT32(nsccfg, ARMSSE), 1425 VMSTATE_END_OF_LIST() 1426 } 1427 }; 1428 1429 static void armsse_reset(DeviceState *dev) 1430 { 1431 ARMSSE *s = ARM_SSE(dev); 1432 1433 s->nsccfg = 0; 1434 } 1435 1436 static void armsse_class_init(ObjectClass *klass, void *data) 1437 { 1438 DeviceClass *dc = DEVICE_CLASS(klass); 1439 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); 1440 ARMSSEClass *asc = ARM_SSE_CLASS(klass); 1441 const ARMSSEInfo *info = data; 1442 1443 dc->realize = armsse_realize; 1444 dc->vmsd = &armsse_vmstate; 1445 device_class_set_props(dc, info->props); 1446 dc->reset = armsse_reset; 1447 iic->check = armsse_idau_check; 1448 asc->info = info; 1449 } 1450 1451 static const TypeInfo armsse_info = { 1452 .name = TYPE_ARM_SSE, 1453 .parent = TYPE_SYS_BUS_DEVICE, 1454 .instance_size = sizeof(ARMSSE), 1455 .class_size = sizeof(ARMSSEClass), 1456 .instance_init = armsse_init, 1457 .abstract = true, 1458 .interfaces = (InterfaceInfo[]) { 1459 { TYPE_IDAU_INTERFACE }, 1460 { } 1461 } 1462 }; 1463 1464 static void armsse_register_types(void) 1465 { 1466 int i; 1467 1468 type_register_static(&armsse_info); 1469 1470 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) { 1471 TypeInfo ti = { 1472 .name = armsse_variants[i].name, 1473 .parent = TYPE_ARM_SSE, 1474 .class_init = armsse_class_init, 1475 .class_data = (void *)&armsse_variants[i], 1476 }; 1477 type_register(&ti); 1478 } 1479 } 1480 1481 type_init(armsse_register_types); 1482