1 /* 2 * Arm SSE (Subsystems for Embedded): IoTKit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qapi/error.h" 15 #include "trace.h" 16 #include "hw/sysbus.h" 17 #include "hw/registerfields.h" 18 #include "hw/arm/armsse.h" 19 #include "hw/arm/arm.h" 20 21 /* Format of the System Information block SYS_CONFIG register */ 22 typedef enum SysConfigFormat { 23 IoTKitFormat, 24 SSE200Format, 25 } SysConfigFormat; 26 27 struct ARMSSEInfo { 28 const char *name; 29 int sram_banks; 30 int num_cpus; 31 uint32_t sys_version; 32 SysConfigFormat sys_config_format; 33 bool has_mhus; 34 bool has_ppus; 35 bool has_cachectrl; 36 bool has_cpusecctrl; 37 bool has_cpuid; 38 }; 39 40 static const ARMSSEInfo armsse_variants[] = { 41 { 42 .name = TYPE_IOTKIT, 43 .sram_banks = 1, 44 .num_cpus = 1, 45 .sys_version = 0x41743, 46 .sys_config_format = IoTKitFormat, 47 .has_mhus = false, 48 .has_ppus = false, 49 .has_cachectrl = false, 50 .has_cpusecctrl = false, 51 .has_cpuid = false, 52 }, 53 { 54 .name = TYPE_SSE200, 55 .sram_banks = 4, 56 .num_cpus = 2, 57 .sys_version = 0x22041743, 58 .sys_config_format = SSE200Format, 59 .has_mhus = true, 60 .has_ppus = true, 61 .has_cachectrl = true, 62 .has_cpusecctrl = true, 63 .has_cpuid = true, 64 }, 65 }; 66 67 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) 68 { 69 /* Return the SYS_CONFIG value for this SSE */ 70 uint32_t sys_config; 71 72 switch (info->sys_config_format) { 73 case IoTKitFormat: 74 sys_config = 0; 75 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 76 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); 77 break; 78 case SSE200Format: 79 sys_config = 0; 80 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 81 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 82 sys_config = deposit32(sys_config, 24, 4, 2); 83 if (info->num_cpus > 1) { 84 sys_config = deposit32(sys_config, 10, 1, 1); 85 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1); 86 sys_config = deposit32(sys_config, 28, 4, 2); 87 } 88 break; 89 default: 90 g_assert_not_reached(); 91 } 92 return sys_config; 93 } 94 95 /* Clock frequency in HZ of the 32KHz "slow clock" */ 96 #define S32KCLK (32 * 1000) 97 98 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ 99 static bool irq_is_common[32] = { 100 [0 ... 5] = true, 101 /* 6, 7: per-CPU MHU interrupts */ 102 [8 ... 12] = true, 103 /* 13: per-CPU icache interrupt */ 104 /* 14: reserved */ 105 [15 ... 20] = true, 106 /* 21: reserved */ 107 [22 ... 26] = true, 108 /* 27: reserved */ 109 /* 28, 29: per-CPU CTI interrupts */ 110 /* 30, 31: reserved */ 111 }; 112 113 /* 114 * Create an alias region in @container of @size bytes starting at @base 115 * which mirrors the memory starting at @orig. 116 */ 117 static void make_alias(ARMSSE *s, MemoryRegion *mr, MemoryRegion *container, 118 const char *name, hwaddr base, hwaddr size, hwaddr orig) 119 { 120 memory_region_init_alias(mr, NULL, name, container, orig, size); 121 /* The alias is even lower priority than unimplemented_device regions */ 122 memory_region_add_subregion_overlap(container, base, mr, -1500); 123 } 124 125 static void irq_status_forwarder(void *opaque, int n, int level) 126 { 127 qemu_irq destirq = opaque; 128 129 qemu_set_irq(destirq, level); 130 } 131 132 static void nsccfg_handler(void *opaque, int n, int level) 133 { 134 ARMSSE *s = ARMSSE(opaque); 135 136 s->nsccfg = level; 137 } 138 139 static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) 140 { 141 /* Each of the 4 AHB and 4 APB PPCs that might be present in a 142 * system using the ARMSSE has a collection of control lines which 143 * are provided by the security controller and which we want to 144 * expose as control lines on the ARMSSE device itself, so the 145 * code using the ARMSSE can wire them up to the PPCs. 146 */ 147 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; 148 DeviceState *armssedev = DEVICE(s); 149 DeviceState *dev_secctl = DEVICE(&s->secctl); 150 DeviceState *dev_splitter = DEVICE(splitter); 151 char *name; 152 153 name = g_strdup_printf("%s_nonsec", ppcname); 154 qdev_pass_gpios(dev_secctl, armssedev, name); 155 g_free(name); 156 name = g_strdup_printf("%s_ap", ppcname); 157 qdev_pass_gpios(dev_secctl, armssedev, name); 158 g_free(name); 159 name = g_strdup_printf("%s_irq_enable", ppcname); 160 qdev_pass_gpios(dev_secctl, armssedev, name); 161 g_free(name); 162 name = g_strdup_printf("%s_irq_clear", ppcname); 163 qdev_pass_gpios(dev_secctl, armssedev, name); 164 g_free(name); 165 166 /* irq_status is a little more tricky, because we need to 167 * split it so we can send it both to the security controller 168 * and to our OR gate for the NVIC interrupt line. 169 * Connect up the splitter's outputs, and create a GPIO input 170 * which will pass the line state to the input splitter. 171 */ 172 name = g_strdup_printf("%s_irq_status", ppcname); 173 qdev_connect_gpio_out(dev_splitter, 0, 174 qdev_get_gpio_in_named(dev_secctl, 175 name, 0)); 176 qdev_connect_gpio_out(dev_splitter, 1, 177 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); 178 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); 179 qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder, 180 s->irq_status_in[ppcnum], name, 1); 181 g_free(name); 182 } 183 184 static void armsse_forward_sec_resp_cfg(ARMSSE *s) 185 { 186 /* Forward the 3rd output from the splitter device as a 187 * named GPIO output of the armsse object. 188 */ 189 DeviceState *dev = DEVICE(s); 190 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); 191 192 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); 193 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, 194 s->sec_resp_cfg, 1); 195 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); 196 } 197 198 static void armsse_init(Object *obj) 199 { 200 ARMSSE *s = ARMSSE(obj); 201 ARMSSEClass *asc = ARMSSE_GET_CLASS(obj); 202 const ARMSSEInfo *info = asc->info; 203 int i; 204 205 assert(info->sram_banks <= MAX_SRAM_BANKS); 206 assert(info->num_cpus <= SSE_MAX_CPUS); 207 208 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); 209 210 for (i = 0; i < info->num_cpus; i++) { 211 /* 212 * We put each CPU in its own cluster as they are logically 213 * distinct and may be configured differently. 214 */ 215 char *name; 216 217 name = g_strdup_printf("cluster%d", i); 218 object_initialize_child(obj, name, &s->cluster[i], 219 sizeof(s->cluster[i]), TYPE_CPU_CLUSTER, 220 &error_abort, NULL); 221 qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); 222 g_free(name); 223 224 name = g_strdup_printf("armv7m%d", i); 225 sysbus_init_child_obj(OBJECT(&s->cluster[i]), name, 226 &s->armv7m[i], sizeof(s->armv7m), TYPE_ARMV7M); 227 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", 228 ARM_CPU_TYPE_NAME("cortex-m33")); 229 g_free(name); 230 name = g_strdup_printf("arm-sse-cpu-container%d", i); 231 memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); 232 g_free(name); 233 if (i > 0) { 234 name = g_strdup_printf("arm-sse-container-alias%d", i); 235 memory_region_init_alias(&s->container_alias[i - 1], obj, 236 name, &s->container, 0, UINT64_MAX); 237 g_free(name); 238 } 239 } 240 241 sysbus_init_child_obj(obj, "secctl", &s->secctl, sizeof(s->secctl), 242 TYPE_IOTKIT_SECCTL); 243 sysbus_init_child_obj(obj, "apb-ppc0", &s->apb_ppc0, sizeof(s->apb_ppc0), 244 TYPE_TZ_PPC); 245 sysbus_init_child_obj(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1), 246 TYPE_TZ_PPC); 247 for (i = 0; i < info->sram_banks; i++) { 248 char *name = g_strdup_printf("mpc%d", i); 249 sysbus_init_child_obj(obj, name, &s->mpc[i], 250 sizeof(s->mpc[i]), TYPE_TZ_MPC); 251 g_free(name); 252 } 253 object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate, 254 sizeof(s->mpc_irq_orgate), TYPE_OR_IRQ, 255 &error_abort, NULL); 256 257 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 258 char *name = g_strdup_printf("mpc-irq-splitter-%d", i); 259 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 260 261 object_initialize_child(obj, name, splitter, sizeof(*splitter), 262 TYPE_SPLIT_IRQ, &error_abort, NULL); 263 g_free(name); 264 } 265 sysbus_init_child_obj(obj, "timer0", &s->timer0, sizeof(s->timer0), 266 TYPE_CMSDK_APB_TIMER); 267 sysbus_init_child_obj(obj, "timer1", &s->timer1, sizeof(s->timer1), 268 TYPE_CMSDK_APB_TIMER); 269 sysbus_init_child_obj(obj, "s32ktimer", &s->s32ktimer, sizeof(s->s32ktimer), 270 TYPE_CMSDK_APB_TIMER); 271 sysbus_init_child_obj(obj, "dualtimer", &s->dualtimer, sizeof(s->dualtimer), 272 TYPE_CMSDK_APB_DUALTIMER); 273 sysbus_init_child_obj(obj, "s32kwatchdog", &s->s32kwatchdog, 274 sizeof(s->s32kwatchdog), TYPE_CMSDK_APB_WATCHDOG); 275 sysbus_init_child_obj(obj, "nswatchdog", &s->nswatchdog, 276 sizeof(s->nswatchdog), TYPE_CMSDK_APB_WATCHDOG); 277 sysbus_init_child_obj(obj, "swatchdog", &s->swatchdog, 278 sizeof(s->swatchdog), TYPE_CMSDK_APB_WATCHDOG); 279 sysbus_init_child_obj(obj, "armsse-sysctl", &s->sysctl, 280 sizeof(s->sysctl), TYPE_IOTKIT_SYSCTL); 281 sysbus_init_child_obj(obj, "armsse-sysinfo", &s->sysinfo, 282 sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO); 283 if (info->has_mhus) { 284 sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]), 285 TYPE_ARMSSE_MHU); 286 sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]), 287 TYPE_ARMSSE_MHU); 288 } 289 if (info->has_ppus) { 290 for (i = 0; i < info->num_cpus; i++) { 291 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 292 int ppuidx = CPU0CORE_PPU + i; 293 294 sysbus_init_child_obj(obj, name, &s->ppu[ppuidx], 295 sizeof(s->ppu[ppuidx]), 296 TYPE_UNIMPLEMENTED_DEVICE); 297 g_free(name); 298 } 299 sysbus_init_child_obj(obj, "DBG_PPU", &s->ppu[DBG_PPU], 300 sizeof(s->ppu[DBG_PPU]), 301 TYPE_UNIMPLEMENTED_DEVICE); 302 for (i = 0; i < info->sram_banks; i++) { 303 char *name = g_strdup_printf("RAM%d_PPU", i); 304 int ppuidx = RAM0_PPU + i; 305 306 sysbus_init_child_obj(obj, name, &s->ppu[ppuidx], 307 sizeof(s->ppu[ppuidx]), 308 TYPE_UNIMPLEMENTED_DEVICE); 309 g_free(name); 310 } 311 } 312 if (info->has_cachectrl) { 313 for (i = 0; i < info->num_cpus; i++) { 314 char *name = g_strdup_printf("cachectrl%d", i); 315 316 sysbus_init_child_obj(obj, name, &s->cachectrl[i], 317 sizeof(s->cachectrl[i]), 318 TYPE_UNIMPLEMENTED_DEVICE); 319 g_free(name); 320 } 321 } 322 if (info->has_cpusecctrl) { 323 for (i = 0; i < info->num_cpus; i++) { 324 char *name = g_strdup_printf("cpusecctrl%d", i); 325 326 sysbus_init_child_obj(obj, name, &s->cpusecctrl[i], 327 sizeof(s->cpusecctrl[i]), 328 TYPE_UNIMPLEMENTED_DEVICE); 329 g_free(name); 330 } 331 } 332 if (info->has_cpuid) { 333 for (i = 0; i < info->num_cpus; i++) { 334 char *name = g_strdup_printf("cpuid%d", i); 335 336 sysbus_init_child_obj(obj, name, &s->cpuid[i], 337 sizeof(s->cpuid[i]), 338 TYPE_ARMSSE_CPUID); 339 g_free(name); 340 } 341 } 342 object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, 343 sizeof(s->nmi_orgate), TYPE_OR_IRQ, 344 &error_abort, NULL); 345 object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, 346 sizeof(s->ppc_irq_orgate), TYPE_OR_IRQ, 347 &error_abort, NULL); 348 object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter, 349 sizeof(s->sec_resp_splitter), TYPE_SPLIT_IRQ, 350 &error_abort, NULL); 351 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 352 char *name = g_strdup_printf("ppc-irq-splitter-%d", i); 353 SplitIRQ *splitter = &s->ppc_irq_splitter[i]; 354 355 object_initialize_child(obj, name, splitter, sizeof(*splitter), 356 TYPE_SPLIT_IRQ, &error_abort, NULL); 357 g_free(name); 358 } 359 if (info->num_cpus > 1) { 360 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 361 if (irq_is_common[i]) { 362 char *name = g_strdup_printf("cpu-irq-splitter%d", i); 363 SplitIRQ *splitter = &s->cpu_irq_splitter[i]; 364 365 object_initialize_child(obj, name, splitter, sizeof(*splitter), 366 TYPE_SPLIT_IRQ, &error_abort, NULL); 367 g_free(name); 368 } 369 } 370 } 371 } 372 373 static void armsse_exp_irq(void *opaque, int n, int level) 374 { 375 qemu_irq *irqarray = opaque; 376 377 qemu_set_irq(irqarray[n], level); 378 } 379 380 static void armsse_mpcexp_status(void *opaque, int n, int level) 381 { 382 ARMSSE *s = ARMSSE(opaque); 383 qemu_set_irq(s->mpcexp_status_in[n], level); 384 } 385 386 static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno) 387 { 388 /* 389 * Return a qemu_irq which can be used to signal IRQ n to 390 * all CPUs in the SSE. 391 */ 392 ARMSSEClass *asc = ARMSSE_GET_CLASS(s); 393 const ARMSSEInfo *info = asc->info; 394 395 assert(irq_is_common[irqno]); 396 397 if (info->num_cpus == 1) { 398 /* Only one CPU -- just connect directly to it */ 399 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); 400 } else { 401 /* Connect to the splitter which feeds all CPUs */ 402 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); 403 } 404 } 405 406 static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) 407 { 408 /* Map a PPU unimplemented device stub */ 409 DeviceState *dev = DEVICE(&s->ppu[ppuidx]); 410 411 qdev_prop_set_string(dev, "name", name); 412 qdev_prop_set_uint64(dev, "size", 0x1000); 413 qdev_init_nofail(dev); 414 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); 415 } 416 417 static void armsse_realize(DeviceState *dev, Error **errp) 418 { 419 ARMSSE *s = ARMSSE(dev); 420 ARMSSEClass *asc = ARMSSE_GET_CLASS(dev); 421 const ARMSSEInfo *info = asc->info; 422 int i; 423 MemoryRegion *mr; 424 Error *err = NULL; 425 SysBusDevice *sbd_apb_ppc0; 426 SysBusDevice *sbd_secctl; 427 DeviceState *dev_apb_ppc0; 428 DeviceState *dev_apb_ppc1; 429 DeviceState *dev_secctl; 430 DeviceState *dev_splitter; 431 uint32_t addr_width_max; 432 433 if (!s->board_memory) { 434 error_setg(errp, "memory property was not set"); 435 return; 436 } 437 438 if (!s->mainclk_frq) { 439 error_setg(errp, "MAINCLK property was not set"); 440 return; 441 } 442 443 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ 444 assert(is_power_of_2(info->sram_banks)); 445 addr_width_max = 24 - ctz32(info->sram_banks); 446 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { 447 error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d", 448 addr_width_max); 449 return; 450 } 451 452 /* Handling of which devices should be available only to secure 453 * code is usually done differently for M profile than for A profile. 454 * Instead of putting some devices only into the secure address space, 455 * devices exist in both address spaces but with hard-wired security 456 * permissions that will cause the CPU to fault for non-secure accesses. 457 * 458 * The ARMSSE has an IDAU (Implementation Defined Access Unit), 459 * which specifies hard-wired security permissions for different 460 * areas of the physical address space. For the ARMSSE IDAU, the 461 * top 4 bits of the physical address are the IDAU region ID, and 462 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS 463 * region, otherwise it is an S region. 464 * 465 * The various devices and RAMs are generally all mapped twice, 466 * once into a region that the IDAU defines as secure and once 467 * into a non-secure region. They sit behind either a Memory 468 * Protection Controller (for RAM) or a Peripheral Protection 469 * Controller (for devices), which allow a more fine grained 470 * configuration of whether non-secure accesses are permitted. 471 * 472 * (The other place that guest software can configure security 473 * permissions is in the architected SAU (Security Attribution 474 * Unit), which is entirely inside the CPU. The IDAU can upgrade 475 * the security attributes for a region to more restrictive than 476 * the SAU specifies, but cannot downgrade them.) 477 * 478 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff 479 * 0x20000000..0x2007ffff 32KB FPGA block RAM 480 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff 481 * 0x40000000..0x4000ffff base peripheral region 1 482 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) 483 * 0x40020000..0x4002ffff system control element peripherals 484 * 0x40080000..0x400fffff base peripheral region 2 485 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff 486 */ 487 488 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); 489 490 for (i = 0; i < info->num_cpus; i++) { 491 DeviceState *cpudev = DEVICE(&s->armv7m[i]); 492 Object *cpuobj = OBJECT(&s->armv7m[i]); 493 int j; 494 char *gpioname; 495 496 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32); 497 /* 498 * In real hardware the initial Secure VTOR is set from the INITSVTOR0 499 * register in the IoT Kit System Control Register block, and the 500 * initial value of that is in turn specifiable by the FPGA that 501 * instantiates the IoT Kit. In QEMU we don't implement this wrinkle, 502 * and simply set the CPU's init-svtor to the IoT Kit default value. 503 * In SSE-200 the situation is similar, except that the default value 504 * is a reset-time signal input. Typically a board using the SSE-200 505 * will have a system control processor whose boot firmware initializes 506 * the INITSVTOR* registers before powering up the CPUs in any case, 507 * so the hardware's default value doesn't matter. QEMU doesn't emulate 508 * the control processor, so instead we behave in the way that the 509 * firmware does. The initial value is configurable by the board code 510 * to match whatever its firmware does. 511 */ 512 qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); 513 /* 514 * Start all CPUs except CPU0 powered down. In real hardware it is 515 * a configurable property of the SSE-200 which CPUs start powered up 516 * (via the CPUWAIT0_RST and CPUWAIT1_RST parameters), but since all 517 * the boards we care about start CPU0 and leave CPU1 powered off, 518 * we hard-code that for now. We can add QOM properties for this 519 * later if necessary. 520 */ 521 if (i > 0) { 522 object_property_set_bool(cpuobj, true, "start-powered-off", &err); 523 if (err) { 524 error_propagate(errp, err); 525 return; 526 } 527 } 528 529 if (i > 0) { 530 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 531 &s->container_alias[i - 1], -1); 532 } else { 533 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 534 &s->container, -1); 535 } 536 object_property_set_link(cpuobj, OBJECT(&s->cpu_container[i]), 537 "memory", &err); 538 if (err) { 539 error_propagate(errp, err); 540 return; 541 } 542 object_property_set_link(cpuobj, OBJECT(s), "idau", &err); 543 if (err) { 544 error_propagate(errp, err); 545 return; 546 } 547 object_property_set_bool(cpuobj, true, "realized", &err); 548 if (err) { 549 error_propagate(errp, err); 550 return; 551 } 552 /* 553 * The cluster must be realized after the armv7m container, as 554 * the container's CPU object is only created on realize, and the 555 * CPU must exist and have been parented into the cluster before 556 * the cluster is realized. 557 */ 558 object_property_set_bool(OBJECT(&s->cluster[i]), 559 true, "realized", &err); 560 if (err) { 561 error_propagate(errp, err); 562 return; 563 } 564 565 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ 566 s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); 567 for (j = 0; j < s->exp_numirq; j++) { 568 s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32); 569 } 570 if (i == 0) { 571 gpioname = g_strdup("EXP_IRQ"); 572 } else { 573 gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i); 574 } 575 qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq, 576 s->exp_irqs[i], 577 gpioname, s->exp_numirq); 578 g_free(gpioname); 579 } 580 581 /* Wire up the splitters that connect common IRQs to all CPUs */ 582 if (info->num_cpus > 1) { 583 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 584 if (irq_is_common[i]) { 585 Object *splitter = OBJECT(&s->cpu_irq_splitter[i]); 586 DeviceState *devs = DEVICE(splitter); 587 int cpunum; 588 589 object_property_set_int(splitter, info->num_cpus, 590 "num-lines", &err); 591 if (err) { 592 error_propagate(errp, err); 593 return; 594 } 595 object_property_set_bool(splitter, true, "realized", &err); 596 if (err) { 597 error_propagate(errp, err); 598 return; 599 } 600 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 601 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 602 603 qdev_connect_gpio_out(devs, cpunum, 604 qdev_get_gpio_in(cpudev, i)); 605 } 606 } 607 } 608 } 609 610 /* Set up the big aliases first */ 611 make_alias(s, &s->alias1, &s->container, "alias 1", 612 0x10000000, 0x10000000, 0x00000000); 613 make_alias(s, &s->alias2, &s->container, 614 "alias 2", 0x30000000, 0x10000000, 0x20000000); 615 /* The 0x50000000..0x5fffffff region is not a pure alias: it has 616 * a few extra devices that only appear there (generally the 617 * control interfaces for the protection controllers). 618 * We implement this by mapping those devices over the top of this 619 * alias MR at a higher priority. Some of the devices in this range 620 * are per-CPU, so we must put this alias in the per-cpu containers. 621 */ 622 for (i = 0; i < info->num_cpus; i++) { 623 make_alias(s, &s->alias3[i], &s->cpu_container[i], 624 "alias 3", 0x50000000, 0x10000000, 0x40000000); 625 } 626 627 /* Security controller */ 628 object_property_set_bool(OBJECT(&s->secctl), true, "realized", &err); 629 if (err) { 630 error_propagate(errp, err); 631 return; 632 } 633 sbd_secctl = SYS_BUS_DEVICE(&s->secctl); 634 dev_secctl = DEVICE(&s->secctl); 635 sysbus_mmio_map(sbd_secctl, 0, 0x50080000); 636 sysbus_mmio_map(sbd_secctl, 1, 0x40080000); 637 638 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); 639 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); 640 641 /* The sec_resp_cfg output from the security controller must be split into 642 * multiple lines, one for each of the PPCs within the ARMSSE and one 643 * that will be an output from the ARMSSE to the system. 644 */ 645 object_property_set_int(OBJECT(&s->sec_resp_splitter), 3, 646 "num-lines", &err); 647 if (err) { 648 error_propagate(errp, err); 649 return; 650 } 651 object_property_set_bool(OBJECT(&s->sec_resp_splitter), true, 652 "realized", &err); 653 if (err) { 654 error_propagate(errp, err); 655 return; 656 } 657 dev_splitter = DEVICE(&s->sec_resp_splitter); 658 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, 659 qdev_get_gpio_in(dev_splitter, 0)); 660 661 /* Each SRAM bank lives behind its own Memory Protection Controller */ 662 for (i = 0; i < info->sram_banks; i++) { 663 char *ramname = g_strdup_printf("armsse.sram%d", i); 664 SysBusDevice *sbd_mpc; 665 uint32_t sram_bank_size = 1 << s->sram_addr_width; 666 667 memory_region_init_ram(&s->sram[i], NULL, ramname, 668 sram_bank_size, &err); 669 g_free(ramname); 670 if (err) { 671 error_propagate(errp, err); 672 return; 673 } 674 object_property_set_link(OBJECT(&s->mpc[i]), OBJECT(&s->sram[i]), 675 "downstream", &err); 676 if (err) { 677 error_propagate(errp, err); 678 return; 679 } 680 object_property_set_bool(OBJECT(&s->mpc[i]), true, "realized", &err); 681 if (err) { 682 error_propagate(errp, err); 683 return; 684 } 685 /* Map the upstream end of the MPC into the right place... */ 686 sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); 687 memory_region_add_subregion(&s->container, 688 0x20000000 + i * sram_bank_size, 689 sysbus_mmio_get_region(sbd_mpc, 1)); 690 /* ...and its register interface */ 691 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, 692 sysbus_mmio_get_region(sbd_mpc, 0)); 693 } 694 695 /* We must OR together lines from the MPC splitters to go to the NVIC */ 696 object_property_set_int(OBJECT(&s->mpc_irq_orgate), 697 IOTS_NUM_EXP_MPC + info->sram_banks, 698 "num-lines", &err); 699 if (err) { 700 error_propagate(errp, err); 701 return; 702 } 703 object_property_set_bool(OBJECT(&s->mpc_irq_orgate), true, 704 "realized", &err); 705 if (err) { 706 error_propagate(errp, err); 707 return; 708 } 709 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, 710 armsse_get_common_irq_in(s, 9)); 711 712 /* Devices behind APB PPC0: 713 * 0x40000000: timer0 714 * 0x40001000: timer1 715 * 0x40002000: dual timer 716 * 0x40003000: MHU0 (SSE-200 only) 717 * 0x40004000: MHU1 (SSE-200 only) 718 * We must configure and realize each downstream device and connect 719 * it to the appropriate PPC port; then we can realize the PPC and 720 * map its upstream ends to the right place in the container. 721 */ 722 qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); 723 object_property_set_bool(OBJECT(&s->timer0), true, "realized", &err); 724 if (err) { 725 error_propagate(errp, err); 726 return; 727 } 728 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, 729 armsse_get_common_irq_in(s, 3)); 730 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); 731 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[0]", &err); 732 if (err) { 733 error_propagate(errp, err); 734 return; 735 } 736 737 qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); 738 object_property_set_bool(OBJECT(&s->timer1), true, "realized", &err); 739 if (err) { 740 error_propagate(errp, err); 741 return; 742 } 743 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, 744 armsse_get_common_irq_in(s, 4)); 745 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); 746 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[1]", &err); 747 if (err) { 748 error_propagate(errp, err); 749 return; 750 } 751 752 753 qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); 754 object_property_set_bool(OBJECT(&s->dualtimer), true, "realized", &err); 755 if (err) { 756 error_propagate(errp, err); 757 return; 758 } 759 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dualtimer), 0, 760 armsse_get_common_irq_in(s, 5)); 761 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); 762 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[2]", &err); 763 if (err) { 764 error_propagate(errp, err); 765 return; 766 } 767 768 if (info->has_mhus) { 769 /* 770 * An SSE-200 with only one CPU should have only one MHU created, 771 * with the region where the second MHU usually is being RAZ/WI. 772 * We don't implement that SSE-200 config; if we want to support 773 * it then this code needs to be enhanced to handle creating the 774 * RAZ/WI region instead of the second MHU. 775 */ 776 assert(info->num_cpus == ARRAY_SIZE(s->mhu)); 777 778 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { 779 char *port; 780 int cpunum; 781 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]); 782 783 object_property_set_bool(OBJECT(&s->mhu[i]), true, 784 "realized", &err); 785 if (err) { 786 error_propagate(errp, err); 787 return; 788 } 789 port = g_strdup_printf("port[%d]", i + 3); 790 mr = sysbus_mmio_get_region(mhu_sbd, 0); 791 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), 792 port, &err); 793 g_free(port); 794 if (err) { 795 error_propagate(errp, err); 796 return; 797 } 798 799 /* 800 * Each MHU has an irq line for each CPU: 801 * MHU 0 irq line 0 -> CPU 0 IRQ 6 802 * MHU 0 irq line 1 -> CPU 1 IRQ 6 803 * MHU 1 irq line 0 -> CPU 0 IRQ 7 804 * MHU 1 irq line 1 -> CPU 1 IRQ 7 805 */ 806 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 807 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 808 809 sysbus_connect_irq(mhu_sbd, cpunum, 810 qdev_get_gpio_in(cpudev, 6 + i)); 811 } 812 } 813 } 814 815 object_property_set_bool(OBJECT(&s->apb_ppc0), true, "realized", &err); 816 if (err) { 817 error_propagate(errp, err); 818 return; 819 } 820 821 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); 822 dev_apb_ppc0 = DEVICE(&s->apb_ppc0); 823 824 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); 825 memory_region_add_subregion(&s->container, 0x40000000, mr); 826 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); 827 memory_region_add_subregion(&s->container, 0x40001000, mr); 828 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); 829 memory_region_add_subregion(&s->container, 0x40002000, mr); 830 if (info->has_mhus) { 831 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3); 832 memory_region_add_subregion(&s->container, 0x40003000, mr); 833 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4); 834 memory_region_add_subregion(&s->container, 0x40004000, mr); 835 } 836 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { 837 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, 838 qdev_get_gpio_in_named(dev_apb_ppc0, 839 "cfg_nonsec", i)); 840 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, 841 qdev_get_gpio_in_named(dev_apb_ppc0, 842 "cfg_ap", i)); 843 } 844 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, 845 qdev_get_gpio_in_named(dev_apb_ppc0, 846 "irq_enable", 0)); 847 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, 848 qdev_get_gpio_in_named(dev_apb_ppc0, 849 "irq_clear", 0)); 850 qdev_connect_gpio_out(dev_splitter, 0, 851 qdev_get_gpio_in_named(dev_apb_ppc0, 852 "cfg_sec_resp", 0)); 853 854 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external 855 * ones) are sent individually to the security controller, and also 856 * ORed together to give a single combined PPC interrupt to the NVIC. 857 */ 858 object_property_set_int(OBJECT(&s->ppc_irq_orgate), 859 NUM_PPCS, "num-lines", &err); 860 if (err) { 861 error_propagate(errp, err); 862 return; 863 } 864 object_property_set_bool(OBJECT(&s->ppc_irq_orgate), true, 865 "realized", &err); 866 if (err) { 867 error_propagate(errp, err); 868 return; 869 } 870 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, 871 armsse_get_common_irq_in(s, 10)); 872 873 /* 874 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): 875 * private per-CPU region (all these devices are SSE-200 only): 876 * 0x50010000: L1 icache control registers 877 * 0x50011000: CPUSECCTRL (CPU local security control registers) 878 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block 879 */ 880 if (info->has_cachectrl) { 881 for (i = 0; i < info->num_cpus; i++) { 882 char *name = g_strdup_printf("cachectrl%d", i); 883 MemoryRegion *mr; 884 885 qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); 886 g_free(name); 887 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); 888 object_property_set_bool(OBJECT(&s->cachectrl[i]), true, 889 "realized", &err); 890 if (err) { 891 error_propagate(errp, err); 892 return; 893 } 894 895 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); 896 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); 897 } 898 } 899 if (info->has_cpusecctrl) { 900 for (i = 0; i < info->num_cpus; i++) { 901 char *name = g_strdup_printf("CPUSECCTRL%d", i); 902 MemoryRegion *mr; 903 904 qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); 905 g_free(name); 906 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); 907 object_property_set_bool(OBJECT(&s->cpusecctrl[i]), true, 908 "realized", &err); 909 if (err) { 910 error_propagate(errp, err); 911 return; 912 } 913 914 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); 915 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); 916 } 917 } 918 if (info->has_cpuid) { 919 for (i = 0; i < info->num_cpus; i++) { 920 MemoryRegion *mr; 921 922 qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); 923 object_property_set_bool(OBJECT(&s->cpuid[i]), true, 924 "realized", &err); 925 if (err) { 926 error_propagate(errp, err); 927 return; 928 } 929 930 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); 931 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); 932 } 933 } 934 935 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */ 936 /* Devices behind APB PPC1: 937 * 0x4002f000: S32K timer 938 */ 939 qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); 940 object_property_set_bool(OBJECT(&s->s32ktimer), true, "realized", &err); 941 if (err) { 942 error_propagate(errp, err); 943 return; 944 } 945 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, 946 armsse_get_common_irq_in(s, 2)); 947 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); 948 object_property_set_link(OBJECT(&s->apb_ppc1), OBJECT(mr), "port[0]", &err); 949 if (err) { 950 error_propagate(errp, err); 951 return; 952 } 953 954 object_property_set_bool(OBJECT(&s->apb_ppc1), true, "realized", &err); 955 if (err) { 956 error_propagate(errp, err); 957 return; 958 } 959 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); 960 memory_region_add_subregion(&s->container, 0x4002f000, mr); 961 962 dev_apb_ppc1 = DEVICE(&s->apb_ppc1); 963 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, 964 qdev_get_gpio_in_named(dev_apb_ppc1, 965 "cfg_nonsec", 0)); 966 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, 967 qdev_get_gpio_in_named(dev_apb_ppc1, 968 "cfg_ap", 0)); 969 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, 970 qdev_get_gpio_in_named(dev_apb_ppc1, 971 "irq_enable", 0)); 972 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, 973 qdev_get_gpio_in_named(dev_apb_ppc1, 974 "irq_clear", 0)); 975 qdev_connect_gpio_out(dev_splitter, 1, 976 qdev_get_gpio_in_named(dev_apb_ppc1, 977 "cfg_sec_resp", 0)); 978 979 object_property_set_int(OBJECT(&s->sysinfo), info->sys_version, 980 "SYS_VERSION", &err); 981 if (err) { 982 error_propagate(errp, err); 983 return; 984 } 985 object_property_set_int(OBJECT(&s->sysinfo), 986 armsse_sys_config_value(s, info), 987 "SYS_CONFIG", &err); 988 if (err) { 989 error_propagate(errp, err); 990 return; 991 } 992 object_property_set_bool(OBJECT(&s->sysinfo), true, "realized", &err); 993 if (err) { 994 error_propagate(errp, err); 995 return; 996 } 997 /* System information registers */ 998 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); 999 /* System control registers */ 1000 object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err); 1001 if (err) { 1002 error_propagate(errp, err); 1003 return; 1004 } 1005 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); 1006 1007 if (info->has_ppus) { 1008 /* CPUnCORE_PPU for each CPU */ 1009 for (i = 0; i < info->num_cpus; i++) { 1010 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 1011 1012 map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); 1013 /* 1014 * We don't support CPU debug so don't create the 1015 * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. 1016 */ 1017 g_free(name); 1018 } 1019 map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); 1020 1021 for (i = 0; i < info->sram_banks; i++) { 1022 char *name = g_strdup_printf("RAM%d_PPU", i); 1023 1024 map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); 1025 g_free(name); 1026 } 1027 } 1028 1029 /* This OR gate wires together outputs from the secure watchdogs to NMI */ 1030 object_property_set_int(OBJECT(&s->nmi_orgate), 2, "num-lines", &err); 1031 if (err) { 1032 error_propagate(errp, err); 1033 return; 1034 } 1035 object_property_set_bool(OBJECT(&s->nmi_orgate), true, "realized", &err); 1036 if (err) { 1037 error_propagate(errp, err); 1038 return; 1039 } 1040 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, 1041 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); 1042 1043 qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); 1044 object_property_set_bool(OBJECT(&s->s32kwatchdog), true, "realized", &err); 1045 if (err) { 1046 error_propagate(errp, err); 1047 return; 1048 } 1049 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 1050 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 0)); 1051 sysbus_mmio_map(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 0x5002e000); 1052 1053 /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ 1054 1055 qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); 1056 object_property_set_bool(OBJECT(&s->nswatchdog), true, "realized", &err); 1057 if (err) { 1058 error_propagate(errp, err); 1059 return; 1060 } 1061 sysbus_connect_irq(SYS_BUS_DEVICE(&s->nswatchdog), 0, 1062 armsse_get_common_irq_in(s, 1)); 1063 sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); 1064 1065 qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); 1066 object_property_set_bool(OBJECT(&s->swatchdog), true, "realized", &err); 1067 if (err) { 1068 error_propagate(errp, err); 1069 return; 1070 } 1071 sysbus_connect_irq(SYS_BUS_DEVICE(&s->swatchdog), 0, 1072 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 1)); 1073 sysbus_mmio_map(SYS_BUS_DEVICE(&s->swatchdog), 0, 0x50081000); 1074 1075 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 1076 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); 1077 1078 object_property_set_int(splitter, 2, "num-lines", &err); 1079 if (err) { 1080 error_propagate(errp, err); 1081 return; 1082 } 1083 object_property_set_bool(splitter, true, "realized", &err); 1084 if (err) { 1085 error_propagate(errp, err); 1086 return; 1087 } 1088 } 1089 1090 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { 1091 char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); 1092 1093 armsse_forward_ppc(s, ppcname, i); 1094 g_free(ppcname); 1095 } 1096 1097 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { 1098 char *ppcname = g_strdup_printf("apb_ppcexp%d", i); 1099 1100 armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); 1101 g_free(ppcname); 1102 } 1103 1104 for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { 1105 /* Wire up IRQ splitter for internal PPCs */ 1106 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); 1107 char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", 1108 i - NUM_EXTERNAL_PPCS); 1109 TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; 1110 1111 qdev_connect_gpio_out(devs, 0, 1112 qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); 1113 qdev_connect_gpio_out(devs, 1, 1114 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); 1115 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, 1116 qdev_get_gpio_in(devs, 0)); 1117 g_free(gpioname); 1118 } 1119 1120 /* Wire up the splitters for the MPC IRQs */ 1121 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 1122 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 1123 DeviceState *dev_splitter = DEVICE(splitter); 1124 1125 object_property_set_int(OBJECT(splitter), 2, "num-lines", &err); 1126 if (err) { 1127 error_propagate(errp, err); 1128 return; 1129 } 1130 object_property_set_bool(OBJECT(splitter), true, "realized", &err); 1131 if (err) { 1132 error_propagate(errp, err); 1133 return; 1134 } 1135 1136 if (i < IOTS_NUM_EXP_MPC) { 1137 /* Splitter input is from GPIO input line */ 1138 s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0); 1139 qdev_connect_gpio_out(dev_splitter, 0, 1140 qdev_get_gpio_in_named(dev_secctl, 1141 "mpcexp_status", i)); 1142 } else { 1143 /* Splitter input is from our own MPC */ 1144 qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]), 1145 "irq", 0, 1146 qdev_get_gpio_in(dev_splitter, 0)); 1147 qdev_connect_gpio_out(dev_splitter, 0, 1148 qdev_get_gpio_in_named(dev_secctl, 1149 "mpc_status", 0)); 1150 } 1151 1152 qdev_connect_gpio_out(dev_splitter, 1, 1153 qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i)); 1154 } 1155 /* Create GPIO inputs which will pass the line state for our 1156 * mpcexp_irq inputs to the correct splitter devices. 1157 */ 1158 qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status", 1159 IOTS_NUM_EXP_MPC); 1160 1161 armsse_forward_sec_resp_cfg(s); 1162 1163 /* Forward the MSC related signals */ 1164 qdev_pass_gpios(dev_secctl, dev, "mscexp_status"); 1165 qdev_pass_gpios(dev_secctl, dev, "mscexp_clear"); 1166 qdev_pass_gpios(dev_secctl, dev, "mscexp_ns"); 1167 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, 1168 armsse_get_common_irq_in(s, 11)); 1169 1170 /* 1171 * Expose our container region to the board model; this corresponds 1172 * to the AHB Slave Expansion ports which allow bus master devices 1173 * (eg DMA controllers) in the board model to make transactions into 1174 * devices in the ARMSSE. 1175 */ 1176 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); 1177 1178 system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; 1179 } 1180 1181 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, 1182 int *iregion, bool *exempt, bool *ns, bool *nsc) 1183 { 1184 /* 1185 * For ARMSSE systems the IDAU responses are simple logical functions 1186 * of the address bits. The NSC attribute is guest-adjustable via the 1187 * NSCCFG register in the security controller. 1188 */ 1189 ARMSSE *s = ARMSSE(ii); 1190 int region = extract32(address, 28, 4); 1191 1192 *ns = !(region & 1); 1193 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); 1194 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1195 *exempt = (address & 0xeff00000) == 0xe0000000; 1196 *iregion = region; 1197 } 1198 1199 static const VMStateDescription armsse_vmstate = { 1200 .name = "iotkit", 1201 .version_id = 1, 1202 .minimum_version_id = 1, 1203 .fields = (VMStateField[]) { 1204 VMSTATE_UINT32(nsccfg, ARMSSE), 1205 VMSTATE_END_OF_LIST() 1206 } 1207 }; 1208 1209 static Property armsse_properties[] = { 1210 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 1211 MemoryRegion *), 1212 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 1213 DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), 1214 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 1215 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 1216 DEFINE_PROP_END_OF_LIST() 1217 }; 1218 1219 static void armsse_reset(DeviceState *dev) 1220 { 1221 ARMSSE *s = ARMSSE(dev); 1222 1223 s->nsccfg = 0; 1224 } 1225 1226 static void armsse_class_init(ObjectClass *klass, void *data) 1227 { 1228 DeviceClass *dc = DEVICE_CLASS(klass); 1229 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); 1230 ARMSSEClass *asc = ARMSSE_CLASS(klass); 1231 1232 dc->realize = armsse_realize; 1233 dc->vmsd = &armsse_vmstate; 1234 dc->props = armsse_properties; 1235 dc->reset = armsse_reset; 1236 iic->check = armsse_idau_check; 1237 asc->info = data; 1238 } 1239 1240 static const TypeInfo armsse_info = { 1241 .name = TYPE_ARMSSE, 1242 .parent = TYPE_SYS_BUS_DEVICE, 1243 .instance_size = sizeof(ARMSSE), 1244 .instance_init = armsse_init, 1245 .abstract = true, 1246 .interfaces = (InterfaceInfo[]) { 1247 { TYPE_IDAU_INTERFACE }, 1248 { } 1249 } 1250 }; 1251 1252 static void armsse_register_types(void) 1253 { 1254 int i; 1255 1256 type_register_static(&armsse_info); 1257 1258 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) { 1259 TypeInfo ti = { 1260 .name = armsse_variants[i].name, 1261 .parent = TYPE_ARMSSE, 1262 .class_init = armsse_class_init, 1263 .class_data = (void *)&armsse_variants[i], 1264 }; 1265 type_register(&ti); 1266 } 1267 } 1268 1269 type_init(armsse_register_types); 1270