1 /* 2 * Arm SSE (Subsystems for Embedded): IoTKit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qemu/bitops.h" 16 #include "qapi/error.h" 17 #include "trace.h" 18 #include "hw/sysbus.h" 19 #include "migration/vmstate.h" 20 #include "hw/registerfields.h" 21 #include "hw/arm/armsse.h" 22 #include "hw/arm/boot.h" 23 #include "hw/irq.h" 24 #include "hw/qdev-clock.h" 25 26 /* Format of the System Information block SYS_CONFIG register */ 27 typedef enum SysConfigFormat { 28 IoTKitFormat, 29 SSE200Format, 30 } SysConfigFormat; 31 32 struct ARMSSEInfo { 33 const char *name; 34 int sram_banks; 35 int num_cpus; 36 uint32_t sys_version; 37 uint32_t cpuwait_rst; 38 SysConfigFormat sys_config_format; 39 bool has_mhus; 40 bool has_ppus; 41 bool has_cachectrl; 42 bool has_cpusecctrl; 43 bool has_cpuid; 44 Property *props; 45 }; 46 47 static Property iotkit_properties[] = { 48 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 49 MemoryRegion *), 50 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 51 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 52 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 53 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), 54 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), 55 DEFINE_PROP_END_OF_LIST() 56 }; 57 58 static Property armsse_properties[] = { 59 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 60 MemoryRegion *), 61 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 62 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 63 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 64 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), 65 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), 66 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), 67 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), 68 DEFINE_PROP_END_OF_LIST() 69 }; 70 71 static const ARMSSEInfo armsse_variants[] = { 72 { 73 .name = TYPE_IOTKIT, 74 .sram_banks = 1, 75 .num_cpus = 1, 76 .sys_version = 0x41743, 77 .cpuwait_rst = 0, 78 .sys_config_format = IoTKitFormat, 79 .has_mhus = false, 80 .has_ppus = false, 81 .has_cachectrl = false, 82 .has_cpusecctrl = false, 83 .has_cpuid = false, 84 .props = iotkit_properties, 85 }, 86 { 87 .name = TYPE_SSE200, 88 .sram_banks = 4, 89 .num_cpus = 2, 90 .sys_version = 0x22041743, 91 .cpuwait_rst = 2, 92 .sys_config_format = SSE200Format, 93 .has_mhus = true, 94 .has_ppus = true, 95 .has_cachectrl = true, 96 .has_cpusecctrl = true, 97 .has_cpuid = true, 98 .props = armsse_properties, 99 }, 100 }; 101 102 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) 103 { 104 /* Return the SYS_CONFIG value for this SSE */ 105 uint32_t sys_config; 106 107 switch (info->sys_config_format) { 108 case IoTKitFormat: 109 sys_config = 0; 110 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 111 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); 112 break; 113 case SSE200Format: 114 sys_config = 0; 115 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 116 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 117 sys_config = deposit32(sys_config, 24, 4, 2); 118 if (info->num_cpus > 1) { 119 sys_config = deposit32(sys_config, 10, 1, 1); 120 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1); 121 sys_config = deposit32(sys_config, 28, 4, 2); 122 } 123 break; 124 default: 125 g_assert_not_reached(); 126 } 127 return sys_config; 128 } 129 130 /* Clock frequency in HZ of the 32KHz "slow clock" */ 131 #define S32KCLK (32 * 1000) 132 133 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ 134 static bool irq_is_common[32] = { 135 [0 ... 5] = true, 136 /* 6, 7: per-CPU MHU interrupts */ 137 [8 ... 12] = true, 138 /* 13: per-CPU icache interrupt */ 139 /* 14: reserved */ 140 [15 ... 20] = true, 141 /* 21: reserved */ 142 [22 ... 26] = true, 143 /* 27: reserved */ 144 /* 28, 29: per-CPU CTI interrupts */ 145 /* 30, 31: reserved */ 146 }; 147 148 /* 149 * Create an alias region in @container of @size bytes starting at @base 150 * which mirrors the memory starting at @orig. 151 */ 152 static void make_alias(ARMSSE *s, MemoryRegion *mr, MemoryRegion *container, 153 const char *name, hwaddr base, hwaddr size, hwaddr orig) 154 { 155 memory_region_init_alias(mr, NULL, name, container, orig, size); 156 /* The alias is even lower priority than unimplemented_device regions */ 157 memory_region_add_subregion_overlap(container, base, mr, -1500); 158 } 159 160 static void irq_status_forwarder(void *opaque, int n, int level) 161 { 162 qemu_irq destirq = opaque; 163 164 qemu_set_irq(destirq, level); 165 } 166 167 static void nsccfg_handler(void *opaque, int n, int level) 168 { 169 ARMSSE *s = ARM_SSE(opaque); 170 171 s->nsccfg = level; 172 } 173 174 static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) 175 { 176 /* Each of the 4 AHB and 4 APB PPCs that might be present in a 177 * system using the ARMSSE has a collection of control lines which 178 * are provided by the security controller and which we want to 179 * expose as control lines on the ARMSSE device itself, so the 180 * code using the ARMSSE can wire them up to the PPCs. 181 */ 182 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; 183 DeviceState *armssedev = DEVICE(s); 184 DeviceState *dev_secctl = DEVICE(&s->secctl); 185 DeviceState *dev_splitter = DEVICE(splitter); 186 char *name; 187 188 name = g_strdup_printf("%s_nonsec", ppcname); 189 qdev_pass_gpios(dev_secctl, armssedev, name); 190 g_free(name); 191 name = g_strdup_printf("%s_ap", ppcname); 192 qdev_pass_gpios(dev_secctl, armssedev, name); 193 g_free(name); 194 name = g_strdup_printf("%s_irq_enable", ppcname); 195 qdev_pass_gpios(dev_secctl, armssedev, name); 196 g_free(name); 197 name = g_strdup_printf("%s_irq_clear", ppcname); 198 qdev_pass_gpios(dev_secctl, armssedev, name); 199 g_free(name); 200 201 /* irq_status is a little more tricky, because we need to 202 * split it so we can send it both to the security controller 203 * and to our OR gate for the NVIC interrupt line. 204 * Connect up the splitter's outputs, and create a GPIO input 205 * which will pass the line state to the input splitter. 206 */ 207 name = g_strdup_printf("%s_irq_status", ppcname); 208 qdev_connect_gpio_out(dev_splitter, 0, 209 qdev_get_gpio_in_named(dev_secctl, 210 name, 0)); 211 qdev_connect_gpio_out(dev_splitter, 1, 212 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); 213 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); 214 qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder, 215 s->irq_status_in[ppcnum], name, 1); 216 g_free(name); 217 } 218 219 static void armsse_forward_sec_resp_cfg(ARMSSE *s) 220 { 221 /* Forward the 3rd output from the splitter device as a 222 * named GPIO output of the armsse object. 223 */ 224 DeviceState *dev = DEVICE(s); 225 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); 226 227 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); 228 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, 229 s->sec_resp_cfg, 1); 230 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); 231 } 232 233 static void armsse_mainclk_update(void *opaque, ClockEvent event) 234 { 235 ARMSSE *s = ARM_SSE(opaque); 236 237 /* 238 * Set system_clock_scale from our Clock input; this is what 239 * controls the tick rate of the CPU SysTick timer. 240 */ 241 system_clock_scale = clock_ticks_to_ns(s->mainclk, 1); 242 } 243 244 static void armsse_init(Object *obj) 245 { 246 ARMSSE *s = ARM_SSE(obj); 247 ARMSSEClass *asc = ARM_SSE_GET_CLASS(obj); 248 const ARMSSEInfo *info = asc->info; 249 int i; 250 251 assert(info->sram_banks <= MAX_SRAM_BANKS); 252 assert(info->num_cpus <= SSE_MAX_CPUS); 253 254 s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", 255 armsse_mainclk_update, s, ClockUpdate); 256 s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0); 257 258 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); 259 260 for (i = 0; i < info->num_cpus; i++) { 261 /* 262 * We put each CPU in its own cluster as they are logically 263 * distinct and may be configured differently. 264 */ 265 char *name; 266 267 name = g_strdup_printf("cluster%d", i); 268 object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER); 269 qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); 270 g_free(name); 271 272 name = g_strdup_printf("armv7m%d", i); 273 object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i], 274 TYPE_ARMV7M); 275 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", 276 ARM_CPU_TYPE_NAME("cortex-m33")); 277 g_free(name); 278 name = g_strdup_printf("arm-sse-cpu-container%d", i); 279 memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); 280 g_free(name); 281 if (i > 0) { 282 name = g_strdup_printf("arm-sse-container-alias%d", i); 283 memory_region_init_alias(&s->container_alias[i - 1], obj, 284 name, &s->container, 0, UINT64_MAX); 285 g_free(name); 286 } 287 } 288 289 object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL); 290 object_initialize_child(obj, "apb-ppc0", &s->apb_ppc0, TYPE_TZ_PPC); 291 object_initialize_child(obj, "apb-ppc1", &s->apb_ppc1, TYPE_TZ_PPC); 292 for (i = 0; i < info->sram_banks; i++) { 293 char *name = g_strdup_printf("mpc%d", i); 294 object_initialize_child(obj, name, &s->mpc[i], TYPE_TZ_MPC); 295 g_free(name); 296 } 297 object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate, 298 TYPE_OR_IRQ); 299 300 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 301 char *name = g_strdup_printf("mpc-irq-splitter-%d", i); 302 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 303 304 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 305 g_free(name); 306 } 307 object_initialize_child(obj, "timer0", &s->timer0, TYPE_CMSDK_APB_TIMER); 308 object_initialize_child(obj, "timer1", &s->timer1, TYPE_CMSDK_APB_TIMER); 309 object_initialize_child(obj, "s32ktimer", &s->s32ktimer, 310 TYPE_CMSDK_APB_TIMER); 311 object_initialize_child(obj, "dualtimer", &s->dualtimer, 312 TYPE_CMSDK_APB_DUALTIMER); 313 object_initialize_child(obj, "s32kwatchdog", &s->s32kwatchdog, 314 TYPE_CMSDK_APB_WATCHDOG); 315 object_initialize_child(obj, "nswatchdog", &s->nswatchdog, 316 TYPE_CMSDK_APB_WATCHDOG); 317 object_initialize_child(obj, "swatchdog", &s->swatchdog, 318 TYPE_CMSDK_APB_WATCHDOG); 319 object_initialize_child(obj, "armsse-sysctl", &s->sysctl, 320 TYPE_IOTKIT_SYSCTL); 321 object_initialize_child(obj, "armsse-sysinfo", &s->sysinfo, 322 TYPE_IOTKIT_SYSINFO); 323 if (info->has_mhus) { 324 object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); 325 object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); 326 } 327 if (info->has_ppus) { 328 for (i = 0; i < info->num_cpus; i++) { 329 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 330 int ppuidx = CPU0CORE_PPU + i; 331 332 object_initialize_child(obj, name, &s->ppu[ppuidx], 333 TYPE_UNIMPLEMENTED_DEVICE); 334 g_free(name); 335 } 336 object_initialize_child(obj, "DBG_PPU", &s->ppu[DBG_PPU], 337 TYPE_UNIMPLEMENTED_DEVICE); 338 for (i = 0; i < info->sram_banks; i++) { 339 char *name = g_strdup_printf("RAM%d_PPU", i); 340 int ppuidx = RAM0_PPU + i; 341 342 object_initialize_child(obj, name, &s->ppu[ppuidx], 343 TYPE_UNIMPLEMENTED_DEVICE); 344 g_free(name); 345 } 346 } 347 if (info->has_cachectrl) { 348 for (i = 0; i < info->num_cpus; i++) { 349 char *name = g_strdup_printf("cachectrl%d", i); 350 351 object_initialize_child(obj, name, &s->cachectrl[i], 352 TYPE_UNIMPLEMENTED_DEVICE); 353 g_free(name); 354 } 355 } 356 if (info->has_cpusecctrl) { 357 for (i = 0; i < info->num_cpus; i++) { 358 char *name = g_strdup_printf("cpusecctrl%d", i); 359 360 object_initialize_child(obj, name, &s->cpusecctrl[i], 361 TYPE_UNIMPLEMENTED_DEVICE); 362 g_free(name); 363 } 364 } 365 if (info->has_cpuid) { 366 for (i = 0; i < info->num_cpus; i++) { 367 char *name = g_strdup_printf("cpuid%d", i); 368 369 object_initialize_child(obj, name, &s->cpuid[i], 370 TYPE_ARMSSE_CPUID); 371 g_free(name); 372 } 373 } 374 object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ); 375 object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, 376 TYPE_OR_IRQ); 377 object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter, 378 TYPE_SPLIT_IRQ); 379 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 380 char *name = g_strdup_printf("ppc-irq-splitter-%d", i); 381 SplitIRQ *splitter = &s->ppc_irq_splitter[i]; 382 383 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 384 g_free(name); 385 } 386 if (info->num_cpus > 1) { 387 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 388 if (irq_is_common[i]) { 389 char *name = g_strdup_printf("cpu-irq-splitter%d", i); 390 SplitIRQ *splitter = &s->cpu_irq_splitter[i]; 391 392 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 393 g_free(name); 394 } 395 } 396 } 397 } 398 399 static void armsse_exp_irq(void *opaque, int n, int level) 400 { 401 qemu_irq *irqarray = opaque; 402 403 qemu_set_irq(irqarray[n], level); 404 } 405 406 static void armsse_mpcexp_status(void *opaque, int n, int level) 407 { 408 ARMSSE *s = ARM_SSE(opaque); 409 qemu_set_irq(s->mpcexp_status_in[n], level); 410 } 411 412 static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno) 413 { 414 /* 415 * Return a qemu_irq which can be used to signal IRQ n to 416 * all CPUs in the SSE. 417 */ 418 ARMSSEClass *asc = ARM_SSE_GET_CLASS(s); 419 const ARMSSEInfo *info = asc->info; 420 421 assert(irq_is_common[irqno]); 422 423 if (info->num_cpus == 1) { 424 /* Only one CPU -- just connect directly to it */ 425 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); 426 } else { 427 /* Connect to the splitter which feeds all CPUs */ 428 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); 429 } 430 } 431 432 static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) 433 { 434 /* Map a PPU unimplemented device stub */ 435 DeviceState *dev = DEVICE(&s->ppu[ppuidx]); 436 437 qdev_prop_set_string(dev, "name", name); 438 qdev_prop_set_uint64(dev, "size", 0x1000); 439 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 440 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); 441 } 442 443 static void armsse_realize(DeviceState *dev, Error **errp) 444 { 445 ARMSSE *s = ARM_SSE(dev); 446 ARMSSEClass *asc = ARM_SSE_GET_CLASS(dev); 447 const ARMSSEInfo *info = asc->info; 448 int i; 449 MemoryRegion *mr; 450 Error *err = NULL; 451 SysBusDevice *sbd_apb_ppc0; 452 SysBusDevice *sbd_secctl; 453 DeviceState *dev_apb_ppc0; 454 DeviceState *dev_apb_ppc1; 455 DeviceState *dev_secctl; 456 DeviceState *dev_splitter; 457 uint32_t addr_width_max; 458 459 if (!s->board_memory) { 460 error_setg(errp, "memory property was not set"); 461 return; 462 } 463 464 if (!clock_has_source(s->mainclk)) { 465 error_setg(errp, "MAINCLK clock was not connected"); 466 } 467 if (!clock_has_source(s->s32kclk)) { 468 error_setg(errp, "S32KCLK clock was not connected"); 469 } 470 471 assert(info->num_cpus <= SSE_MAX_CPUS); 472 473 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ 474 assert(is_power_of_2(info->sram_banks)); 475 addr_width_max = 24 - ctz32(info->sram_banks); 476 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { 477 error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d", 478 addr_width_max); 479 return; 480 } 481 482 /* Handling of which devices should be available only to secure 483 * code is usually done differently for M profile than for A profile. 484 * Instead of putting some devices only into the secure address space, 485 * devices exist in both address spaces but with hard-wired security 486 * permissions that will cause the CPU to fault for non-secure accesses. 487 * 488 * The ARMSSE has an IDAU (Implementation Defined Access Unit), 489 * which specifies hard-wired security permissions for different 490 * areas of the physical address space. For the ARMSSE IDAU, the 491 * top 4 bits of the physical address are the IDAU region ID, and 492 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS 493 * region, otherwise it is an S region. 494 * 495 * The various devices and RAMs are generally all mapped twice, 496 * once into a region that the IDAU defines as secure and once 497 * into a non-secure region. They sit behind either a Memory 498 * Protection Controller (for RAM) or a Peripheral Protection 499 * Controller (for devices), which allow a more fine grained 500 * configuration of whether non-secure accesses are permitted. 501 * 502 * (The other place that guest software can configure security 503 * permissions is in the architected SAU (Security Attribution 504 * Unit), which is entirely inside the CPU. The IDAU can upgrade 505 * the security attributes for a region to more restrictive than 506 * the SAU specifies, but cannot downgrade them.) 507 * 508 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff 509 * 0x20000000..0x2007ffff 32KB FPGA block RAM 510 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff 511 * 0x40000000..0x4000ffff base peripheral region 1 512 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) 513 * 0x40020000..0x4002ffff system control element peripherals 514 * 0x40080000..0x400fffff base peripheral region 2 515 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff 516 */ 517 518 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); 519 520 for (i = 0; i < info->num_cpus; i++) { 521 DeviceState *cpudev = DEVICE(&s->armv7m[i]); 522 Object *cpuobj = OBJECT(&s->armv7m[i]); 523 int j; 524 char *gpioname; 525 526 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32); 527 /* 528 * In real hardware the initial Secure VTOR is set from the INITSVTOR* 529 * registers in the IoT Kit System Control Register block. In QEMU 530 * we set the initial value here, and also the reset value of the 531 * sysctl register, from this object's QOM init-svtor property. 532 * If the guest changes the INITSVTOR* registers at runtime then the 533 * code in iotkit-sysctl.c will update the CPU init-svtor property 534 * (which will then take effect on the next CPU warm-reset). 535 * 536 * Note that typically a board using the SSE-200 will have a system 537 * control processor whose boot firmware initializes the INITSVTOR* 538 * registers before powering up the CPUs. QEMU doesn't emulate 539 * the control processor, so instead we behave in the way that the 540 * firmware does: the initial value should be set by the board code 541 * (using the init-svtor property on the ARMSSE object) to match 542 * whatever its firmware does. 543 */ 544 qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); 545 /* 546 * CPUs start powered down if the corresponding bit in the CPUWAIT 547 * register is 1. In real hardware the CPUWAIT register reset value is 548 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and 549 * CPUWAIT1_RST parameters), but since all the boards we care about 550 * start CPU0 and leave CPU1 powered off, we hard-code that in 551 * info->cpuwait_rst for now. We can add QOM properties for this 552 * later if necessary. 553 */ 554 if (extract32(info->cpuwait_rst, i, 1)) { 555 if (!object_property_set_bool(cpuobj, "start-powered-off", true, 556 errp)) { 557 return; 558 } 559 } 560 if (!s->cpu_fpu[i]) { 561 if (!object_property_set_bool(cpuobj, "vfp", false, errp)) { 562 return; 563 } 564 } 565 if (!s->cpu_dsp[i]) { 566 if (!object_property_set_bool(cpuobj, "dsp", false, errp)) { 567 return; 568 } 569 } 570 571 if (i > 0) { 572 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 573 &s->container_alias[i - 1], -1); 574 } else { 575 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 576 &s->container, -1); 577 } 578 object_property_set_link(cpuobj, "memory", 579 OBJECT(&s->cpu_container[i]), &error_abort); 580 object_property_set_link(cpuobj, "idau", OBJECT(s), &error_abort); 581 if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj), errp)) { 582 return; 583 } 584 /* 585 * The cluster must be realized after the armv7m container, as 586 * the container's CPU object is only created on realize, and the 587 * CPU must exist and have been parented into the cluster before 588 * the cluster is realized. 589 */ 590 if (!qdev_realize(DEVICE(&s->cluster[i]), NULL, errp)) { 591 return; 592 } 593 594 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ 595 s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); 596 for (j = 0; j < s->exp_numirq; j++) { 597 s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32); 598 } 599 if (i == 0) { 600 gpioname = g_strdup("EXP_IRQ"); 601 } else { 602 gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i); 603 } 604 qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq, 605 s->exp_irqs[i], 606 gpioname, s->exp_numirq); 607 g_free(gpioname); 608 } 609 610 /* Wire up the splitters that connect common IRQs to all CPUs */ 611 if (info->num_cpus > 1) { 612 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 613 if (irq_is_common[i]) { 614 Object *splitter = OBJECT(&s->cpu_irq_splitter[i]); 615 DeviceState *devs = DEVICE(splitter); 616 int cpunum; 617 618 if (!object_property_set_int(splitter, "num-lines", 619 info->num_cpus, errp)) { 620 return; 621 } 622 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 623 return; 624 } 625 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 626 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 627 628 qdev_connect_gpio_out(devs, cpunum, 629 qdev_get_gpio_in(cpudev, i)); 630 } 631 } 632 } 633 } 634 635 /* Set up the big aliases first */ 636 make_alias(s, &s->alias1, &s->container, "alias 1", 637 0x10000000, 0x10000000, 0x00000000); 638 make_alias(s, &s->alias2, &s->container, 639 "alias 2", 0x30000000, 0x10000000, 0x20000000); 640 /* The 0x50000000..0x5fffffff region is not a pure alias: it has 641 * a few extra devices that only appear there (generally the 642 * control interfaces for the protection controllers). 643 * We implement this by mapping those devices over the top of this 644 * alias MR at a higher priority. Some of the devices in this range 645 * are per-CPU, so we must put this alias in the per-cpu containers. 646 */ 647 for (i = 0; i < info->num_cpus; i++) { 648 make_alias(s, &s->alias3[i], &s->cpu_container[i], 649 "alias 3", 0x50000000, 0x10000000, 0x40000000); 650 } 651 652 /* Security controller */ 653 if (!sysbus_realize(SYS_BUS_DEVICE(&s->secctl), errp)) { 654 return; 655 } 656 sbd_secctl = SYS_BUS_DEVICE(&s->secctl); 657 dev_secctl = DEVICE(&s->secctl); 658 sysbus_mmio_map(sbd_secctl, 0, 0x50080000); 659 sysbus_mmio_map(sbd_secctl, 1, 0x40080000); 660 661 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); 662 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); 663 664 /* The sec_resp_cfg output from the security controller must be split into 665 * multiple lines, one for each of the PPCs within the ARMSSE and one 666 * that will be an output from the ARMSSE to the system. 667 */ 668 if (!object_property_set_int(OBJECT(&s->sec_resp_splitter), 669 "num-lines", 3, errp)) { 670 return; 671 } 672 if (!qdev_realize(DEVICE(&s->sec_resp_splitter), NULL, errp)) { 673 return; 674 } 675 dev_splitter = DEVICE(&s->sec_resp_splitter); 676 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, 677 qdev_get_gpio_in(dev_splitter, 0)); 678 679 /* Each SRAM bank lives behind its own Memory Protection Controller */ 680 for (i = 0; i < info->sram_banks; i++) { 681 char *ramname = g_strdup_printf("armsse.sram%d", i); 682 SysBusDevice *sbd_mpc; 683 uint32_t sram_bank_size = 1 << s->sram_addr_width; 684 685 memory_region_init_ram(&s->sram[i], NULL, ramname, 686 sram_bank_size, &err); 687 g_free(ramname); 688 if (err) { 689 error_propagate(errp, err); 690 return; 691 } 692 object_property_set_link(OBJECT(&s->mpc[i]), "downstream", 693 OBJECT(&s->sram[i]), &error_abort); 694 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mpc[i]), errp)) { 695 return; 696 } 697 /* Map the upstream end of the MPC into the right place... */ 698 sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); 699 memory_region_add_subregion(&s->container, 700 0x20000000 + i * sram_bank_size, 701 sysbus_mmio_get_region(sbd_mpc, 1)); 702 /* ...and its register interface */ 703 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, 704 sysbus_mmio_get_region(sbd_mpc, 0)); 705 } 706 707 /* We must OR together lines from the MPC splitters to go to the NVIC */ 708 if (!object_property_set_int(OBJECT(&s->mpc_irq_orgate), "num-lines", 709 IOTS_NUM_EXP_MPC + info->sram_banks, 710 errp)) { 711 return; 712 } 713 if (!qdev_realize(DEVICE(&s->mpc_irq_orgate), NULL, errp)) { 714 return; 715 } 716 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, 717 armsse_get_common_irq_in(s, 9)); 718 719 /* Devices behind APB PPC0: 720 * 0x40000000: timer0 721 * 0x40001000: timer1 722 * 0x40002000: dual timer 723 * 0x40003000: MHU0 (SSE-200 only) 724 * 0x40004000: MHU1 (SSE-200 only) 725 * We must configure and realize each downstream device and connect 726 * it to the appropriate PPC port; then we can realize the PPC and 727 * map its upstream ends to the right place in the container. 728 */ 729 qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); 730 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { 731 return; 732 } 733 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, 734 armsse_get_common_irq_in(s, 3)); 735 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); 736 object_property_set_link(OBJECT(&s->apb_ppc0), "port[0]", OBJECT(mr), 737 &error_abort); 738 739 qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); 740 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { 741 return; 742 } 743 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, 744 armsse_get_common_irq_in(s, 4)); 745 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); 746 object_property_set_link(OBJECT(&s->apb_ppc0), "port[1]", OBJECT(mr), 747 &error_abort); 748 749 qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); 750 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { 751 return; 752 } 753 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dualtimer), 0, 754 armsse_get_common_irq_in(s, 5)); 755 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); 756 object_property_set_link(OBJECT(&s->apb_ppc0), "port[2]", OBJECT(mr), 757 &error_abort); 758 759 if (info->has_mhus) { 760 /* 761 * An SSE-200 with only one CPU should have only one MHU created, 762 * with the region where the second MHU usually is being RAZ/WI. 763 * We don't implement that SSE-200 config; if we want to support 764 * it then this code needs to be enhanced to handle creating the 765 * RAZ/WI region instead of the second MHU. 766 */ 767 assert(info->num_cpus == ARRAY_SIZE(s->mhu)); 768 769 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { 770 char *port; 771 int cpunum; 772 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]); 773 774 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mhu[i]), errp)) { 775 return; 776 } 777 port = g_strdup_printf("port[%d]", i + 3); 778 mr = sysbus_mmio_get_region(mhu_sbd, 0); 779 object_property_set_link(OBJECT(&s->apb_ppc0), port, OBJECT(mr), 780 &error_abort); 781 g_free(port); 782 783 /* 784 * Each MHU has an irq line for each CPU: 785 * MHU 0 irq line 0 -> CPU 0 IRQ 6 786 * MHU 0 irq line 1 -> CPU 1 IRQ 6 787 * MHU 1 irq line 0 -> CPU 0 IRQ 7 788 * MHU 1 irq line 1 -> CPU 1 IRQ 7 789 */ 790 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 791 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 792 793 sysbus_connect_irq(mhu_sbd, cpunum, 794 qdev_get_gpio_in(cpudev, 6 + i)); 795 } 796 } 797 } 798 799 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc0), errp)) { 800 return; 801 } 802 803 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); 804 dev_apb_ppc0 = DEVICE(&s->apb_ppc0); 805 806 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); 807 memory_region_add_subregion(&s->container, 0x40000000, mr); 808 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); 809 memory_region_add_subregion(&s->container, 0x40001000, mr); 810 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); 811 memory_region_add_subregion(&s->container, 0x40002000, mr); 812 if (info->has_mhus) { 813 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3); 814 memory_region_add_subregion(&s->container, 0x40003000, mr); 815 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4); 816 memory_region_add_subregion(&s->container, 0x40004000, mr); 817 } 818 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { 819 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, 820 qdev_get_gpio_in_named(dev_apb_ppc0, 821 "cfg_nonsec", i)); 822 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, 823 qdev_get_gpio_in_named(dev_apb_ppc0, 824 "cfg_ap", i)); 825 } 826 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, 827 qdev_get_gpio_in_named(dev_apb_ppc0, 828 "irq_enable", 0)); 829 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, 830 qdev_get_gpio_in_named(dev_apb_ppc0, 831 "irq_clear", 0)); 832 qdev_connect_gpio_out(dev_splitter, 0, 833 qdev_get_gpio_in_named(dev_apb_ppc0, 834 "cfg_sec_resp", 0)); 835 836 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external 837 * ones) are sent individually to the security controller, and also 838 * ORed together to give a single combined PPC interrupt to the NVIC. 839 */ 840 if (!object_property_set_int(OBJECT(&s->ppc_irq_orgate), 841 "num-lines", NUM_PPCS, errp)) { 842 return; 843 } 844 if (!qdev_realize(DEVICE(&s->ppc_irq_orgate), NULL, errp)) { 845 return; 846 } 847 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, 848 armsse_get_common_irq_in(s, 10)); 849 850 /* 851 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): 852 * private per-CPU region (all these devices are SSE-200 only): 853 * 0x50010000: L1 icache control registers 854 * 0x50011000: CPUSECCTRL (CPU local security control registers) 855 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block 856 */ 857 if (info->has_cachectrl) { 858 for (i = 0; i < info->num_cpus; i++) { 859 char *name = g_strdup_printf("cachectrl%d", i); 860 MemoryRegion *mr; 861 862 qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); 863 g_free(name); 864 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); 865 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cachectrl[i]), errp)) { 866 return; 867 } 868 869 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); 870 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); 871 } 872 } 873 if (info->has_cpusecctrl) { 874 for (i = 0; i < info->num_cpus; i++) { 875 char *name = g_strdup_printf("CPUSECCTRL%d", i); 876 MemoryRegion *mr; 877 878 qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); 879 g_free(name); 880 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); 881 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpusecctrl[i]), errp)) { 882 return; 883 } 884 885 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); 886 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); 887 } 888 } 889 if (info->has_cpuid) { 890 for (i = 0; i < info->num_cpus; i++) { 891 MemoryRegion *mr; 892 893 qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); 894 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpuid[i]), errp)) { 895 return; 896 } 897 898 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); 899 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); 900 } 901 } 902 903 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */ 904 /* Devices behind APB PPC1: 905 * 0x4002f000: S32K timer 906 */ 907 qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); 908 if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { 909 return; 910 } 911 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, 912 armsse_get_common_irq_in(s, 2)); 913 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); 914 object_property_set_link(OBJECT(&s->apb_ppc1), "port[0]", OBJECT(mr), 915 &error_abort); 916 917 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc1), errp)) { 918 return; 919 } 920 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); 921 memory_region_add_subregion(&s->container, 0x4002f000, mr); 922 923 dev_apb_ppc1 = DEVICE(&s->apb_ppc1); 924 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, 925 qdev_get_gpio_in_named(dev_apb_ppc1, 926 "cfg_nonsec", 0)); 927 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, 928 qdev_get_gpio_in_named(dev_apb_ppc1, 929 "cfg_ap", 0)); 930 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, 931 qdev_get_gpio_in_named(dev_apb_ppc1, 932 "irq_enable", 0)); 933 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, 934 qdev_get_gpio_in_named(dev_apb_ppc1, 935 "irq_clear", 0)); 936 qdev_connect_gpio_out(dev_splitter, 1, 937 qdev_get_gpio_in_named(dev_apb_ppc1, 938 "cfg_sec_resp", 0)); 939 940 if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION", 941 info->sys_version, errp)) { 942 return; 943 } 944 if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG", 945 armsse_sys_config_value(s, info), errp)) { 946 return; 947 } 948 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), errp)) { 949 return; 950 } 951 /* System information registers */ 952 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); 953 /* System control registers */ 954 object_property_set_int(OBJECT(&s->sysctl), "SYS_VERSION", 955 info->sys_version, &error_abort); 956 object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST", 957 info->cpuwait_rst, &error_abort); 958 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST", 959 s->init_svtor, &error_abort); 960 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST", 961 s->init_svtor, &error_abort); 962 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysctl), errp)) { 963 return; 964 } 965 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); 966 967 if (info->has_ppus) { 968 /* CPUnCORE_PPU for each CPU */ 969 for (i = 0; i < info->num_cpus; i++) { 970 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 971 972 map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); 973 /* 974 * We don't support CPU debug so don't create the 975 * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. 976 */ 977 g_free(name); 978 } 979 map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); 980 981 for (i = 0; i < info->sram_banks; i++) { 982 char *name = g_strdup_printf("RAM%d_PPU", i); 983 984 map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); 985 g_free(name); 986 } 987 } 988 989 /* This OR gate wires together outputs from the secure watchdogs to NMI */ 990 if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2, 991 errp)) { 992 return; 993 } 994 if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) { 995 return; 996 } 997 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, 998 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); 999 1000 qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); 1001 if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { 1002 return; 1003 } 1004 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 1005 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 0)); 1006 sysbus_mmio_map(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 0x5002e000); 1007 1008 /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ 1009 1010 qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); 1011 if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { 1012 return; 1013 } 1014 sysbus_connect_irq(SYS_BUS_DEVICE(&s->nswatchdog), 0, 1015 armsse_get_common_irq_in(s, 1)); 1016 sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); 1017 1018 qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); 1019 if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { 1020 return; 1021 } 1022 sysbus_connect_irq(SYS_BUS_DEVICE(&s->swatchdog), 0, 1023 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 1)); 1024 sysbus_mmio_map(SYS_BUS_DEVICE(&s->swatchdog), 0, 0x50081000); 1025 1026 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 1027 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); 1028 1029 if (!object_property_set_int(splitter, "num-lines", 2, errp)) { 1030 return; 1031 } 1032 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1033 return; 1034 } 1035 } 1036 1037 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { 1038 char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); 1039 1040 armsse_forward_ppc(s, ppcname, i); 1041 g_free(ppcname); 1042 } 1043 1044 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { 1045 char *ppcname = g_strdup_printf("apb_ppcexp%d", i); 1046 1047 armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); 1048 g_free(ppcname); 1049 } 1050 1051 for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { 1052 /* Wire up IRQ splitter for internal PPCs */ 1053 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); 1054 char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", 1055 i - NUM_EXTERNAL_PPCS); 1056 TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; 1057 1058 qdev_connect_gpio_out(devs, 0, 1059 qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); 1060 qdev_connect_gpio_out(devs, 1, 1061 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); 1062 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, 1063 qdev_get_gpio_in(devs, 0)); 1064 g_free(gpioname); 1065 } 1066 1067 /* Wire up the splitters for the MPC IRQs */ 1068 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 1069 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 1070 DeviceState *dev_splitter = DEVICE(splitter); 1071 1072 if (!object_property_set_int(OBJECT(splitter), "num-lines", 2, 1073 errp)) { 1074 return; 1075 } 1076 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1077 return; 1078 } 1079 1080 if (i < IOTS_NUM_EXP_MPC) { 1081 /* Splitter input is from GPIO input line */ 1082 s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0); 1083 qdev_connect_gpio_out(dev_splitter, 0, 1084 qdev_get_gpio_in_named(dev_secctl, 1085 "mpcexp_status", i)); 1086 } else { 1087 /* Splitter input is from our own MPC */ 1088 qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]), 1089 "irq", 0, 1090 qdev_get_gpio_in(dev_splitter, 0)); 1091 qdev_connect_gpio_out(dev_splitter, 0, 1092 qdev_get_gpio_in_named(dev_secctl, 1093 "mpc_status", 1094 i - IOTS_NUM_EXP_MPC)); 1095 } 1096 1097 qdev_connect_gpio_out(dev_splitter, 1, 1098 qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i)); 1099 } 1100 /* Create GPIO inputs which will pass the line state for our 1101 * mpcexp_irq inputs to the correct splitter devices. 1102 */ 1103 qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status", 1104 IOTS_NUM_EXP_MPC); 1105 1106 armsse_forward_sec_resp_cfg(s); 1107 1108 /* Forward the MSC related signals */ 1109 qdev_pass_gpios(dev_secctl, dev, "mscexp_status"); 1110 qdev_pass_gpios(dev_secctl, dev, "mscexp_clear"); 1111 qdev_pass_gpios(dev_secctl, dev, "mscexp_ns"); 1112 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, 1113 armsse_get_common_irq_in(s, 11)); 1114 1115 /* 1116 * Expose our container region to the board model; this corresponds 1117 * to the AHB Slave Expansion ports which allow bus master devices 1118 * (eg DMA controllers) in the board model to make transactions into 1119 * devices in the ARMSSE. 1120 */ 1121 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); 1122 1123 /* Set initial system_clock_scale from MAINCLK */ 1124 armsse_mainclk_update(s, ClockUpdate); 1125 } 1126 1127 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, 1128 int *iregion, bool *exempt, bool *ns, bool *nsc) 1129 { 1130 /* 1131 * For ARMSSE systems the IDAU responses are simple logical functions 1132 * of the address bits. The NSC attribute is guest-adjustable via the 1133 * NSCCFG register in the security controller. 1134 */ 1135 ARMSSE *s = ARM_SSE(ii); 1136 int region = extract32(address, 28, 4); 1137 1138 *ns = !(region & 1); 1139 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); 1140 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1141 *exempt = (address & 0xeff00000) == 0xe0000000; 1142 *iregion = region; 1143 } 1144 1145 static const VMStateDescription armsse_vmstate = { 1146 .name = "iotkit", 1147 .version_id = 2, 1148 .minimum_version_id = 2, 1149 .fields = (VMStateField[]) { 1150 VMSTATE_CLOCK(mainclk, ARMSSE), 1151 VMSTATE_CLOCK(s32kclk, ARMSSE), 1152 VMSTATE_UINT32(nsccfg, ARMSSE), 1153 VMSTATE_END_OF_LIST() 1154 } 1155 }; 1156 1157 static void armsse_reset(DeviceState *dev) 1158 { 1159 ARMSSE *s = ARM_SSE(dev); 1160 1161 s->nsccfg = 0; 1162 } 1163 1164 static void armsse_class_init(ObjectClass *klass, void *data) 1165 { 1166 DeviceClass *dc = DEVICE_CLASS(klass); 1167 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); 1168 ARMSSEClass *asc = ARM_SSE_CLASS(klass); 1169 const ARMSSEInfo *info = data; 1170 1171 dc->realize = armsse_realize; 1172 dc->vmsd = &armsse_vmstate; 1173 device_class_set_props(dc, info->props); 1174 dc->reset = armsse_reset; 1175 iic->check = armsse_idau_check; 1176 asc->info = info; 1177 } 1178 1179 static const TypeInfo armsse_info = { 1180 .name = TYPE_ARM_SSE, 1181 .parent = TYPE_SYS_BUS_DEVICE, 1182 .instance_size = sizeof(ARMSSE), 1183 .class_size = sizeof(ARMSSEClass), 1184 .instance_init = armsse_init, 1185 .abstract = true, 1186 .interfaces = (InterfaceInfo[]) { 1187 { TYPE_IDAU_INTERFACE }, 1188 { } 1189 } 1190 }; 1191 1192 static void armsse_register_types(void) 1193 { 1194 int i; 1195 1196 type_register_static(&armsse_info); 1197 1198 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) { 1199 TypeInfo ti = { 1200 .name = armsse_variants[i].name, 1201 .parent = TYPE_ARM_SSE, 1202 .class_init = armsse_class_init, 1203 .class_data = (void *)&armsse_variants[i], 1204 }; 1205 type_register(&ti); 1206 } 1207 } 1208 1209 type_init(armsse_register_types); 1210