1 /* 2 * Arm SSE (Subsystems for Embedded): IoTKit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qemu/bitops.h" 16 #include "qapi/error.h" 17 #include "trace.h" 18 #include "hw/sysbus.h" 19 #include "migration/vmstate.h" 20 #include "hw/registerfields.h" 21 #include "hw/arm/armsse.h" 22 #include "hw/arm/armsse-version.h" 23 #include "hw/arm/boot.h" 24 #include "hw/irq.h" 25 #include "hw/qdev-clock.h" 26 27 /* 28 * The SSE-300 puts some devices in different places to the 29 * SSE-200 (and original IoTKit). We use an array of these structs 30 * to define how each variant lays out these devices. (Parts of the 31 * SoC that are the same for all variants aren't handled via these 32 * data structures.) 33 */ 34 35 #define NO_IRQ -1 36 #define NO_PPC -1 37 /* 38 * Special values for ARMSSEDeviceInfo::irq to indicate that this 39 * device uses one of the inputs to the OR gate that feeds into the 40 * CPU NMI input. 41 */ 42 #define NMI_0 10000 43 #define NMI_1 10001 44 45 typedef struct ARMSSEDeviceInfo { 46 const char *name; /* name to use for the QOM object; NULL terminates list */ 47 const char *type; /* QOM type name */ 48 unsigned int index; /* Which of the N devices of this type is this ? */ 49 hwaddr addr; 50 int ppc; /* Index of APB PPC this device is wired up to, or NO_PPC */ 51 int ppc_port; /* Port number of this device on the PPC */ 52 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */ 53 bool slowclk; /* true if device uses the slow 32KHz clock */ 54 } ARMSSEDeviceInfo; 55 56 struct ARMSSEInfo { 57 const char *name; 58 uint32_t sse_version; 59 int sram_banks; 60 int num_cpus; 61 uint32_t sys_version; 62 uint32_t iidr; 63 uint32_t cpuwait_rst; 64 bool has_mhus; 65 bool has_ppus; 66 bool has_cachectrl; 67 bool has_cpusecctrl; 68 bool has_cpuid; 69 Property *props; 70 const ARMSSEDeviceInfo *devinfo; 71 }; 72 73 static Property iotkit_properties[] = { 74 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 75 MemoryRegion *), 76 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 77 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 78 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 79 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), 80 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), 81 DEFINE_PROP_END_OF_LIST() 82 }; 83 84 static Property armsse_properties[] = { 85 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 86 MemoryRegion *), 87 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 88 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 89 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 90 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), 91 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), 92 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), 93 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), 94 DEFINE_PROP_END_OF_LIST() 95 }; 96 97 static const ARMSSEDeviceInfo sse200_devices[] = { 98 { 99 .name = "timer0", 100 .type = TYPE_CMSDK_APB_TIMER, 101 .index = 0, 102 .addr = 0x40000000, 103 .ppc = 0, 104 .ppc_port = 0, 105 .irq = 3, 106 }, 107 { 108 .name = "timer1", 109 .type = TYPE_CMSDK_APB_TIMER, 110 .index = 1, 111 .addr = 0x40001000, 112 .ppc = 0, 113 .ppc_port = 1, 114 .irq = 4, 115 }, 116 { 117 .name = "s32ktimer", 118 .type = TYPE_CMSDK_APB_TIMER, 119 .index = 2, 120 .addr = 0x4002f000, 121 .ppc = 1, 122 .ppc_port = 0, 123 .irq = 2, 124 .slowclk = true, 125 }, 126 { 127 .name = "dualtimer", 128 .type = TYPE_CMSDK_APB_DUALTIMER, 129 .index = 0, 130 .addr = 0x40002000, 131 .ppc = 0, 132 .ppc_port = 2, 133 .irq = 5, 134 }, 135 { 136 .name = "s32kwatchdog", 137 .type = TYPE_CMSDK_APB_WATCHDOG, 138 .index = 0, 139 .addr = 0x5002e000, 140 .ppc = NO_PPC, 141 .irq = NMI_0, 142 .slowclk = true, 143 }, 144 { 145 .name = "nswatchdog", 146 .type = TYPE_CMSDK_APB_WATCHDOG, 147 .index = 1, 148 .addr = 0x40081000, 149 .ppc = NO_PPC, 150 .irq = 1, 151 }, 152 { 153 .name = "swatchdog", 154 .type = TYPE_CMSDK_APB_WATCHDOG, 155 .index = 2, 156 .addr = 0x50081000, 157 .ppc = NO_PPC, 158 .irq = NMI_1, 159 }, 160 { 161 .name = "armsse-sysinfo", 162 .type = TYPE_IOTKIT_SYSINFO, 163 .index = 0, 164 .addr = 0x40020000, 165 .ppc = NO_PPC, 166 .irq = NO_IRQ, 167 }, 168 { 169 .name = NULL, 170 } 171 }; 172 173 static const ARMSSEInfo armsse_variants[] = { 174 { 175 .name = TYPE_IOTKIT, 176 .sse_version = ARMSSE_IOTKIT, 177 .sram_banks = 1, 178 .num_cpus = 1, 179 .sys_version = 0x41743, 180 .iidr = 0, 181 .cpuwait_rst = 0, 182 .has_mhus = false, 183 .has_ppus = false, 184 .has_cachectrl = false, 185 .has_cpusecctrl = false, 186 .has_cpuid = false, 187 .props = iotkit_properties, 188 .devinfo = sse200_devices, 189 }, 190 { 191 .name = TYPE_SSE200, 192 .sse_version = ARMSSE_SSE200, 193 .sram_banks = 4, 194 .num_cpus = 2, 195 .sys_version = 0x22041743, 196 .iidr = 0, 197 .cpuwait_rst = 2, 198 .has_mhus = true, 199 .has_ppus = true, 200 .has_cachectrl = true, 201 .has_cpusecctrl = true, 202 .has_cpuid = true, 203 .props = armsse_properties, 204 .devinfo = sse200_devices, 205 }, 206 }; 207 208 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) 209 { 210 /* Return the SYS_CONFIG value for this SSE */ 211 uint32_t sys_config; 212 213 switch (info->sse_version) { 214 case ARMSSE_IOTKIT: 215 sys_config = 0; 216 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 217 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); 218 break; 219 case ARMSSE_SSE200: 220 sys_config = 0; 221 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 222 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 223 sys_config = deposit32(sys_config, 24, 4, 2); 224 if (info->num_cpus > 1) { 225 sys_config = deposit32(sys_config, 10, 1, 1); 226 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1); 227 sys_config = deposit32(sys_config, 28, 4, 2); 228 } 229 break; 230 case ARMSSE_SSE300: 231 sys_config = 0; 232 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 233 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 234 sys_config = deposit32(sys_config, 16, 3, 3); /* CPU0 = Cortex-M55 */ 235 break; 236 default: 237 g_assert_not_reached(); 238 } 239 return sys_config; 240 } 241 242 /* Clock frequency in HZ of the 32KHz "slow clock" */ 243 #define S32KCLK (32 * 1000) 244 245 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ 246 static bool irq_is_common[32] = { 247 [0 ... 5] = true, 248 /* 6, 7: per-CPU MHU interrupts */ 249 [8 ... 12] = true, 250 /* 13: per-CPU icache interrupt */ 251 /* 14: reserved */ 252 [15 ... 20] = true, 253 /* 21: reserved */ 254 [22 ... 26] = true, 255 /* 27: reserved */ 256 /* 28, 29: per-CPU CTI interrupts */ 257 /* 30, 31: reserved */ 258 }; 259 260 /* 261 * Create an alias region in @container of @size bytes starting at @base 262 * which mirrors the memory starting at @orig. 263 */ 264 static void make_alias(ARMSSE *s, MemoryRegion *mr, MemoryRegion *container, 265 const char *name, hwaddr base, hwaddr size, hwaddr orig) 266 { 267 memory_region_init_alias(mr, NULL, name, container, orig, size); 268 /* The alias is even lower priority than unimplemented_device regions */ 269 memory_region_add_subregion_overlap(container, base, mr, -1500); 270 } 271 272 static void irq_status_forwarder(void *opaque, int n, int level) 273 { 274 qemu_irq destirq = opaque; 275 276 qemu_set_irq(destirq, level); 277 } 278 279 static void nsccfg_handler(void *opaque, int n, int level) 280 { 281 ARMSSE *s = ARM_SSE(opaque); 282 283 s->nsccfg = level; 284 } 285 286 static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) 287 { 288 /* Each of the 4 AHB and 4 APB PPCs that might be present in a 289 * system using the ARMSSE has a collection of control lines which 290 * are provided by the security controller and which we want to 291 * expose as control lines on the ARMSSE device itself, so the 292 * code using the ARMSSE can wire them up to the PPCs. 293 */ 294 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; 295 DeviceState *armssedev = DEVICE(s); 296 DeviceState *dev_secctl = DEVICE(&s->secctl); 297 DeviceState *dev_splitter = DEVICE(splitter); 298 char *name; 299 300 name = g_strdup_printf("%s_nonsec", ppcname); 301 qdev_pass_gpios(dev_secctl, armssedev, name); 302 g_free(name); 303 name = g_strdup_printf("%s_ap", ppcname); 304 qdev_pass_gpios(dev_secctl, armssedev, name); 305 g_free(name); 306 name = g_strdup_printf("%s_irq_enable", ppcname); 307 qdev_pass_gpios(dev_secctl, armssedev, name); 308 g_free(name); 309 name = g_strdup_printf("%s_irq_clear", ppcname); 310 qdev_pass_gpios(dev_secctl, armssedev, name); 311 g_free(name); 312 313 /* irq_status is a little more tricky, because we need to 314 * split it so we can send it both to the security controller 315 * and to our OR gate for the NVIC interrupt line. 316 * Connect up the splitter's outputs, and create a GPIO input 317 * which will pass the line state to the input splitter. 318 */ 319 name = g_strdup_printf("%s_irq_status", ppcname); 320 qdev_connect_gpio_out(dev_splitter, 0, 321 qdev_get_gpio_in_named(dev_secctl, 322 name, 0)); 323 qdev_connect_gpio_out(dev_splitter, 1, 324 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); 325 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); 326 qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder, 327 s->irq_status_in[ppcnum], name, 1); 328 g_free(name); 329 } 330 331 static void armsse_forward_sec_resp_cfg(ARMSSE *s) 332 { 333 /* Forward the 3rd output from the splitter device as a 334 * named GPIO output of the armsse object. 335 */ 336 DeviceState *dev = DEVICE(s); 337 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); 338 339 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); 340 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, 341 s->sec_resp_cfg, 1); 342 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); 343 } 344 345 static void armsse_mainclk_update(void *opaque, ClockEvent event) 346 { 347 ARMSSE *s = ARM_SSE(opaque); 348 349 /* 350 * Set system_clock_scale from our Clock input; this is what 351 * controls the tick rate of the CPU SysTick timer. 352 */ 353 system_clock_scale = clock_ticks_to_ns(s->mainclk, 1); 354 } 355 356 static void armsse_init(Object *obj) 357 { 358 ARMSSE *s = ARM_SSE(obj); 359 ARMSSEClass *asc = ARM_SSE_GET_CLASS(obj); 360 const ARMSSEInfo *info = asc->info; 361 const ARMSSEDeviceInfo *devinfo; 362 int i; 363 364 assert(info->sram_banks <= MAX_SRAM_BANKS); 365 assert(info->num_cpus <= SSE_MAX_CPUS); 366 367 s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", 368 armsse_mainclk_update, s, ClockUpdate); 369 s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0); 370 371 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); 372 373 for (i = 0; i < info->num_cpus; i++) { 374 /* 375 * We put each CPU in its own cluster as they are logically 376 * distinct and may be configured differently. 377 */ 378 char *name; 379 380 name = g_strdup_printf("cluster%d", i); 381 object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER); 382 qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); 383 g_free(name); 384 385 name = g_strdup_printf("armv7m%d", i); 386 object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i], 387 TYPE_ARMV7M); 388 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", 389 ARM_CPU_TYPE_NAME("cortex-m33")); 390 g_free(name); 391 name = g_strdup_printf("arm-sse-cpu-container%d", i); 392 memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); 393 g_free(name); 394 if (i > 0) { 395 name = g_strdup_printf("arm-sse-container-alias%d", i); 396 memory_region_init_alias(&s->container_alias[i - 1], obj, 397 name, &s->container, 0, UINT64_MAX); 398 g_free(name); 399 } 400 } 401 402 for (devinfo = info->devinfo; devinfo->name; devinfo++) { 403 assert(devinfo->ppc == NO_PPC || devinfo->ppc < ARRAY_SIZE(s->apb_ppc)); 404 if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) { 405 assert(devinfo->index < ARRAY_SIZE(s->timer)); 406 object_initialize_child(obj, devinfo->name, 407 &s->timer[devinfo->index], 408 TYPE_CMSDK_APB_TIMER); 409 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_DUALTIMER)) { 410 assert(devinfo->index == 0); 411 object_initialize_child(obj, devinfo->name, &s->dualtimer, 412 TYPE_CMSDK_APB_DUALTIMER); 413 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) { 414 assert(devinfo->index < ARRAY_SIZE(s->cmsdk_watchdog)); 415 object_initialize_child(obj, devinfo->name, 416 &s->cmsdk_watchdog[devinfo->index], 417 TYPE_CMSDK_APB_WATCHDOG); 418 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSINFO)) { 419 assert(devinfo->index == 0); 420 object_initialize_child(obj, devinfo->name, &s->sysinfo, 421 TYPE_IOTKIT_SYSINFO); 422 } else { 423 g_assert_not_reached(); 424 } 425 } 426 427 object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL); 428 429 for (i = 0; i < ARRAY_SIZE(s->apb_ppc); i++) { 430 g_autofree char *name = g_strdup_printf("apb-ppc%d", i); 431 object_initialize_child(obj, name, &s->apb_ppc[i], TYPE_TZ_PPC); 432 } 433 434 for (i = 0; i < info->sram_banks; i++) { 435 char *name = g_strdup_printf("mpc%d", i); 436 object_initialize_child(obj, name, &s->mpc[i], TYPE_TZ_MPC); 437 g_free(name); 438 } 439 object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate, 440 TYPE_OR_IRQ); 441 442 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 443 char *name = g_strdup_printf("mpc-irq-splitter-%d", i); 444 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 445 446 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 447 g_free(name); 448 } 449 450 object_initialize_child(obj, "armsse-sysctl", &s->sysctl, 451 TYPE_IOTKIT_SYSCTL); 452 if (info->has_mhus) { 453 object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); 454 object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); 455 } 456 if (info->has_ppus) { 457 for (i = 0; i < info->num_cpus; i++) { 458 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 459 int ppuidx = CPU0CORE_PPU + i; 460 461 object_initialize_child(obj, name, &s->ppu[ppuidx], 462 TYPE_UNIMPLEMENTED_DEVICE); 463 g_free(name); 464 } 465 object_initialize_child(obj, "DBG_PPU", &s->ppu[DBG_PPU], 466 TYPE_UNIMPLEMENTED_DEVICE); 467 for (i = 0; i < info->sram_banks; i++) { 468 char *name = g_strdup_printf("RAM%d_PPU", i); 469 int ppuidx = RAM0_PPU + i; 470 471 object_initialize_child(obj, name, &s->ppu[ppuidx], 472 TYPE_UNIMPLEMENTED_DEVICE); 473 g_free(name); 474 } 475 } 476 if (info->has_cachectrl) { 477 for (i = 0; i < info->num_cpus; i++) { 478 char *name = g_strdup_printf("cachectrl%d", i); 479 480 object_initialize_child(obj, name, &s->cachectrl[i], 481 TYPE_UNIMPLEMENTED_DEVICE); 482 g_free(name); 483 } 484 } 485 if (info->has_cpusecctrl) { 486 for (i = 0; i < info->num_cpus; i++) { 487 char *name = g_strdup_printf("cpusecctrl%d", i); 488 489 object_initialize_child(obj, name, &s->cpusecctrl[i], 490 TYPE_UNIMPLEMENTED_DEVICE); 491 g_free(name); 492 } 493 } 494 if (info->has_cpuid) { 495 for (i = 0; i < info->num_cpus; i++) { 496 char *name = g_strdup_printf("cpuid%d", i); 497 498 object_initialize_child(obj, name, &s->cpuid[i], 499 TYPE_ARMSSE_CPUID); 500 g_free(name); 501 } 502 } 503 object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ); 504 object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, 505 TYPE_OR_IRQ); 506 object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter, 507 TYPE_SPLIT_IRQ); 508 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 509 char *name = g_strdup_printf("ppc-irq-splitter-%d", i); 510 SplitIRQ *splitter = &s->ppc_irq_splitter[i]; 511 512 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 513 g_free(name); 514 } 515 if (info->num_cpus > 1) { 516 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 517 if (irq_is_common[i]) { 518 char *name = g_strdup_printf("cpu-irq-splitter%d", i); 519 SplitIRQ *splitter = &s->cpu_irq_splitter[i]; 520 521 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 522 g_free(name); 523 } 524 } 525 } 526 } 527 528 static void armsse_exp_irq(void *opaque, int n, int level) 529 { 530 qemu_irq *irqarray = opaque; 531 532 qemu_set_irq(irqarray[n], level); 533 } 534 535 static void armsse_mpcexp_status(void *opaque, int n, int level) 536 { 537 ARMSSE *s = ARM_SSE(opaque); 538 qemu_set_irq(s->mpcexp_status_in[n], level); 539 } 540 541 static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno) 542 { 543 /* 544 * Return a qemu_irq which can be used to signal IRQ n to 545 * all CPUs in the SSE. 546 */ 547 ARMSSEClass *asc = ARM_SSE_GET_CLASS(s); 548 const ARMSSEInfo *info = asc->info; 549 550 assert(irq_is_common[irqno]); 551 552 if (info->num_cpus == 1) { 553 /* Only one CPU -- just connect directly to it */ 554 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); 555 } else { 556 /* Connect to the splitter which feeds all CPUs */ 557 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); 558 } 559 } 560 561 static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) 562 { 563 /* Map a PPU unimplemented device stub */ 564 DeviceState *dev = DEVICE(&s->ppu[ppuidx]); 565 566 qdev_prop_set_string(dev, "name", name); 567 qdev_prop_set_uint64(dev, "size", 0x1000); 568 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 569 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); 570 } 571 572 static void armsse_realize(DeviceState *dev, Error **errp) 573 { 574 ARMSSE *s = ARM_SSE(dev); 575 ARMSSEClass *asc = ARM_SSE_GET_CLASS(dev); 576 const ARMSSEInfo *info = asc->info; 577 const ARMSSEDeviceInfo *devinfo; 578 int i; 579 MemoryRegion *mr; 580 Error *err = NULL; 581 SysBusDevice *sbd_apb_ppc0; 582 SysBusDevice *sbd_secctl; 583 DeviceState *dev_apb_ppc0; 584 DeviceState *dev_apb_ppc1; 585 DeviceState *dev_secctl; 586 DeviceState *dev_splitter; 587 uint32_t addr_width_max; 588 589 if (!s->board_memory) { 590 error_setg(errp, "memory property was not set"); 591 return; 592 } 593 594 if (!clock_has_source(s->mainclk)) { 595 error_setg(errp, "MAINCLK clock was not connected"); 596 } 597 if (!clock_has_source(s->s32kclk)) { 598 error_setg(errp, "S32KCLK clock was not connected"); 599 } 600 601 assert(info->num_cpus <= SSE_MAX_CPUS); 602 603 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ 604 assert(is_power_of_2(info->sram_banks)); 605 addr_width_max = 24 - ctz32(info->sram_banks); 606 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { 607 error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d", 608 addr_width_max); 609 return; 610 } 611 612 /* Handling of which devices should be available only to secure 613 * code is usually done differently for M profile than for A profile. 614 * Instead of putting some devices only into the secure address space, 615 * devices exist in both address spaces but with hard-wired security 616 * permissions that will cause the CPU to fault for non-secure accesses. 617 * 618 * The ARMSSE has an IDAU (Implementation Defined Access Unit), 619 * which specifies hard-wired security permissions for different 620 * areas of the physical address space. For the ARMSSE IDAU, the 621 * top 4 bits of the physical address are the IDAU region ID, and 622 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS 623 * region, otherwise it is an S region. 624 * 625 * The various devices and RAMs are generally all mapped twice, 626 * once into a region that the IDAU defines as secure and once 627 * into a non-secure region. They sit behind either a Memory 628 * Protection Controller (for RAM) or a Peripheral Protection 629 * Controller (for devices), which allow a more fine grained 630 * configuration of whether non-secure accesses are permitted. 631 * 632 * (The other place that guest software can configure security 633 * permissions is in the architected SAU (Security Attribution 634 * Unit), which is entirely inside the CPU. The IDAU can upgrade 635 * the security attributes for a region to more restrictive than 636 * the SAU specifies, but cannot downgrade them.) 637 * 638 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff 639 * 0x20000000..0x2007ffff 32KB FPGA block RAM 640 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff 641 * 0x40000000..0x4000ffff base peripheral region 1 642 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) 643 * 0x40020000..0x4002ffff system control element peripherals 644 * 0x40080000..0x400fffff base peripheral region 2 645 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff 646 */ 647 648 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); 649 650 for (i = 0; i < info->num_cpus; i++) { 651 DeviceState *cpudev = DEVICE(&s->armv7m[i]); 652 Object *cpuobj = OBJECT(&s->armv7m[i]); 653 int j; 654 char *gpioname; 655 656 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IRQS); 657 /* 658 * In real hardware the initial Secure VTOR is set from the INITSVTOR* 659 * registers in the IoT Kit System Control Register block. In QEMU 660 * we set the initial value here, and also the reset value of the 661 * sysctl register, from this object's QOM init-svtor property. 662 * If the guest changes the INITSVTOR* registers at runtime then the 663 * code in iotkit-sysctl.c will update the CPU init-svtor property 664 * (which will then take effect on the next CPU warm-reset). 665 * 666 * Note that typically a board using the SSE-200 will have a system 667 * control processor whose boot firmware initializes the INITSVTOR* 668 * registers before powering up the CPUs. QEMU doesn't emulate 669 * the control processor, so instead we behave in the way that the 670 * firmware does: the initial value should be set by the board code 671 * (using the init-svtor property on the ARMSSE object) to match 672 * whatever its firmware does. 673 */ 674 qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); 675 /* 676 * CPUs start powered down if the corresponding bit in the CPUWAIT 677 * register is 1. In real hardware the CPUWAIT register reset value is 678 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and 679 * CPUWAIT1_RST parameters), but since all the boards we care about 680 * start CPU0 and leave CPU1 powered off, we hard-code that in 681 * info->cpuwait_rst for now. We can add QOM properties for this 682 * later if necessary. 683 */ 684 if (extract32(info->cpuwait_rst, i, 1)) { 685 if (!object_property_set_bool(cpuobj, "start-powered-off", true, 686 errp)) { 687 return; 688 } 689 } 690 if (!s->cpu_fpu[i]) { 691 if (!object_property_set_bool(cpuobj, "vfp", false, errp)) { 692 return; 693 } 694 } 695 if (!s->cpu_dsp[i]) { 696 if (!object_property_set_bool(cpuobj, "dsp", false, errp)) { 697 return; 698 } 699 } 700 701 if (i > 0) { 702 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 703 &s->container_alias[i - 1], -1); 704 } else { 705 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 706 &s->container, -1); 707 } 708 object_property_set_link(cpuobj, "memory", 709 OBJECT(&s->cpu_container[i]), &error_abort); 710 object_property_set_link(cpuobj, "idau", OBJECT(s), &error_abort); 711 if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj), errp)) { 712 return; 713 } 714 /* 715 * The cluster must be realized after the armv7m container, as 716 * the container's CPU object is only created on realize, and the 717 * CPU must exist and have been parented into the cluster before 718 * the cluster is realized. 719 */ 720 if (!qdev_realize(DEVICE(&s->cluster[i]), NULL, errp)) { 721 return; 722 } 723 724 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ 725 s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); 726 for (j = 0; j < s->exp_numirq; j++) { 727 s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + NUM_SSE_IRQS); 728 } 729 if (i == 0) { 730 gpioname = g_strdup("EXP_IRQ"); 731 } else { 732 gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i); 733 } 734 qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq, 735 s->exp_irqs[i], 736 gpioname, s->exp_numirq); 737 g_free(gpioname); 738 } 739 740 /* Wire up the splitters that connect common IRQs to all CPUs */ 741 if (info->num_cpus > 1) { 742 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 743 if (irq_is_common[i]) { 744 Object *splitter = OBJECT(&s->cpu_irq_splitter[i]); 745 DeviceState *devs = DEVICE(splitter); 746 int cpunum; 747 748 if (!object_property_set_int(splitter, "num-lines", 749 info->num_cpus, errp)) { 750 return; 751 } 752 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 753 return; 754 } 755 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 756 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 757 758 qdev_connect_gpio_out(devs, cpunum, 759 qdev_get_gpio_in(cpudev, i)); 760 } 761 } 762 } 763 } 764 765 /* Set up the big aliases first */ 766 make_alias(s, &s->alias1, &s->container, "alias 1", 767 0x10000000, 0x10000000, 0x00000000); 768 make_alias(s, &s->alias2, &s->container, 769 "alias 2", 0x30000000, 0x10000000, 0x20000000); 770 /* The 0x50000000..0x5fffffff region is not a pure alias: it has 771 * a few extra devices that only appear there (generally the 772 * control interfaces for the protection controllers). 773 * We implement this by mapping those devices over the top of this 774 * alias MR at a higher priority. Some of the devices in this range 775 * are per-CPU, so we must put this alias in the per-cpu containers. 776 */ 777 for (i = 0; i < info->num_cpus; i++) { 778 make_alias(s, &s->alias3[i], &s->cpu_container[i], 779 "alias 3", 0x50000000, 0x10000000, 0x40000000); 780 } 781 782 /* Security controller */ 783 object_property_set_int(OBJECT(&s->secctl), "sse-version", 784 info->sse_version, &error_abort); 785 if (!sysbus_realize(SYS_BUS_DEVICE(&s->secctl), errp)) { 786 return; 787 } 788 sbd_secctl = SYS_BUS_DEVICE(&s->secctl); 789 dev_secctl = DEVICE(&s->secctl); 790 sysbus_mmio_map(sbd_secctl, 0, 0x50080000); 791 sysbus_mmio_map(sbd_secctl, 1, 0x40080000); 792 793 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); 794 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); 795 796 /* The sec_resp_cfg output from the security controller must be split into 797 * multiple lines, one for each of the PPCs within the ARMSSE and one 798 * that will be an output from the ARMSSE to the system. 799 */ 800 if (!object_property_set_int(OBJECT(&s->sec_resp_splitter), 801 "num-lines", 3, errp)) { 802 return; 803 } 804 if (!qdev_realize(DEVICE(&s->sec_resp_splitter), NULL, errp)) { 805 return; 806 } 807 dev_splitter = DEVICE(&s->sec_resp_splitter); 808 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, 809 qdev_get_gpio_in(dev_splitter, 0)); 810 811 /* Each SRAM bank lives behind its own Memory Protection Controller */ 812 for (i = 0; i < info->sram_banks; i++) { 813 char *ramname = g_strdup_printf("armsse.sram%d", i); 814 SysBusDevice *sbd_mpc; 815 uint32_t sram_bank_size = 1 << s->sram_addr_width; 816 817 memory_region_init_ram(&s->sram[i], NULL, ramname, 818 sram_bank_size, &err); 819 g_free(ramname); 820 if (err) { 821 error_propagate(errp, err); 822 return; 823 } 824 object_property_set_link(OBJECT(&s->mpc[i]), "downstream", 825 OBJECT(&s->sram[i]), &error_abort); 826 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mpc[i]), errp)) { 827 return; 828 } 829 /* Map the upstream end of the MPC into the right place... */ 830 sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); 831 memory_region_add_subregion(&s->container, 832 0x20000000 + i * sram_bank_size, 833 sysbus_mmio_get_region(sbd_mpc, 1)); 834 /* ...and its register interface */ 835 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, 836 sysbus_mmio_get_region(sbd_mpc, 0)); 837 } 838 839 /* We must OR together lines from the MPC splitters to go to the NVIC */ 840 if (!object_property_set_int(OBJECT(&s->mpc_irq_orgate), "num-lines", 841 IOTS_NUM_EXP_MPC + info->sram_banks, 842 errp)) { 843 return; 844 } 845 if (!qdev_realize(DEVICE(&s->mpc_irq_orgate), NULL, errp)) { 846 return; 847 } 848 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, 849 armsse_get_common_irq_in(s, 9)); 850 851 /* This OR gate wires together outputs from the secure watchdogs to NMI */ 852 if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2, 853 errp)) { 854 return; 855 } 856 if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) { 857 return; 858 } 859 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, 860 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); 861 862 /* Devices behind APB PPC0: 863 * 0x40000000: timer0 864 * 0x40001000: timer1 865 * 0x40002000: dual timer 866 * 0x40003000: MHU0 (SSE-200 only) 867 * 0x40004000: MHU1 (SSE-200 only) 868 * We must configure and realize each downstream device and connect 869 * it to the appropriate PPC port; then we can realize the PPC and 870 * map its upstream ends to the right place in the container. 871 */ 872 for (devinfo = info->devinfo; devinfo->name; devinfo++) { 873 SysBusDevice *sbd; 874 qemu_irq irq; 875 876 if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) { 877 sbd = SYS_BUS_DEVICE(&s->timer[devinfo->index]); 878 879 qdev_connect_clock_in(DEVICE(sbd), "pclk", 880 devinfo->slowclk ? s->s32kclk : s->mainclk); 881 if (!sysbus_realize(sbd, errp)) { 882 return; 883 } 884 mr = sysbus_mmio_get_region(sbd, 0); 885 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_DUALTIMER)) { 886 sbd = SYS_BUS_DEVICE(&s->dualtimer); 887 888 qdev_connect_clock_in(DEVICE(sbd), "TIMCLK", s->mainclk); 889 if (!sysbus_realize(sbd, errp)) { 890 return; 891 } 892 mr = sysbus_mmio_get_region(sbd, 0); 893 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) { 894 sbd = SYS_BUS_DEVICE(&s->cmsdk_watchdog[devinfo->index]); 895 896 qdev_connect_clock_in(DEVICE(sbd), "WDOGCLK", 897 devinfo->slowclk ? s->s32kclk : s->mainclk); 898 if (!sysbus_realize(sbd, errp)) { 899 return; 900 } 901 mr = sysbus_mmio_get_region(sbd, 0); 902 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSINFO)) { 903 sbd = SYS_BUS_DEVICE(&s->sysinfo); 904 905 object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION", 906 info->sys_version, &error_abort); 907 object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG", 908 armsse_sys_config_value(s, info), 909 &error_abort); 910 object_property_set_int(OBJECT(&s->sysinfo), "sse-version", 911 info->sse_version, &error_abort); 912 object_property_set_int(OBJECT(&s->sysinfo), "IIDR", 913 info->iidr, &error_abort); 914 if (!sysbus_realize(sbd, errp)) { 915 return; 916 } 917 mr = sysbus_mmio_get_region(sbd, 0); 918 } else { 919 g_assert_not_reached(); 920 } 921 922 switch (devinfo->irq) { 923 case NO_IRQ: 924 irq = NULL; 925 break; 926 case 0 ... NUM_SSE_IRQS - 1: 927 irq = armsse_get_common_irq_in(s, devinfo->irq); 928 break; 929 case NMI_0: 930 case NMI_1: 931 irq = qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 932 devinfo->irq - NMI_0); 933 break; 934 default: 935 g_assert_not_reached(); 936 } 937 938 if (irq) { 939 sysbus_connect_irq(sbd, 0, irq); 940 } 941 942 /* 943 * Devices connected to a PPC are connected to the port here; 944 * we will map the upstream end of that port to the right address 945 * in the container later after the PPC has been realized. 946 * Devices not connected to a PPC can be mapped immediately. 947 */ 948 if (devinfo->ppc != NO_PPC) { 949 TZPPC *ppc = &s->apb_ppc[devinfo->ppc]; 950 g_autofree char *portname = g_strdup_printf("port[%d]", 951 devinfo->ppc_port); 952 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), 953 &error_abort); 954 } else { 955 memory_region_add_subregion(&s->container, devinfo->addr, mr); 956 } 957 } 958 959 if (info->has_mhus) { 960 /* 961 * An SSE-200 with only one CPU should have only one MHU created, 962 * with the region where the second MHU usually is being RAZ/WI. 963 * We don't implement that SSE-200 config; if we want to support 964 * it then this code needs to be enhanced to handle creating the 965 * RAZ/WI region instead of the second MHU. 966 */ 967 assert(info->num_cpus == ARRAY_SIZE(s->mhu)); 968 969 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { 970 char *port; 971 int cpunum; 972 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]); 973 974 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mhu[i]), errp)) { 975 return; 976 } 977 port = g_strdup_printf("port[%d]", i + 3); 978 mr = sysbus_mmio_get_region(mhu_sbd, 0); 979 object_property_set_link(OBJECT(&s->apb_ppc[0]), port, OBJECT(mr), 980 &error_abort); 981 g_free(port); 982 983 /* 984 * Each MHU has an irq line for each CPU: 985 * MHU 0 irq line 0 -> CPU 0 IRQ 6 986 * MHU 0 irq line 1 -> CPU 1 IRQ 6 987 * MHU 1 irq line 0 -> CPU 0 IRQ 7 988 * MHU 1 irq line 1 -> CPU 1 IRQ 7 989 */ 990 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 991 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 992 993 sysbus_connect_irq(mhu_sbd, cpunum, 994 qdev_get_gpio_in(cpudev, 6 + i)); 995 } 996 } 997 } 998 999 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[0]), errp)) { 1000 return; 1001 } 1002 1003 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc[0]); 1004 dev_apb_ppc0 = DEVICE(&s->apb_ppc[0]); 1005 1006 if (info->has_mhus) { 1007 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3); 1008 memory_region_add_subregion(&s->container, 0x40003000, mr); 1009 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4); 1010 memory_region_add_subregion(&s->container, 0x40004000, mr); 1011 } 1012 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { 1013 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, 1014 qdev_get_gpio_in_named(dev_apb_ppc0, 1015 "cfg_nonsec", i)); 1016 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, 1017 qdev_get_gpio_in_named(dev_apb_ppc0, 1018 "cfg_ap", i)); 1019 } 1020 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, 1021 qdev_get_gpio_in_named(dev_apb_ppc0, 1022 "irq_enable", 0)); 1023 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, 1024 qdev_get_gpio_in_named(dev_apb_ppc0, 1025 "irq_clear", 0)); 1026 qdev_connect_gpio_out(dev_splitter, 0, 1027 qdev_get_gpio_in_named(dev_apb_ppc0, 1028 "cfg_sec_resp", 0)); 1029 1030 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external 1031 * ones) are sent individually to the security controller, and also 1032 * ORed together to give a single combined PPC interrupt to the NVIC. 1033 */ 1034 if (!object_property_set_int(OBJECT(&s->ppc_irq_orgate), 1035 "num-lines", NUM_PPCS, errp)) { 1036 return; 1037 } 1038 if (!qdev_realize(DEVICE(&s->ppc_irq_orgate), NULL, errp)) { 1039 return; 1040 } 1041 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, 1042 armsse_get_common_irq_in(s, 10)); 1043 1044 /* 1045 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): 1046 * private per-CPU region (all these devices are SSE-200 only): 1047 * 0x50010000: L1 icache control registers 1048 * 0x50011000: CPUSECCTRL (CPU local security control registers) 1049 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block 1050 */ 1051 if (info->has_cachectrl) { 1052 for (i = 0; i < info->num_cpus; i++) { 1053 char *name = g_strdup_printf("cachectrl%d", i); 1054 MemoryRegion *mr; 1055 1056 qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); 1057 g_free(name); 1058 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); 1059 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cachectrl[i]), errp)) { 1060 return; 1061 } 1062 1063 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); 1064 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); 1065 } 1066 } 1067 if (info->has_cpusecctrl) { 1068 for (i = 0; i < info->num_cpus; i++) { 1069 char *name = g_strdup_printf("CPUSECCTRL%d", i); 1070 MemoryRegion *mr; 1071 1072 qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); 1073 g_free(name); 1074 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); 1075 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpusecctrl[i]), errp)) { 1076 return; 1077 } 1078 1079 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); 1080 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); 1081 } 1082 } 1083 if (info->has_cpuid) { 1084 for (i = 0; i < info->num_cpus; i++) { 1085 MemoryRegion *mr; 1086 1087 qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); 1088 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpuid[i]), errp)) { 1089 return; 1090 } 1091 1092 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); 1093 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); 1094 } 1095 } 1096 1097 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[1]), errp)) { 1098 return; 1099 } 1100 1101 dev_apb_ppc1 = DEVICE(&s->apb_ppc[1]); 1102 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, 1103 qdev_get_gpio_in_named(dev_apb_ppc1, 1104 "cfg_nonsec", 0)); 1105 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, 1106 qdev_get_gpio_in_named(dev_apb_ppc1, 1107 "cfg_ap", 0)); 1108 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, 1109 qdev_get_gpio_in_named(dev_apb_ppc1, 1110 "irq_enable", 0)); 1111 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, 1112 qdev_get_gpio_in_named(dev_apb_ppc1, 1113 "irq_clear", 0)); 1114 qdev_connect_gpio_out(dev_splitter, 1, 1115 qdev_get_gpio_in_named(dev_apb_ppc1, 1116 "cfg_sec_resp", 0)); 1117 1118 /* 1119 * Now both PPCs are realized we can map the upstream ends of 1120 * ports which correspond to entries in the devinfo array. 1121 * The ports which are connected to non-devinfo devices have 1122 * already been mapped. 1123 */ 1124 for (devinfo = info->devinfo; devinfo->name; devinfo++) { 1125 SysBusDevice *ppc_sbd; 1126 1127 if (devinfo->ppc == NO_PPC) { 1128 continue; 1129 } 1130 ppc_sbd = SYS_BUS_DEVICE(&s->apb_ppc[devinfo->ppc]); 1131 mr = sysbus_mmio_get_region(ppc_sbd, devinfo->ppc_port); 1132 memory_region_add_subregion(&s->container, devinfo->addr, mr); 1133 } 1134 1135 /* System control registers */ 1136 object_property_set_int(OBJECT(&s->sysctl), "sse-version", 1137 info->sse_version, &error_abort); 1138 object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST", 1139 info->cpuwait_rst, &error_abort); 1140 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST", 1141 s->init_svtor, &error_abort); 1142 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST", 1143 s->init_svtor, &error_abort); 1144 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysctl), errp)) { 1145 return; 1146 } 1147 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); 1148 1149 if (info->has_ppus) { 1150 /* CPUnCORE_PPU for each CPU */ 1151 for (i = 0; i < info->num_cpus; i++) { 1152 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 1153 1154 map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); 1155 /* 1156 * We don't support CPU debug so don't create the 1157 * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. 1158 */ 1159 g_free(name); 1160 } 1161 map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); 1162 1163 for (i = 0; i < info->sram_banks; i++) { 1164 char *name = g_strdup_printf("RAM%d_PPU", i); 1165 1166 map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); 1167 g_free(name); 1168 } 1169 } 1170 1171 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 1172 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); 1173 1174 if (!object_property_set_int(splitter, "num-lines", 2, errp)) { 1175 return; 1176 } 1177 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1178 return; 1179 } 1180 } 1181 1182 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { 1183 char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); 1184 1185 armsse_forward_ppc(s, ppcname, i); 1186 g_free(ppcname); 1187 } 1188 1189 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { 1190 char *ppcname = g_strdup_printf("apb_ppcexp%d", i); 1191 1192 armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); 1193 g_free(ppcname); 1194 } 1195 1196 for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { 1197 /* Wire up IRQ splitter for internal PPCs */ 1198 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); 1199 char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", 1200 i - NUM_EXTERNAL_PPCS); 1201 TZPPC *ppc = &s->apb_ppc[i - NUM_EXTERNAL_PPCS]; 1202 1203 qdev_connect_gpio_out(devs, 0, 1204 qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); 1205 qdev_connect_gpio_out(devs, 1, 1206 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); 1207 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, 1208 qdev_get_gpio_in(devs, 0)); 1209 g_free(gpioname); 1210 } 1211 1212 /* Wire up the splitters for the MPC IRQs */ 1213 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 1214 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 1215 DeviceState *dev_splitter = DEVICE(splitter); 1216 1217 if (!object_property_set_int(OBJECT(splitter), "num-lines", 2, 1218 errp)) { 1219 return; 1220 } 1221 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1222 return; 1223 } 1224 1225 if (i < IOTS_NUM_EXP_MPC) { 1226 /* Splitter input is from GPIO input line */ 1227 s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0); 1228 qdev_connect_gpio_out(dev_splitter, 0, 1229 qdev_get_gpio_in_named(dev_secctl, 1230 "mpcexp_status", i)); 1231 } else { 1232 /* Splitter input is from our own MPC */ 1233 qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]), 1234 "irq", 0, 1235 qdev_get_gpio_in(dev_splitter, 0)); 1236 qdev_connect_gpio_out(dev_splitter, 0, 1237 qdev_get_gpio_in_named(dev_secctl, 1238 "mpc_status", 1239 i - IOTS_NUM_EXP_MPC)); 1240 } 1241 1242 qdev_connect_gpio_out(dev_splitter, 1, 1243 qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i)); 1244 } 1245 /* Create GPIO inputs which will pass the line state for our 1246 * mpcexp_irq inputs to the correct splitter devices. 1247 */ 1248 qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status", 1249 IOTS_NUM_EXP_MPC); 1250 1251 armsse_forward_sec_resp_cfg(s); 1252 1253 /* Forward the MSC related signals */ 1254 qdev_pass_gpios(dev_secctl, dev, "mscexp_status"); 1255 qdev_pass_gpios(dev_secctl, dev, "mscexp_clear"); 1256 qdev_pass_gpios(dev_secctl, dev, "mscexp_ns"); 1257 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, 1258 armsse_get_common_irq_in(s, 11)); 1259 1260 /* 1261 * Expose our container region to the board model; this corresponds 1262 * to the AHB Slave Expansion ports which allow bus master devices 1263 * (eg DMA controllers) in the board model to make transactions into 1264 * devices in the ARMSSE. 1265 */ 1266 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); 1267 1268 /* Set initial system_clock_scale from MAINCLK */ 1269 armsse_mainclk_update(s, ClockUpdate); 1270 } 1271 1272 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, 1273 int *iregion, bool *exempt, bool *ns, bool *nsc) 1274 { 1275 /* 1276 * For ARMSSE systems the IDAU responses are simple logical functions 1277 * of the address bits. The NSC attribute is guest-adjustable via the 1278 * NSCCFG register in the security controller. 1279 */ 1280 ARMSSE *s = ARM_SSE(ii); 1281 int region = extract32(address, 28, 4); 1282 1283 *ns = !(region & 1); 1284 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); 1285 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1286 *exempt = (address & 0xeff00000) == 0xe0000000; 1287 *iregion = region; 1288 } 1289 1290 static const VMStateDescription armsse_vmstate = { 1291 .name = "iotkit", 1292 .version_id = 2, 1293 .minimum_version_id = 2, 1294 .fields = (VMStateField[]) { 1295 VMSTATE_CLOCK(mainclk, ARMSSE), 1296 VMSTATE_CLOCK(s32kclk, ARMSSE), 1297 VMSTATE_UINT32(nsccfg, ARMSSE), 1298 VMSTATE_END_OF_LIST() 1299 } 1300 }; 1301 1302 static void armsse_reset(DeviceState *dev) 1303 { 1304 ARMSSE *s = ARM_SSE(dev); 1305 1306 s->nsccfg = 0; 1307 } 1308 1309 static void armsse_class_init(ObjectClass *klass, void *data) 1310 { 1311 DeviceClass *dc = DEVICE_CLASS(klass); 1312 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); 1313 ARMSSEClass *asc = ARM_SSE_CLASS(klass); 1314 const ARMSSEInfo *info = data; 1315 1316 dc->realize = armsse_realize; 1317 dc->vmsd = &armsse_vmstate; 1318 device_class_set_props(dc, info->props); 1319 dc->reset = armsse_reset; 1320 iic->check = armsse_idau_check; 1321 asc->info = info; 1322 } 1323 1324 static const TypeInfo armsse_info = { 1325 .name = TYPE_ARM_SSE, 1326 .parent = TYPE_SYS_BUS_DEVICE, 1327 .instance_size = sizeof(ARMSSE), 1328 .class_size = sizeof(ARMSSEClass), 1329 .instance_init = armsse_init, 1330 .abstract = true, 1331 .interfaces = (InterfaceInfo[]) { 1332 { TYPE_IDAU_INTERFACE }, 1333 { } 1334 } 1335 }; 1336 1337 static void armsse_register_types(void) 1338 { 1339 int i; 1340 1341 type_register_static(&armsse_info); 1342 1343 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) { 1344 TypeInfo ti = { 1345 .name = armsse_variants[i].name, 1346 .parent = TYPE_ARM_SSE, 1347 .class_init = armsse_class_init, 1348 .class_data = (void *)&armsse_variants[i], 1349 }; 1350 type_register(&ti); 1351 } 1352 } 1353 1354 type_init(armsse_register_types); 1355