1 /* 2 * Arm SSE (Subsystems for Embedded): IoTKit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qemu/bitops.h" 16 #include "qapi/error.h" 17 #include "trace.h" 18 #include "hw/sysbus.h" 19 #include "migration/vmstate.h" 20 #include "hw/registerfields.h" 21 #include "hw/arm/armsse.h" 22 #include "hw/arm/armsse-version.h" 23 #include "hw/arm/boot.h" 24 #include "hw/irq.h" 25 #include "hw/qdev-clock.h" 26 27 /* 28 * The SSE-300 puts some devices in different places to the 29 * SSE-200 (and original IoTKit). We use an array of these structs 30 * to define how each variant lays out these devices. (Parts of the 31 * SoC that are the same for all variants aren't handled via these 32 * data structures.) 33 */ 34 35 #define NO_IRQ -1 36 #define NO_PPC -1 37 /* 38 * Special values for ARMSSEDeviceInfo::irq to indicate that this 39 * device uses one of the inputs to the OR gate that feeds into the 40 * CPU NMI input. 41 */ 42 #define NMI_0 10000 43 #define NMI_1 10001 44 45 typedef struct ARMSSEDeviceInfo { 46 const char *name; /* name to use for the QOM object; NULL terminates list */ 47 const char *type; /* QOM type name */ 48 unsigned int index; /* Which of the N devices of this type is this ? */ 49 hwaddr addr; 50 int ppc; /* Index of APB PPC this device is wired up to, or NO_PPC */ 51 int ppc_port; /* Port number of this device on the PPC */ 52 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */ 53 bool slowclk; /* true if device uses the slow 32KHz clock */ 54 } ARMSSEDeviceInfo; 55 56 struct ARMSSEInfo { 57 const char *name; 58 uint32_t sse_version; 59 int sram_banks; 60 int num_cpus; 61 uint32_t sys_version; 62 uint32_t iidr; 63 uint32_t cpuwait_rst; 64 bool has_mhus; 65 bool has_ppus; 66 bool has_cachectrl; 67 bool has_cpusecctrl; 68 bool has_cpuid; 69 Property *props; 70 const ARMSSEDeviceInfo *devinfo; 71 }; 72 73 static Property iotkit_properties[] = { 74 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 75 MemoryRegion *), 76 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 77 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 78 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 79 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), 80 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), 81 DEFINE_PROP_END_OF_LIST() 82 }; 83 84 static Property armsse_properties[] = { 85 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 86 MemoryRegion *), 87 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 88 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 89 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 90 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), 91 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), 92 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), 93 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), 94 DEFINE_PROP_END_OF_LIST() 95 }; 96 97 static const ARMSSEDeviceInfo sse200_devices[] = { 98 { 99 .name = "timer0", 100 .type = TYPE_CMSDK_APB_TIMER, 101 .index = 0, 102 .addr = 0x40000000, 103 .ppc = 0, 104 .ppc_port = 0, 105 .irq = 3, 106 }, 107 { 108 .name = "timer1", 109 .type = TYPE_CMSDK_APB_TIMER, 110 .index = 1, 111 .addr = 0x40001000, 112 .ppc = 0, 113 .ppc_port = 1, 114 .irq = 4, 115 }, 116 { 117 .name = "dualtimer", 118 .type = TYPE_CMSDK_APB_DUALTIMER, 119 .index = 0, 120 .addr = 0x40002000, 121 .ppc = 0, 122 .ppc_port = 2, 123 .irq = 5, 124 }, 125 { 126 .name = "s32kwatchdog", 127 .type = TYPE_CMSDK_APB_WATCHDOG, 128 .index = 0, 129 .addr = 0x5002e000, 130 .ppc = NO_PPC, 131 .irq = NMI_0, 132 .slowclk = true, 133 }, 134 { 135 .name = "nswatchdog", 136 .type = TYPE_CMSDK_APB_WATCHDOG, 137 .index = 1, 138 .addr = 0x40081000, 139 .ppc = NO_PPC, 140 .irq = 1, 141 }, 142 { 143 .name = "swatchdog", 144 .type = TYPE_CMSDK_APB_WATCHDOG, 145 .index = 2, 146 .addr = 0x50081000, 147 .ppc = NO_PPC, 148 .irq = NMI_1, 149 }, 150 { 151 .name = NULL, 152 } 153 }; 154 155 static const ARMSSEInfo armsse_variants[] = { 156 { 157 .name = TYPE_IOTKIT, 158 .sse_version = ARMSSE_IOTKIT, 159 .sram_banks = 1, 160 .num_cpus = 1, 161 .sys_version = 0x41743, 162 .iidr = 0, 163 .cpuwait_rst = 0, 164 .has_mhus = false, 165 .has_ppus = false, 166 .has_cachectrl = false, 167 .has_cpusecctrl = false, 168 .has_cpuid = false, 169 .props = iotkit_properties, 170 .devinfo = sse200_devices, 171 }, 172 { 173 .name = TYPE_SSE200, 174 .sse_version = ARMSSE_SSE200, 175 .sram_banks = 4, 176 .num_cpus = 2, 177 .sys_version = 0x22041743, 178 .iidr = 0, 179 .cpuwait_rst = 2, 180 .has_mhus = true, 181 .has_ppus = true, 182 .has_cachectrl = true, 183 .has_cpusecctrl = true, 184 .has_cpuid = true, 185 .props = armsse_properties, 186 .devinfo = sse200_devices, 187 }, 188 }; 189 190 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) 191 { 192 /* Return the SYS_CONFIG value for this SSE */ 193 uint32_t sys_config; 194 195 switch (info->sse_version) { 196 case ARMSSE_IOTKIT: 197 sys_config = 0; 198 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 199 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); 200 break; 201 case ARMSSE_SSE200: 202 sys_config = 0; 203 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 204 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 205 sys_config = deposit32(sys_config, 24, 4, 2); 206 if (info->num_cpus > 1) { 207 sys_config = deposit32(sys_config, 10, 1, 1); 208 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1); 209 sys_config = deposit32(sys_config, 28, 4, 2); 210 } 211 break; 212 case ARMSSE_SSE300: 213 sys_config = 0; 214 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 215 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 216 sys_config = deposit32(sys_config, 16, 3, 3); /* CPU0 = Cortex-M55 */ 217 break; 218 default: 219 g_assert_not_reached(); 220 } 221 return sys_config; 222 } 223 224 /* Clock frequency in HZ of the 32KHz "slow clock" */ 225 #define S32KCLK (32 * 1000) 226 227 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ 228 static bool irq_is_common[32] = { 229 [0 ... 5] = true, 230 /* 6, 7: per-CPU MHU interrupts */ 231 [8 ... 12] = true, 232 /* 13: per-CPU icache interrupt */ 233 /* 14: reserved */ 234 [15 ... 20] = true, 235 /* 21: reserved */ 236 [22 ... 26] = true, 237 /* 27: reserved */ 238 /* 28, 29: per-CPU CTI interrupts */ 239 /* 30, 31: reserved */ 240 }; 241 242 /* 243 * Create an alias region in @container of @size bytes starting at @base 244 * which mirrors the memory starting at @orig. 245 */ 246 static void make_alias(ARMSSE *s, MemoryRegion *mr, MemoryRegion *container, 247 const char *name, hwaddr base, hwaddr size, hwaddr orig) 248 { 249 memory_region_init_alias(mr, NULL, name, container, orig, size); 250 /* The alias is even lower priority than unimplemented_device regions */ 251 memory_region_add_subregion_overlap(container, base, mr, -1500); 252 } 253 254 static void irq_status_forwarder(void *opaque, int n, int level) 255 { 256 qemu_irq destirq = opaque; 257 258 qemu_set_irq(destirq, level); 259 } 260 261 static void nsccfg_handler(void *opaque, int n, int level) 262 { 263 ARMSSE *s = ARM_SSE(opaque); 264 265 s->nsccfg = level; 266 } 267 268 static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) 269 { 270 /* Each of the 4 AHB and 4 APB PPCs that might be present in a 271 * system using the ARMSSE has a collection of control lines which 272 * are provided by the security controller and which we want to 273 * expose as control lines on the ARMSSE device itself, so the 274 * code using the ARMSSE can wire them up to the PPCs. 275 */ 276 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; 277 DeviceState *armssedev = DEVICE(s); 278 DeviceState *dev_secctl = DEVICE(&s->secctl); 279 DeviceState *dev_splitter = DEVICE(splitter); 280 char *name; 281 282 name = g_strdup_printf("%s_nonsec", ppcname); 283 qdev_pass_gpios(dev_secctl, armssedev, name); 284 g_free(name); 285 name = g_strdup_printf("%s_ap", ppcname); 286 qdev_pass_gpios(dev_secctl, armssedev, name); 287 g_free(name); 288 name = g_strdup_printf("%s_irq_enable", ppcname); 289 qdev_pass_gpios(dev_secctl, armssedev, name); 290 g_free(name); 291 name = g_strdup_printf("%s_irq_clear", ppcname); 292 qdev_pass_gpios(dev_secctl, armssedev, name); 293 g_free(name); 294 295 /* irq_status is a little more tricky, because we need to 296 * split it so we can send it both to the security controller 297 * and to our OR gate for the NVIC interrupt line. 298 * Connect up the splitter's outputs, and create a GPIO input 299 * which will pass the line state to the input splitter. 300 */ 301 name = g_strdup_printf("%s_irq_status", ppcname); 302 qdev_connect_gpio_out(dev_splitter, 0, 303 qdev_get_gpio_in_named(dev_secctl, 304 name, 0)); 305 qdev_connect_gpio_out(dev_splitter, 1, 306 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); 307 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); 308 qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder, 309 s->irq_status_in[ppcnum], name, 1); 310 g_free(name); 311 } 312 313 static void armsse_forward_sec_resp_cfg(ARMSSE *s) 314 { 315 /* Forward the 3rd output from the splitter device as a 316 * named GPIO output of the armsse object. 317 */ 318 DeviceState *dev = DEVICE(s); 319 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); 320 321 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); 322 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, 323 s->sec_resp_cfg, 1); 324 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); 325 } 326 327 static void armsse_mainclk_update(void *opaque, ClockEvent event) 328 { 329 ARMSSE *s = ARM_SSE(opaque); 330 331 /* 332 * Set system_clock_scale from our Clock input; this is what 333 * controls the tick rate of the CPU SysTick timer. 334 */ 335 system_clock_scale = clock_ticks_to_ns(s->mainclk, 1); 336 } 337 338 static void armsse_init(Object *obj) 339 { 340 ARMSSE *s = ARM_SSE(obj); 341 ARMSSEClass *asc = ARM_SSE_GET_CLASS(obj); 342 const ARMSSEInfo *info = asc->info; 343 const ARMSSEDeviceInfo *devinfo; 344 int i; 345 346 assert(info->sram_banks <= MAX_SRAM_BANKS); 347 assert(info->num_cpus <= SSE_MAX_CPUS); 348 349 s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", 350 armsse_mainclk_update, s, ClockUpdate); 351 s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0); 352 353 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); 354 355 for (i = 0; i < info->num_cpus; i++) { 356 /* 357 * We put each CPU in its own cluster as they are logically 358 * distinct and may be configured differently. 359 */ 360 char *name; 361 362 name = g_strdup_printf("cluster%d", i); 363 object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER); 364 qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); 365 g_free(name); 366 367 name = g_strdup_printf("armv7m%d", i); 368 object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i], 369 TYPE_ARMV7M); 370 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", 371 ARM_CPU_TYPE_NAME("cortex-m33")); 372 g_free(name); 373 name = g_strdup_printf("arm-sse-cpu-container%d", i); 374 memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); 375 g_free(name); 376 if (i > 0) { 377 name = g_strdup_printf("arm-sse-container-alias%d", i); 378 memory_region_init_alias(&s->container_alias[i - 1], obj, 379 name, &s->container, 0, UINT64_MAX); 380 g_free(name); 381 } 382 } 383 384 for (devinfo = info->devinfo; devinfo->name; devinfo++) { 385 assert(devinfo->ppc == NO_PPC || devinfo->ppc < ARRAY_SIZE(s->apb_ppc)); 386 if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) { 387 assert(devinfo->index < ARRAY_SIZE(s->timer)); 388 object_initialize_child(obj, devinfo->name, 389 &s->timer[devinfo->index], 390 TYPE_CMSDK_APB_TIMER); 391 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_DUALTIMER)) { 392 assert(devinfo->index == 0); 393 object_initialize_child(obj, devinfo->name, &s->dualtimer, 394 TYPE_CMSDK_APB_DUALTIMER); 395 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) { 396 assert(devinfo->index < ARRAY_SIZE(s->cmsdk_watchdog)); 397 object_initialize_child(obj, devinfo->name, 398 &s->cmsdk_watchdog[devinfo->index], 399 TYPE_CMSDK_APB_WATCHDOG); 400 } else { 401 g_assert_not_reached(); 402 } 403 } 404 405 object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL); 406 407 for (i = 0; i < ARRAY_SIZE(s->apb_ppc); i++) { 408 g_autofree char *name = g_strdup_printf("apb-ppc%d", i); 409 object_initialize_child(obj, name, &s->apb_ppc[i], TYPE_TZ_PPC); 410 } 411 412 for (i = 0; i < info->sram_banks; i++) { 413 char *name = g_strdup_printf("mpc%d", i); 414 object_initialize_child(obj, name, &s->mpc[i], TYPE_TZ_MPC); 415 g_free(name); 416 } 417 object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate, 418 TYPE_OR_IRQ); 419 420 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 421 char *name = g_strdup_printf("mpc-irq-splitter-%d", i); 422 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 423 424 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 425 g_free(name); 426 } 427 428 object_initialize_child(obj, "s32ktimer", &s->s32ktimer, 429 TYPE_CMSDK_APB_TIMER); 430 object_initialize_child(obj, "armsse-sysctl", &s->sysctl, 431 TYPE_IOTKIT_SYSCTL); 432 object_initialize_child(obj, "armsse-sysinfo", &s->sysinfo, 433 TYPE_IOTKIT_SYSINFO); 434 if (info->has_mhus) { 435 object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); 436 object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); 437 } 438 if (info->has_ppus) { 439 for (i = 0; i < info->num_cpus; i++) { 440 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 441 int ppuidx = CPU0CORE_PPU + i; 442 443 object_initialize_child(obj, name, &s->ppu[ppuidx], 444 TYPE_UNIMPLEMENTED_DEVICE); 445 g_free(name); 446 } 447 object_initialize_child(obj, "DBG_PPU", &s->ppu[DBG_PPU], 448 TYPE_UNIMPLEMENTED_DEVICE); 449 for (i = 0; i < info->sram_banks; i++) { 450 char *name = g_strdup_printf("RAM%d_PPU", i); 451 int ppuidx = RAM0_PPU + i; 452 453 object_initialize_child(obj, name, &s->ppu[ppuidx], 454 TYPE_UNIMPLEMENTED_DEVICE); 455 g_free(name); 456 } 457 } 458 if (info->has_cachectrl) { 459 for (i = 0; i < info->num_cpus; i++) { 460 char *name = g_strdup_printf("cachectrl%d", i); 461 462 object_initialize_child(obj, name, &s->cachectrl[i], 463 TYPE_UNIMPLEMENTED_DEVICE); 464 g_free(name); 465 } 466 } 467 if (info->has_cpusecctrl) { 468 for (i = 0; i < info->num_cpus; i++) { 469 char *name = g_strdup_printf("cpusecctrl%d", i); 470 471 object_initialize_child(obj, name, &s->cpusecctrl[i], 472 TYPE_UNIMPLEMENTED_DEVICE); 473 g_free(name); 474 } 475 } 476 if (info->has_cpuid) { 477 for (i = 0; i < info->num_cpus; i++) { 478 char *name = g_strdup_printf("cpuid%d", i); 479 480 object_initialize_child(obj, name, &s->cpuid[i], 481 TYPE_ARMSSE_CPUID); 482 g_free(name); 483 } 484 } 485 object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ); 486 object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, 487 TYPE_OR_IRQ); 488 object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter, 489 TYPE_SPLIT_IRQ); 490 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 491 char *name = g_strdup_printf("ppc-irq-splitter-%d", i); 492 SplitIRQ *splitter = &s->ppc_irq_splitter[i]; 493 494 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 495 g_free(name); 496 } 497 if (info->num_cpus > 1) { 498 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 499 if (irq_is_common[i]) { 500 char *name = g_strdup_printf("cpu-irq-splitter%d", i); 501 SplitIRQ *splitter = &s->cpu_irq_splitter[i]; 502 503 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 504 g_free(name); 505 } 506 } 507 } 508 } 509 510 static void armsse_exp_irq(void *opaque, int n, int level) 511 { 512 qemu_irq *irqarray = opaque; 513 514 qemu_set_irq(irqarray[n], level); 515 } 516 517 static void armsse_mpcexp_status(void *opaque, int n, int level) 518 { 519 ARMSSE *s = ARM_SSE(opaque); 520 qemu_set_irq(s->mpcexp_status_in[n], level); 521 } 522 523 static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno) 524 { 525 /* 526 * Return a qemu_irq which can be used to signal IRQ n to 527 * all CPUs in the SSE. 528 */ 529 ARMSSEClass *asc = ARM_SSE_GET_CLASS(s); 530 const ARMSSEInfo *info = asc->info; 531 532 assert(irq_is_common[irqno]); 533 534 if (info->num_cpus == 1) { 535 /* Only one CPU -- just connect directly to it */ 536 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); 537 } else { 538 /* Connect to the splitter which feeds all CPUs */ 539 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); 540 } 541 } 542 543 static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) 544 { 545 /* Map a PPU unimplemented device stub */ 546 DeviceState *dev = DEVICE(&s->ppu[ppuidx]); 547 548 qdev_prop_set_string(dev, "name", name); 549 qdev_prop_set_uint64(dev, "size", 0x1000); 550 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 551 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); 552 } 553 554 static void armsse_realize(DeviceState *dev, Error **errp) 555 { 556 ARMSSE *s = ARM_SSE(dev); 557 ARMSSEClass *asc = ARM_SSE_GET_CLASS(dev); 558 const ARMSSEInfo *info = asc->info; 559 const ARMSSEDeviceInfo *devinfo; 560 int i; 561 MemoryRegion *mr; 562 Error *err = NULL; 563 SysBusDevice *sbd_apb_ppc0; 564 SysBusDevice *sbd_secctl; 565 DeviceState *dev_apb_ppc0; 566 DeviceState *dev_apb_ppc1; 567 DeviceState *dev_secctl; 568 DeviceState *dev_splitter; 569 uint32_t addr_width_max; 570 571 if (!s->board_memory) { 572 error_setg(errp, "memory property was not set"); 573 return; 574 } 575 576 if (!clock_has_source(s->mainclk)) { 577 error_setg(errp, "MAINCLK clock was not connected"); 578 } 579 if (!clock_has_source(s->s32kclk)) { 580 error_setg(errp, "S32KCLK clock was not connected"); 581 } 582 583 assert(info->num_cpus <= SSE_MAX_CPUS); 584 585 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ 586 assert(is_power_of_2(info->sram_banks)); 587 addr_width_max = 24 - ctz32(info->sram_banks); 588 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { 589 error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d", 590 addr_width_max); 591 return; 592 } 593 594 /* Handling of which devices should be available only to secure 595 * code is usually done differently for M profile than for A profile. 596 * Instead of putting some devices only into the secure address space, 597 * devices exist in both address spaces but with hard-wired security 598 * permissions that will cause the CPU to fault for non-secure accesses. 599 * 600 * The ARMSSE has an IDAU (Implementation Defined Access Unit), 601 * which specifies hard-wired security permissions for different 602 * areas of the physical address space. For the ARMSSE IDAU, the 603 * top 4 bits of the physical address are the IDAU region ID, and 604 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS 605 * region, otherwise it is an S region. 606 * 607 * The various devices and RAMs are generally all mapped twice, 608 * once into a region that the IDAU defines as secure and once 609 * into a non-secure region. They sit behind either a Memory 610 * Protection Controller (for RAM) or a Peripheral Protection 611 * Controller (for devices), which allow a more fine grained 612 * configuration of whether non-secure accesses are permitted. 613 * 614 * (The other place that guest software can configure security 615 * permissions is in the architected SAU (Security Attribution 616 * Unit), which is entirely inside the CPU. The IDAU can upgrade 617 * the security attributes for a region to more restrictive than 618 * the SAU specifies, but cannot downgrade them.) 619 * 620 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff 621 * 0x20000000..0x2007ffff 32KB FPGA block RAM 622 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff 623 * 0x40000000..0x4000ffff base peripheral region 1 624 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) 625 * 0x40020000..0x4002ffff system control element peripherals 626 * 0x40080000..0x400fffff base peripheral region 2 627 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff 628 */ 629 630 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); 631 632 for (i = 0; i < info->num_cpus; i++) { 633 DeviceState *cpudev = DEVICE(&s->armv7m[i]); 634 Object *cpuobj = OBJECT(&s->armv7m[i]); 635 int j; 636 char *gpioname; 637 638 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IRQS); 639 /* 640 * In real hardware the initial Secure VTOR is set from the INITSVTOR* 641 * registers in the IoT Kit System Control Register block. In QEMU 642 * we set the initial value here, and also the reset value of the 643 * sysctl register, from this object's QOM init-svtor property. 644 * If the guest changes the INITSVTOR* registers at runtime then the 645 * code in iotkit-sysctl.c will update the CPU init-svtor property 646 * (which will then take effect on the next CPU warm-reset). 647 * 648 * Note that typically a board using the SSE-200 will have a system 649 * control processor whose boot firmware initializes the INITSVTOR* 650 * registers before powering up the CPUs. QEMU doesn't emulate 651 * the control processor, so instead we behave in the way that the 652 * firmware does: the initial value should be set by the board code 653 * (using the init-svtor property on the ARMSSE object) to match 654 * whatever its firmware does. 655 */ 656 qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); 657 /* 658 * CPUs start powered down if the corresponding bit in the CPUWAIT 659 * register is 1. In real hardware the CPUWAIT register reset value is 660 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and 661 * CPUWAIT1_RST parameters), but since all the boards we care about 662 * start CPU0 and leave CPU1 powered off, we hard-code that in 663 * info->cpuwait_rst for now. We can add QOM properties for this 664 * later if necessary. 665 */ 666 if (extract32(info->cpuwait_rst, i, 1)) { 667 if (!object_property_set_bool(cpuobj, "start-powered-off", true, 668 errp)) { 669 return; 670 } 671 } 672 if (!s->cpu_fpu[i]) { 673 if (!object_property_set_bool(cpuobj, "vfp", false, errp)) { 674 return; 675 } 676 } 677 if (!s->cpu_dsp[i]) { 678 if (!object_property_set_bool(cpuobj, "dsp", false, errp)) { 679 return; 680 } 681 } 682 683 if (i > 0) { 684 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 685 &s->container_alias[i - 1], -1); 686 } else { 687 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 688 &s->container, -1); 689 } 690 object_property_set_link(cpuobj, "memory", 691 OBJECT(&s->cpu_container[i]), &error_abort); 692 object_property_set_link(cpuobj, "idau", OBJECT(s), &error_abort); 693 if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj), errp)) { 694 return; 695 } 696 /* 697 * The cluster must be realized after the armv7m container, as 698 * the container's CPU object is only created on realize, and the 699 * CPU must exist and have been parented into the cluster before 700 * the cluster is realized. 701 */ 702 if (!qdev_realize(DEVICE(&s->cluster[i]), NULL, errp)) { 703 return; 704 } 705 706 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ 707 s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); 708 for (j = 0; j < s->exp_numirq; j++) { 709 s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + NUM_SSE_IRQS); 710 } 711 if (i == 0) { 712 gpioname = g_strdup("EXP_IRQ"); 713 } else { 714 gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i); 715 } 716 qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq, 717 s->exp_irqs[i], 718 gpioname, s->exp_numirq); 719 g_free(gpioname); 720 } 721 722 /* Wire up the splitters that connect common IRQs to all CPUs */ 723 if (info->num_cpus > 1) { 724 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 725 if (irq_is_common[i]) { 726 Object *splitter = OBJECT(&s->cpu_irq_splitter[i]); 727 DeviceState *devs = DEVICE(splitter); 728 int cpunum; 729 730 if (!object_property_set_int(splitter, "num-lines", 731 info->num_cpus, errp)) { 732 return; 733 } 734 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 735 return; 736 } 737 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 738 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 739 740 qdev_connect_gpio_out(devs, cpunum, 741 qdev_get_gpio_in(cpudev, i)); 742 } 743 } 744 } 745 } 746 747 /* Set up the big aliases first */ 748 make_alias(s, &s->alias1, &s->container, "alias 1", 749 0x10000000, 0x10000000, 0x00000000); 750 make_alias(s, &s->alias2, &s->container, 751 "alias 2", 0x30000000, 0x10000000, 0x20000000); 752 /* The 0x50000000..0x5fffffff region is not a pure alias: it has 753 * a few extra devices that only appear there (generally the 754 * control interfaces for the protection controllers). 755 * We implement this by mapping those devices over the top of this 756 * alias MR at a higher priority. Some of the devices in this range 757 * are per-CPU, so we must put this alias in the per-cpu containers. 758 */ 759 for (i = 0; i < info->num_cpus; i++) { 760 make_alias(s, &s->alias3[i], &s->cpu_container[i], 761 "alias 3", 0x50000000, 0x10000000, 0x40000000); 762 } 763 764 /* Security controller */ 765 object_property_set_int(OBJECT(&s->secctl), "sse-version", 766 info->sse_version, &error_abort); 767 if (!sysbus_realize(SYS_BUS_DEVICE(&s->secctl), errp)) { 768 return; 769 } 770 sbd_secctl = SYS_BUS_DEVICE(&s->secctl); 771 dev_secctl = DEVICE(&s->secctl); 772 sysbus_mmio_map(sbd_secctl, 0, 0x50080000); 773 sysbus_mmio_map(sbd_secctl, 1, 0x40080000); 774 775 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); 776 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); 777 778 /* The sec_resp_cfg output from the security controller must be split into 779 * multiple lines, one for each of the PPCs within the ARMSSE and one 780 * that will be an output from the ARMSSE to the system. 781 */ 782 if (!object_property_set_int(OBJECT(&s->sec_resp_splitter), 783 "num-lines", 3, errp)) { 784 return; 785 } 786 if (!qdev_realize(DEVICE(&s->sec_resp_splitter), NULL, errp)) { 787 return; 788 } 789 dev_splitter = DEVICE(&s->sec_resp_splitter); 790 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, 791 qdev_get_gpio_in(dev_splitter, 0)); 792 793 /* Each SRAM bank lives behind its own Memory Protection Controller */ 794 for (i = 0; i < info->sram_banks; i++) { 795 char *ramname = g_strdup_printf("armsse.sram%d", i); 796 SysBusDevice *sbd_mpc; 797 uint32_t sram_bank_size = 1 << s->sram_addr_width; 798 799 memory_region_init_ram(&s->sram[i], NULL, ramname, 800 sram_bank_size, &err); 801 g_free(ramname); 802 if (err) { 803 error_propagate(errp, err); 804 return; 805 } 806 object_property_set_link(OBJECT(&s->mpc[i]), "downstream", 807 OBJECT(&s->sram[i]), &error_abort); 808 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mpc[i]), errp)) { 809 return; 810 } 811 /* Map the upstream end of the MPC into the right place... */ 812 sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); 813 memory_region_add_subregion(&s->container, 814 0x20000000 + i * sram_bank_size, 815 sysbus_mmio_get_region(sbd_mpc, 1)); 816 /* ...and its register interface */ 817 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, 818 sysbus_mmio_get_region(sbd_mpc, 0)); 819 } 820 821 /* We must OR together lines from the MPC splitters to go to the NVIC */ 822 if (!object_property_set_int(OBJECT(&s->mpc_irq_orgate), "num-lines", 823 IOTS_NUM_EXP_MPC + info->sram_banks, 824 errp)) { 825 return; 826 } 827 if (!qdev_realize(DEVICE(&s->mpc_irq_orgate), NULL, errp)) { 828 return; 829 } 830 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, 831 armsse_get_common_irq_in(s, 9)); 832 833 /* This OR gate wires together outputs from the secure watchdogs to NMI */ 834 if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2, 835 errp)) { 836 return; 837 } 838 if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) { 839 return; 840 } 841 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, 842 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); 843 844 /* Devices behind APB PPC0: 845 * 0x40000000: timer0 846 * 0x40001000: timer1 847 * 0x40002000: dual timer 848 * 0x40003000: MHU0 (SSE-200 only) 849 * 0x40004000: MHU1 (SSE-200 only) 850 * We must configure and realize each downstream device and connect 851 * it to the appropriate PPC port; then we can realize the PPC and 852 * map its upstream ends to the right place in the container. 853 */ 854 for (devinfo = info->devinfo; devinfo->name; devinfo++) { 855 SysBusDevice *sbd; 856 qemu_irq irq; 857 858 if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) { 859 sbd = SYS_BUS_DEVICE(&s->timer[devinfo->index]); 860 861 qdev_connect_clock_in(DEVICE(sbd), "pclk", s->mainclk); 862 if (!sysbus_realize(sbd, errp)) { 863 return; 864 } 865 mr = sysbus_mmio_get_region(sbd, 0); 866 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_DUALTIMER)) { 867 sbd = SYS_BUS_DEVICE(&s->dualtimer); 868 869 qdev_connect_clock_in(DEVICE(sbd), "TIMCLK", s->mainclk); 870 if (!sysbus_realize(sbd, errp)) { 871 return; 872 } 873 mr = sysbus_mmio_get_region(sbd, 0); 874 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) { 875 sbd = SYS_BUS_DEVICE(&s->cmsdk_watchdog[devinfo->index]); 876 877 qdev_connect_clock_in(DEVICE(sbd), "WDOGCLK", 878 devinfo->slowclk ? s->s32kclk : s->mainclk); 879 if (!sysbus_realize(sbd, errp)) { 880 return; 881 } 882 mr = sysbus_mmio_get_region(sbd, 0); 883 } else { 884 g_assert_not_reached(); 885 } 886 887 switch (devinfo->irq) { 888 case NO_IRQ: 889 irq = NULL; 890 break; 891 case 0 ... NUM_SSE_IRQS - 1: 892 irq = armsse_get_common_irq_in(s, devinfo->irq); 893 break; 894 case NMI_0: 895 case NMI_1: 896 irq = qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 897 devinfo->irq - NMI_0); 898 break; 899 default: 900 g_assert_not_reached(); 901 } 902 903 if (irq) { 904 sysbus_connect_irq(sbd, 0, irq); 905 } 906 907 /* 908 * Devices connected to a PPC are connected to the port here; 909 * we will map the upstream end of that port to the right address 910 * in the container later after the PPC has been realized. 911 * Devices not connected to a PPC can be mapped immediately. 912 */ 913 if (devinfo->ppc != NO_PPC) { 914 TZPPC *ppc = &s->apb_ppc[devinfo->ppc]; 915 g_autofree char *portname = g_strdup_printf("port[%d]", 916 devinfo->ppc_port); 917 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), 918 &error_abort); 919 } else { 920 memory_region_add_subregion(&s->container, devinfo->addr, mr); 921 } 922 } 923 924 if (info->has_mhus) { 925 /* 926 * An SSE-200 with only one CPU should have only one MHU created, 927 * with the region where the second MHU usually is being RAZ/WI. 928 * We don't implement that SSE-200 config; if we want to support 929 * it then this code needs to be enhanced to handle creating the 930 * RAZ/WI region instead of the second MHU. 931 */ 932 assert(info->num_cpus == ARRAY_SIZE(s->mhu)); 933 934 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { 935 char *port; 936 int cpunum; 937 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]); 938 939 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mhu[i]), errp)) { 940 return; 941 } 942 port = g_strdup_printf("port[%d]", i + 3); 943 mr = sysbus_mmio_get_region(mhu_sbd, 0); 944 object_property_set_link(OBJECT(&s->apb_ppc[0]), port, OBJECT(mr), 945 &error_abort); 946 g_free(port); 947 948 /* 949 * Each MHU has an irq line for each CPU: 950 * MHU 0 irq line 0 -> CPU 0 IRQ 6 951 * MHU 0 irq line 1 -> CPU 1 IRQ 6 952 * MHU 1 irq line 0 -> CPU 0 IRQ 7 953 * MHU 1 irq line 1 -> CPU 1 IRQ 7 954 */ 955 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 956 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 957 958 sysbus_connect_irq(mhu_sbd, cpunum, 959 qdev_get_gpio_in(cpudev, 6 + i)); 960 } 961 } 962 } 963 964 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[0]), errp)) { 965 return; 966 } 967 968 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc[0]); 969 dev_apb_ppc0 = DEVICE(&s->apb_ppc[0]); 970 971 if (info->has_mhus) { 972 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3); 973 memory_region_add_subregion(&s->container, 0x40003000, mr); 974 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4); 975 memory_region_add_subregion(&s->container, 0x40004000, mr); 976 } 977 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { 978 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, 979 qdev_get_gpio_in_named(dev_apb_ppc0, 980 "cfg_nonsec", i)); 981 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, 982 qdev_get_gpio_in_named(dev_apb_ppc0, 983 "cfg_ap", i)); 984 } 985 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, 986 qdev_get_gpio_in_named(dev_apb_ppc0, 987 "irq_enable", 0)); 988 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, 989 qdev_get_gpio_in_named(dev_apb_ppc0, 990 "irq_clear", 0)); 991 qdev_connect_gpio_out(dev_splitter, 0, 992 qdev_get_gpio_in_named(dev_apb_ppc0, 993 "cfg_sec_resp", 0)); 994 995 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external 996 * ones) are sent individually to the security controller, and also 997 * ORed together to give a single combined PPC interrupt to the NVIC. 998 */ 999 if (!object_property_set_int(OBJECT(&s->ppc_irq_orgate), 1000 "num-lines", NUM_PPCS, errp)) { 1001 return; 1002 } 1003 if (!qdev_realize(DEVICE(&s->ppc_irq_orgate), NULL, errp)) { 1004 return; 1005 } 1006 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, 1007 armsse_get_common_irq_in(s, 10)); 1008 1009 /* 1010 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): 1011 * private per-CPU region (all these devices are SSE-200 only): 1012 * 0x50010000: L1 icache control registers 1013 * 0x50011000: CPUSECCTRL (CPU local security control registers) 1014 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block 1015 */ 1016 if (info->has_cachectrl) { 1017 for (i = 0; i < info->num_cpus; i++) { 1018 char *name = g_strdup_printf("cachectrl%d", i); 1019 MemoryRegion *mr; 1020 1021 qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); 1022 g_free(name); 1023 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); 1024 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cachectrl[i]), errp)) { 1025 return; 1026 } 1027 1028 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); 1029 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); 1030 } 1031 } 1032 if (info->has_cpusecctrl) { 1033 for (i = 0; i < info->num_cpus; i++) { 1034 char *name = g_strdup_printf("CPUSECCTRL%d", i); 1035 MemoryRegion *mr; 1036 1037 qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); 1038 g_free(name); 1039 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); 1040 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpusecctrl[i]), errp)) { 1041 return; 1042 } 1043 1044 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); 1045 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); 1046 } 1047 } 1048 if (info->has_cpuid) { 1049 for (i = 0; i < info->num_cpus; i++) { 1050 MemoryRegion *mr; 1051 1052 qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); 1053 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpuid[i]), errp)) { 1054 return; 1055 } 1056 1057 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); 1058 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); 1059 } 1060 } 1061 1062 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */ 1063 /* Devices behind APB PPC1: 1064 * 0x4002f000: S32K timer 1065 */ 1066 qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); 1067 if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { 1068 return; 1069 } 1070 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, 1071 armsse_get_common_irq_in(s, 2)); 1072 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); 1073 object_property_set_link(OBJECT(&s->apb_ppc[1]), "port[0]", OBJECT(mr), 1074 &error_abort); 1075 1076 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[1]), errp)) { 1077 return; 1078 } 1079 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc[1]), 0); 1080 memory_region_add_subregion(&s->container, 0x4002f000, mr); 1081 1082 dev_apb_ppc1 = DEVICE(&s->apb_ppc[1]); 1083 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, 1084 qdev_get_gpio_in_named(dev_apb_ppc1, 1085 "cfg_nonsec", 0)); 1086 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, 1087 qdev_get_gpio_in_named(dev_apb_ppc1, 1088 "cfg_ap", 0)); 1089 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, 1090 qdev_get_gpio_in_named(dev_apb_ppc1, 1091 "irq_enable", 0)); 1092 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, 1093 qdev_get_gpio_in_named(dev_apb_ppc1, 1094 "irq_clear", 0)); 1095 qdev_connect_gpio_out(dev_splitter, 1, 1096 qdev_get_gpio_in_named(dev_apb_ppc1, 1097 "cfg_sec_resp", 0)); 1098 1099 /* 1100 * Now both PPCs are realized we can map the upstream ends of 1101 * ports which correspond to entries in the devinfo array. 1102 * The ports which are connected to non-devinfo devices have 1103 * already been mapped. 1104 */ 1105 for (devinfo = info->devinfo; devinfo->name; devinfo++) { 1106 SysBusDevice *ppc_sbd; 1107 1108 if (devinfo->ppc == NO_PPC) { 1109 continue; 1110 } 1111 ppc_sbd = SYS_BUS_DEVICE(&s->apb_ppc[devinfo->ppc]); 1112 mr = sysbus_mmio_get_region(ppc_sbd, devinfo->ppc_port); 1113 memory_region_add_subregion(&s->container, devinfo->addr, mr); 1114 } 1115 1116 if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION", 1117 info->sys_version, errp)) { 1118 return; 1119 } 1120 if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG", 1121 armsse_sys_config_value(s, info), errp)) { 1122 return; 1123 } 1124 object_property_set_int(OBJECT(&s->sysinfo), "sse-version", 1125 info->sse_version, &error_abort); 1126 object_property_set_int(OBJECT(&s->sysinfo), "IIDR", 1127 info->iidr, &error_abort); 1128 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), errp)) { 1129 return; 1130 } 1131 /* System information registers */ 1132 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); 1133 /* System control registers */ 1134 object_property_set_int(OBJECT(&s->sysctl), "sse-version", 1135 info->sse_version, &error_abort); 1136 object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST", 1137 info->cpuwait_rst, &error_abort); 1138 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST", 1139 s->init_svtor, &error_abort); 1140 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST", 1141 s->init_svtor, &error_abort); 1142 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysctl), errp)) { 1143 return; 1144 } 1145 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); 1146 1147 if (info->has_ppus) { 1148 /* CPUnCORE_PPU for each CPU */ 1149 for (i = 0; i < info->num_cpus; i++) { 1150 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 1151 1152 map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); 1153 /* 1154 * We don't support CPU debug so don't create the 1155 * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. 1156 */ 1157 g_free(name); 1158 } 1159 map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); 1160 1161 for (i = 0; i < info->sram_banks; i++) { 1162 char *name = g_strdup_printf("RAM%d_PPU", i); 1163 1164 map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); 1165 g_free(name); 1166 } 1167 } 1168 1169 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 1170 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); 1171 1172 if (!object_property_set_int(splitter, "num-lines", 2, errp)) { 1173 return; 1174 } 1175 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1176 return; 1177 } 1178 } 1179 1180 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { 1181 char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); 1182 1183 armsse_forward_ppc(s, ppcname, i); 1184 g_free(ppcname); 1185 } 1186 1187 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { 1188 char *ppcname = g_strdup_printf("apb_ppcexp%d", i); 1189 1190 armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); 1191 g_free(ppcname); 1192 } 1193 1194 for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { 1195 /* Wire up IRQ splitter for internal PPCs */ 1196 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); 1197 char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", 1198 i - NUM_EXTERNAL_PPCS); 1199 TZPPC *ppc = &s->apb_ppc[i - NUM_EXTERNAL_PPCS]; 1200 1201 qdev_connect_gpio_out(devs, 0, 1202 qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); 1203 qdev_connect_gpio_out(devs, 1, 1204 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); 1205 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, 1206 qdev_get_gpio_in(devs, 0)); 1207 g_free(gpioname); 1208 } 1209 1210 /* Wire up the splitters for the MPC IRQs */ 1211 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 1212 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 1213 DeviceState *dev_splitter = DEVICE(splitter); 1214 1215 if (!object_property_set_int(OBJECT(splitter), "num-lines", 2, 1216 errp)) { 1217 return; 1218 } 1219 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1220 return; 1221 } 1222 1223 if (i < IOTS_NUM_EXP_MPC) { 1224 /* Splitter input is from GPIO input line */ 1225 s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0); 1226 qdev_connect_gpio_out(dev_splitter, 0, 1227 qdev_get_gpio_in_named(dev_secctl, 1228 "mpcexp_status", i)); 1229 } else { 1230 /* Splitter input is from our own MPC */ 1231 qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]), 1232 "irq", 0, 1233 qdev_get_gpio_in(dev_splitter, 0)); 1234 qdev_connect_gpio_out(dev_splitter, 0, 1235 qdev_get_gpio_in_named(dev_secctl, 1236 "mpc_status", 1237 i - IOTS_NUM_EXP_MPC)); 1238 } 1239 1240 qdev_connect_gpio_out(dev_splitter, 1, 1241 qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i)); 1242 } 1243 /* Create GPIO inputs which will pass the line state for our 1244 * mpcexp_irq inputs to the correct splitter devices. 1245 */ 1246 qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status", 1247 IOTS_NUM_EXP_MPC); 1248 1249 armsse_forward_sec_resp_cfg(s); 1250 1251 /* Forward the MSC related signals */ 1252 qdev_pass_gpios(dev_secctl, dev, "mscexp_status"); 1253 qdev_pass_gpios(dev_secctl, dev, "mscexp_clear"); 1254 qdev_pass_gpios(dev_secctl, dev, "mscexp_ns"); 1255 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, 1256 armsse_get_common_irq_in(s, 11)); 1257 1258 /* 1259 * Expose our container region to the board model; this corresponds 1260 * to the AHB Slave Expansion ports which allow bus master devices 1261 * (eg DMA controllers) in the board model to make transactions into 1262 * devices in the ARMSSE. 1263 */ 1264 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); 1265 1266 /* Set initial system_clock_scale from MAINCLK */ 1267 armsse_mainclk_update(s, ClockUpdate); 1268 } 1269 1270 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, 1271 int *iregion, bool *exempt, bool *ns, bool *nsc) 1272 { 1273 /* 1274 * For ARMSSE systems the IDAU responses are simple logical functions 1275 * of the address bits. The NSC attribute is guest-adjustable via the 1276 * NSCCFG register in the security controller. 1277 */ 1278 ARMSSE *s = ARM_SSE(ii); 1279 int region = extract32(address, 28, 4); 1280 1281 *ns = !(region & 1); 1282 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); 1283 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1284 *exempt = (address & 0xeff00000) == 0xe0000000; 1285 *iregion = region; 1286 } 1287 1288 static const VMStateDescription armsse_vmstate = { 1289 .name = "iotkit", 1290 .version_id = 2, 1291 .minimum_version_id = 2, 1292 .fields = (VMStateField[]) { 1293 VMSTATE_CLOCK(mainclk, ARMSSE), 1294 VMSTATE_CLOCK(s32kclk, ARMSSE), 1295 VMSTATE_UINT32(nsccfg, ARMSSE), 1296 VMSTATE_END_OF_LIST() 1297 } 1298 }; 1299 1300 static void armsse_reset(DeviceState *dev) 1301 { 1302 ARMSSE *s = ARM_SSE(dev); 1303 1304 s->nsccfg = 0; 1305 } 1306 1307 static void armsse_class_init(ObjectClass *klass, void *data) 1308 { 1309 DeviceClass *dc = DEVICE_CLASS(klass); 1310 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); 1311 ARMSSEClass *asc = ARM_SSE_CLASS(klass); 1312 const ARMSSEInfo *info = data; 1313 1314 dc->realize = armsse_realize; 1315 dc->vmsd = &armsse_vmstate; 1316 device_class_set_props(dc, info->props); 1317 dc->reset = armsse_reset; 1318 iic->check = armsse_idau_check; 1319 asc->info = info; 1320 } 1321 1322 static const TypeInfo armsse_info = { 1323 .name = TYPE_ARM_SSE, 1324 .parent = TYPE_SYS_BUS_DEVICE, 1325 .instance_size = sizeof(ARMSSE), 1326 .class_size = sizeof(ARMSSEClass), 1327 .instance_init = armsse_init, 1328 .abstract = true, 1329 .interfaces = (InterfaceInfo[]) { 1330 { TYPE_IDAU_INTERFACE }, 1331 { } 1332 } 1333 }; 1334 1335 static void armsse_register_types(void) 1336 { 1337 int i; 1338 1339 type_register_static(&armsse_info); 1340 1341 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) { 1342 TypeInfo ti = { 1343 .name = armsse_variants[i].name, 1344 .parent = TYPE_ARM_SSE, 1345 .class_init = armsse_class_init, 1346 .class_data = (void *)&armsse_variants[i], 1347 }; 1348 type_register(&ti); 1349 } 1350 } 1351 1352 type_init(armsse_register_types); 1353