1 /* 2 * Allwinner R40/A40i/T3 System on Chip emulation 3 * 4 * Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/error-report.h" 23 #include "qemu/bswap.h" 24 #include "qemu/module.h" 25 #include "qemu/units.h" 26 #include "hw/qdev-core.h" 27 #include "hw/sysbus.h" 28 #include "hw/char/serial.h" 29 #include "hw/misc/unimp.h" 30 #include "hw/usb/hcd-ehci.h" 31 #include "hw/loader.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/arm/allwinner-r40.h" 34 35 /* Memory map */ 36 const hwaddr allwinner_r40_memmap[] = { 37 [AW_R40_DEV_SRAM_A1] = 0x00000000, 38 [AW_R40_DEV_SRAM_A2] = 0x00004000, 39 [AW_R40_DEV_SRAM_A3] = 0x00008000, 40 [AW_R40_DEV_SRAM_A4] = 0x0000b400, 41 [AW_R40_DEV_MMC0] = 0x01c0f000, 42 [AW_R40_DEV_MMC1] = 0x01c10000, 43 [AW_R40_DEV_MMC2] = 0x01c11000, 44 [AW_R40_DEV_MMC3] = 0x01c12000, 45 [AW_R40_DEV_CCU] = 0x01c20000, 46 [AW_R40_DEV_PIT] = 0x01c20c00, 47 [AW_R40_DEV_UART0] = 0x01c28000, 48 [AW_R40_DEV_UART1] = 0x01c28400, 49 [AW_R40_DEV_UART2] = 0x01c28800, 50 [AW_R40_DEV_UART3] = 0x01c28c00, 51 [AW_R40_DEV_UART4] = 0x01c29000, 52 [AW_R40_DEV_UART5] = 0x01c29400, 53 [AW_R40_DEV_UART6] = 0x01c29800, 54 [AW_R40_DEV_UART7] = 0x01c29c00, 55 [AW_R40_DEV_GIC_DIST] = 0x01c81000, 56 [AW_R40_DEV_GIC_CPU] = 0x01c82000, 57 [AW_R40_DEV_GIC_HYP] = 0x01c84000, 58 [AW_R40_DEV_GIC_VCPU] = 0x01c86000, 59 [AW_R40_DEV_SDRAM] = 0x40000000 60 }; 61 62 /* List of unimplemented devices */ 63 struct AwR40Unimplemented { 64 const char *device_name; 65 hwaddr base; 66 hwaddr size; 67 }; 68 69 static struct AwR40Unimplemented r40_unimplemented[] = { 70 { "d-engine", 0x01000000, 4 * MiB }, 71 { "d-inter", 0x01400000, 128 * KiB }, 72 { "sram-c", 0x01c00000, 4 * KiB }, 73 { "dma", 0x01c02000, 4 * KiB }, 74 { "nfdc", 0x01c03000, 4 * KiB }, 75 { "ts", 0x01c04000, 4 * KiB }, 76 { "spi0", 0x01c05000, 4 * KiB }, 77 { "spi1", 0x01c06000, 4 * KiB }, 78 { "cs0", 0x01c09000, 4 * KiB }, 79 { "keymem", 0x01c0a000, 4 * KiB }, 80 { "emac", 0x01c0b000, 4 * KiB }, 81 { "usb0-otg", 0x01c13000, 4 * KiB }, 82 { "usb0-host", 0x01c14000, 4 * KiB }, 83 { "crypto", 0x01c15000, 4 * KiB }, 84 { "spi2", 0x01c17000, 4 * KiB }, 85 { "sata", 0x01c18000, 4 * KiB }, 86 { "usb1-host", 0x01c19000, 4 * KiB }, 87 { "sid", 0x01c1b000, 4 * KiB }, 88 { "usb2-host", 0x01c1c000, 4 * KiB }, 89 { "cs1", 0x01c1d000, 4 * KiB }, 90 { "spi3", 0x01c1f000, 4 * KiB }, 91 { "rtc", 0x01c20400, 1 * KiB }, 92 { "pio", 0x01c20800, 1 * KiB }, 93 { "owa", 0x01c21000, 1 * KiB }, 94 { "ac97", 0x01c21400, 1 * KiB }, 95 { "cir0", 0x01c21800, 1 * KiB }, 96 { "cir1", 0x01c21c00, 1 * KiB }, 97 { "pcm0", 0x01c22000, 1 * KiB }, 98 { "pcm1", 0x01c22400, 1 * KiB }, 99 { "pcm2", 0x01c22800, 1 * KiB }, 100 { "audio", 0x01c22c00, 1 * KiB }, 101 { "keypad", 0x01c23000, 1 * KiB }, 102 { "pwm", 0x01c23400, 1 * KiB }, 103 { "keyadc", 0x01c24400, 1 * KiB }, 104 { "ths", 0x01c24c00, 1 * KiB }, 105 { "rtp", 0x01c25000, 1 * KiB }, 106 { "pmu", 0x01c25400, 1 * KiB }, 107 { "cpu-cfg", 0x01c25c00, 1 * KiB }, 108 { "uart0", 0x01c28000, 1 * KiB }, 109 { "uart1", 0x01c28400, 1 * KiB }, 110 { "uart2", 0x01c28800, 1 * KiB }, 111 { "uart3", 0x01c28c00, 1 * KiB }, 112 { "uart4", 0x01c29000, 1 * KiB }, 113 { "uart5", 0x01c29400, 1 * KiB }, 114 { "uart6", 0x01c29800, 1 * KiB }, 115 { "uart7", 0x01c29c00, 1 * KiB }, 116 { "ps20", 0x01c2a000, 1 * KiB }, 117 { "ps21", 0x01c2a400, 1 * KiB }, 118 { "twi0", 0x01c2ac00, 1 * KiB }, 119 { "twi1", 0x01c2b000, 1 * KiB }, 120 { "twi2", 0x01c2b400, 1 * KiB }, 121 { "twi3", 0x01c2b800, 1 * KiB }, 122 { "twi4", 0x01c2c000, 1 * KiB }, 123 { "scr", 0x01c2c400, 1 * KiB }, 124 { "tvd-top", 0x01c30000, 4 * KiB }, 125 { "tvd0", 0x01c31000, 4 * KiB }, 126 { "tvd1", 0x01c32000, 4 * KiB }, 127 { "tvd2", 0x01c33000, 4 * KiB }, 128 { "tvd3", 0x01c34000, 4 * KiB }, 129 { "gpu", 0x01c40000, 64 * KiB }, 130 { "gmac", 0x01c50000, 64 * KiB }, 131 { "hstmr", 0x01c60000, 4 * KiB }, 132 { "dram-com", 0x01c62000, 4 * KiB }, 133 { "dram-ctl", 0x01c63000, 4 * KiB }, 134 { "tcon-top", 0x01c70000, 4 * KiB }, 135 { "lcd0", 0x01c71000, 4 * KiB }, 136 { "lcd1", 0x01c72000, 4 * KiB }, 137 { "tv0", 0x01c73000, 4 * KiB }, 138 { "tv1", 0x01c74000, 4 * KiB }, 139 { "tve-top", 0x01c90000, 16 * KiB }, 140 { "tve0", 0x01c94000, 16 * KiB }, 141 { "tve1", 0x01c98000, 16 * KiB }, 142 { "mipi_dsi", 0x01ca0000, 4 * KiB }, 143 { "mipi_dphy", 0x01ca1000, 4 * KiB }, 144 { "ve", 0x01d00000, 1024 * KiB }, 145 { "mp", 0x01e80000, 128 * KiB }, 146 { "hdmi", 0x01ee0000, 128 * KiB }, 147 { "prcm", 0x01f01400, 1 * KiB }, 148 { "debug", 0x3f500000, 64 * KiB }, 149 { "cpubist", 0x3f501000, 4 * KiB }, 150 { "dcu", 0x3fff0000, 64 * KiB }, 151 { "hstmr", 0x01c60000, 4 * KiB }, 152 { "brom", 0xffff0000, 36 * KiB } 153 }; 154 155 /* Per Processor Interrupts */ 156 enum { 157 AW_R40_GIC_PPI_MAINT = 9, 158 AW_R40_GIC_PPI_HYPTIMER = 10, 159 AW_R40_GIC_PPI_VIRTTIMER = 11, 160 AW_R40_GIC_PPI_SECTIMER = 13, 161 AW_R40_GIC_PPI_PHYSTIMER = 14 162 }; 163 164 /* Shared Processor Interrupts */ 165 enum { 166 AW_R40_GIC_SPI_UART0 = 1, 167 AW_R40_GIC_SPI_UART1 = 2, 168 AW_R40_GIC_SPI_UART2 = 3, 169 AW_R40_GIC_SPI_UART3 = 4, 170 AW_R40_GIC_SPI_UART4 = 17, 171 AW_R40_GIC_SPI_UART5 = 18, 172 AW_R40_GIC_SPI_UART6 = 19, 173 AW_R40_GIC_SPI_UART7 = 20, 174 AW_R40_GIC_SPI_TIMER0 = 22, 175 AW_R40_GIC_SPI_TIMER1 = 23, 176 AW_R40_GIC_SPI_MMC0 = 32, 177 AW_R40_GIC_SPI_MMC1 = 33, 178 AW_R40_GIC_SPI_MMC2 = 34, 179 AW_R40_GIC_SPI_MMC3 = 35, 180 }; 181 182 /* Allwinner R40 general constants */ 183 enum { 184 AW_R40_GIC_NUM_SPI = 128 185 }; 186 187 #define BOOT0_MAGIC "eGON.BT0" 188 189 /* The low 8-bits of the 'boot_media' field in the SPL header */ 190 #define SUNXI_BOOTED_FROM_MMC0 0 191 #define SUNXI_BOOTED_FROM_NAND 1 192 #define SUNXI_BOOTED_FROM_MMC2 2 193 #define SUNXI_BOOTED_FROM_SPI 3 194 195 struct boot_file_head { 196 uint32_t b_instruction; 197 uint8_t magic[8]; 198 uint32_t check_sum; 199 uint32_t length; 200 uint32_t pub_head_size; 201 uint32_t fel_script_address; 202 uint32_t fel_uEnv_length; 203 uint32_t dt_name_offset; 204 uint32_t dram_size; 205 uint32_t boot_media; 206 uint32_t string_pool[13]; 207 }; 208 209 bool allwinner_r40_bootrom_setup(AwR40State *s, BlockBackend *blk, int unit) 210 { 211 const int64_t rom_size = 32 * KiB; 212 g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size); 213 struct boot_file_head *head = (struct boot_file_head *)buffer; 214 215 if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) { 216 error_setg(&error_fatal, "%s: failed to read BlockBackend data", 217 __func__); 218 return false; 219 } 220 221 /* we only check the magic string here. */ 222 if (memcmp(head->magic, BOOT0_MAGIC, sizeof(head->magic))) { 223 return false; 224 } 225 226 /* 227 * Simulate the behavior of the bootROM, it will change the boot_media 228 * flag to indicate where the chip is booting from. R40 can boot from 229 * mmc0 or mmc2, the default value of boot_media is zero 230 * (SUNXI_BOOTED_FROM_MMC0), let's fix this flag when it is booting from 231 * the others. 232 */ 233 if (unit == 2) { 234 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC2); 235 } else { 236 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC0); 237 } 238 239 rom_add_blob("allwinner-r40.bootrom", buffer, rom_size, 240 rom_size, s->memmap[AW_R40_DEV_SRAM_A1], 241 NULL, NULL, NULL, NULL, false); 242 return true; 243 } 244 245 static void allwinner_r40_init(Object *obj) 246 { 247 static const char *mmc_names[AW_R40_NUM_MMCS] = { 248 "mmc0", "mmc1", "mmc2", "mmc3" 249 }; 250 AwR40State *s = AW_R40(obj); 251 252 s->memmap = allwinner_r40_memmap; 253 254 for (int i = 0; i < AW_R40_NUM_CPUS; i++) { 255 object_initialize_child(obj, "cpu[*]", &s->cpus[i], 256 ARM_CPU_TYPE_NAME("cortex-a7")); 257 } 258 259 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); 260 261 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT); 262 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer), 263 "clk0-freq"); 264 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), 265 "clk1-freq"); 266 267 object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_R40_CCU); 268 269 for (int i = 0; i < AW_R40_NUM_MMCS; i++) { 270 object_initialize_child(obj, mmc_names[i], &s->mmc[i], 271 TYPE_AW_SDHOST_SUN5I); 272 } 273 } 274 275 static void allwinner_r40_realize(DeviceState *dev, Error **errp) 276 { 277 AwR40State *s = AW_R40(dev); 278 unsigned i; 279 280 /* CPUs */ 281 for (i = 0; i < AW_R40_NUM_CPUS; i++) { 282 283 /* 284 * Disable secondary CPUs. Guest EL3 firmware will start 285 * them via CPU reset control registers. 286 */ 287 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", 288 i > 0); 289 290 /* All exception levels required */ 291 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true); 292 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true); 293 294 /* Mark realized */ 295 qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal); 296 } 297 298 /* Generic Interrupt Controller */ 299 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_R40_GIC_NUM_SPI + 300 GIC_INTERNAL); 301 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 302 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_R40_NUM_CPUS); 303 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false); 304 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true); 305 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal); 306 307 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_R40_DEV_GIC_DIST]); 308 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_R40_DEV_GIC_CPU]); 309 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_R40_DEV_GIC_HYP]); 310 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_R40_DEV_GIC_VCPU]); 311 312 /* 313 * Wire the outputs from each CPU's generic timer and the GICv2 314 * maintenance interrupt signal to the appropriate GIC PPI inputs, 315 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 316 */ 317 for (i = 0; i < AW_R40_NUM_CPUS; i++) { 318 DeviceState *cpudev = DEVICE(&s->cpus[i]); 319 int ppibase = AW_R40_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS; 320 int irq; 321 /* 322 * Mapping from the output timer irq lines from the CPU to the 323 * GIC PPI inputs used for this board. 324 */ 325 const int timer_irq[] = { 326 [GTIMER_PHYS] = AW_R40_GIC_PPI_PHYSTIMER, 327 [GTIMER_VIRT] = AW_R40_GIC_PPI_VIRTTIMER, 328 [GTIMER_HYP] = AW_R40_GIC_PPI_HYPTIMER, 329 [GTIMER_SEC] = AW_R40_GIC_PPI_SECTIMER, 330 }; 331 332 /* Connect CPU timer outputs to GIC PPI inputs */ 333 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 334 qdev_connect_gpio_out(cpudev, irq, 335 qdev_get_gpio_in(DEVICE(&s->gic), 336 ppibase + timer_irq[irq])); 337 } 338 339 /* Connect GIC outputs to CPU interrupt inputs */ 340 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 341 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 342 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_R40_NUM_CPUS, 343 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 344 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_R40_NUM_CPUS), 345 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 346 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_R40_NUM_CPUS), 347 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 348 349 /* GIC maintenance signal */ 350 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_R40_NUM_CPUS), 351 qdev_get_gpio_in(DEVICE(&s->gic), 352 ppibase + AW_R40_GIC_PPI_MAINT)); 353 } 354 355 /* Timer */ 356 sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal); 357 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_R40_DEV_PIT]); 358 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0, 359 qdev_get_gpio_in(DEVICE(&s->gic), 360 AW_R40_GIC_SPI_TIMER0)); 361 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1, 362 qdev_get_gpio_in(DEVICE(&s->gic), 363 AW_R40_GIC_SPI_TIMER1)); 364 365 /* SRAM */ 366 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1", 367 16 * KiB, &error_abort); 368 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2", 369 16 * KiB, &error_abort); 370 memory_region_init_ram(&s->sram_a3, OBJECT(dev), "sram A3", 371 13 * KiB, &error_abort); 372 memory_region_init_ram(&s->sram_a4, OBJECT(dev), "sram A4", 373 3 * KiB, &error_abort); 374 memory_region_add_subregion(get_system_memory(), 375 s->memmap[AW_R40_DEV_SRAM_A1], &s->sram_a1); 376 memory_region_add_subregion(get_system_memory(), 377 s->memmap[AW_R40_DEV_SRAM_A2], &s->sram_a2); 378 memory_region_add_subregion(get_system_memory(), 379 s->memmap[AW_R40_DEV_SRAM_A3], &s->sram_a3); 380 memory_region_add_subregion(get_system_memory(), 381 s->memmap[AW_R40_DEV_SRAM_A4], &s->sram_a4); 382 383 /* Clock Control Unit */ 384 sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal); 385 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]); 386 387 /* SD/MMC */ 388 for (int i = 0; i < AW_R40_NUM_MMCS; i++) { 389 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->gic), 390 AW_R40_GIC_SPI_MMC0 + i); 391 const hwaddr addr = s->memmap[AW_R40_DEV_MMC0 + i]; 392 393 object_property_set_link(OBJECT(&s->mmc[i]), "dma-memory", 394 OBJECT(get_system_memory()), &error_fatal); 395 sysbus_realize(SYS_BUS_DEVICE(&s->mmc[i]), &error_fatal); 396 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc[i]), 0, addr); 397 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc[i]), 0, irq); 398 } 399 400 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */ 401 for (int i = 0; i < AW_R40_NUM_UARTS; i++) { 402 static const int uart_irqs[AW_R40_NUM_UARTS] = { 403 AW_R40_GIC_SPI_UART0, 404 AW_R40_GIC_SPI_UART1, 405 AW_R40_GIC_SPI_UART2, 406 AW_R40_GIC_SPI_UART3, 407 AW_R40_GIC_SPI_UART4, 408 AW_R40_GIC_SPI_UART5, 409 AW_R40_GIC_SPI_UART6, 410 AW_R40_GIC_SPI_UART7, 411 }; 412 const hwaddr addr = s->memmap[AW_R40_DEV_UART0 + i]; 413 414 serial_mm_init(get_system_memory(), addr, 2, 415 qdev_get_gpio_in(DEVICE(&s->gic), uart_irqs[i]), 416 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN); 417 } 418 419 /* Unimplemented devices */ 420 for (i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) { 421 create_unimplemented_device(r40_unimplemented[i].device_name, 422 r40_unimplemented[i].base, 423 r40_unimplemented[i].size); 424 } 425 } 426 427 static void allwinner_r40_class_init(ObjectClass *oc, void *data) 428 { 429 DeviceClass *dc = DEVICE_CLASS(oc); 430 431 dc->realize = allwinner_r40_realize; 432 /* Reason: uses serial_hd() in realize function */ 433 dc->user_creatable = false; 434 } 435 436 static const TypeInfo allwinner_r40_type_info = { 437 .name = TYPE_AW_R40, 438 .parent = TYPE_DEVICE, 439 .instance_size = sizeof(AwR40State), 440 .instance_init = allwinner_r40_init, 441 .class_init = allwinner_r40_class_init, 442 }; 443 444 static void allwinner_r40_register_types(void) 445 { 446 type_register_static(&allwinner_r40_type_info); 447 } 448 449 type_init(allwinner_r40_register_types) 450