1 /* 2 * Allwinner R40/A40i/T3 System on Chip emulation 3 * 4 * Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/error-report.h" 23 #include "qemu/bswap.h" 24 #include "qemu/module.h" 25 #include "qemu/units.h" 26 #include "hw/qdev-core.h" 27 #include "hw/sysbus.h" 28 #include "hw/char/serial.h" 29 #include "hw/misc/unimp.h" 30 #include "hw/usb/hcd-ehci.h" 31 #include "hw/loader.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/arm/allwinner-r40.h" 34 35 /* Memory map */ 36 const hwaddr allwinner_r40_memmap[] = { 37 [AW_R40_DEV_SRAM_A1] = 0x00000000, 38 [AW_R40_DEV_SRAM_A2] = 0x00004000, 39 [AW_R40_DEV_SRAM_A3] = 0x00008000, 40 [AW_R40_DEV_SRAM_A4] = 0x0000b400, 41 [AW_R40_DEV_MMC0] = 0x01c0f000, 42 [AW_R40_DEV_MMC1] = 0x01c10000, 43 [AW_R40_DEV_MMC2] = 0x01c11000, 44 [AW_R40_DEV_MMC3] = 0x01c12000, 45 [AW_R40_DEV_CCU] = 0x01c20000, 46 [AW_R40_DEV_PIT] = 0x01c20c00, 47 [AW_R40_DEV_UART0] = 0x01c28000, 48 [AW_R40_DEV_UART1] = 0x01c28400, 49 [AW_R40_DEV_UART2] = 0x01c28800, 50 [AW_R40_DEV_UART3] = 0x01c28c00, 51 [AW_R40_DEV_UART4] = 0x01c29000, 52 [AW_R40_DEV_UART5] = 0x01c29400, 53 [AW_R40_DEV_UART6] = 0x01c29800, 54 [AW_R40_DEV_UART7] = 0x01c29c00, 55 [AW_R40_DEV_TWI0] = 0x01c2ac00, 56 [AW_R40_DEV_GIC_DIST] = 0x01c81000, 57 [AW_R40_DEV_GIC_CPU] = 0x01c82000, 58 [AW_R40_DEV_GIC_HYP] = 0x01c84000, 59 [AW_R40_DEV_GIC_VCPU] = 0x01c86000, 60 [AW_R40_DEV_SDRAM] = 0x40000000 61 }; 62 63 /* List of unimplemented devices */ 64 struct AwR40Unimplemented { 65 const char *device_name; 66 hwaddr base; 67 hwaddr size; 68 }; 69 70 static struct AwR40Unimplemented r40_unimplemented[] = { 71 { "d-engine", 0x01000000, 4 * MiB }, 72 { "d-inter", 0x01400000, 128 * KiB }, 73 { "sram-c", 0x01c00000, 4 * KiB }, 74 { "dma", 0x01c02000, 4 * KiB }, 75 { "nfdc", 0x01c03000, 4 * KiB }, 76 { "ts", 0x01c04000, 4 * KiB }, 77 { "spi0", 0x01c05000, 4 * KiB }, 78 { "spi1", 0x01c06000, 4 * KiB }, 79 { "cs0", 0x01c09000, 4 * KiB }, 80 { "keymem", 0x01c0a000, 4 * KiB }, 81 { "emac", 0x01c0b000, 4 * KiB }, 82 { "usb0-otg", 0x01c13000, 4 * KiB }, 83 { "usb0-host", 0x01c14000, 4 * KiB }, 84 { "crypto", 0x01c15000, 4 * KiB }, 85 { "spi2", 0x01c17000, 4 * KiB }, 86 { "sata", 0x01c18000, 4 * KiB }, 87 { "usb1-host", 0x01c19000, 4 * KiB }, 88 { "sid", 0x01c1b000, 4 * KiB }, 89 { "usb2-host", 0x01c1c000, 4 * KiB }, 90 { "cs1", 0x01c1d000, 4 * KiB }, 91 { "spi3", 0x01c1f000, 4 * KiB }, 92 { "rtc", 0x01c20400, 1 * KiB }, 93 { "pio", 0x01c20800, 1 * KiB }, 94 { "owa", 0x01c21000, 1 * KiB }, 95 { "ac97", 0x01c21400, 1 * KiB }, 96 { "cir0", 0x01c21800, 1 * KiB }, 97 { "cir1", 0x01c21c00, 1 * KiB }, 98 { "pcm0", 0x01c22000, 1 * KiB }, 99 { "pcm1", 0x01c22400, 1 * KiB }, 100 { "pcm2", 0x01c22800, 1 * KiB }, 101 { "audio", 0x01c22c00, 1 * KiB }, 102 { "keypad", 0x01c23000, 1 * KiB }, 103 { "pwm", 0x01c23400, 1 * KiB }, 104 { "keyadc", 0x01c24400, 1 * KiB }, 105 { "ths", 0x01c24c00, 1 * KiB }, 106 { "rtp", 0x01c25000, 1 * KiB }, 107 { "pmu", 0x01c25400, 1 * KiB }, 108 { "cpu-cfg", 0x01c25c00, 1 * KiB }, 109 { "uart0", 0x01c28000, 1 * KiB }, 110 { "uart1", 0x01c28400, 1 * KiB }, 111 { "uart2", 0x01c28800, 1 * KiB }, 112 { "uart3", 0x01c28c00, 1 * KiB }, 113 { "uart4", 0x01c29000, 1 * KiB }, 114 { "uart5", 0x01c29400, 1 * KiB }, 115 { "uart6", 0x01c29800, 1 * KiB }, 116 { "uart7", 0x01c29c00, 1 * KiB }, 117 { "ps20", 0x01c2a000, 1 * KiB }, 118 { "ps21", 0x01c2a400, 1 * KiB }, 119 { "twi1", 0x01c2b000, 1 * KiB }, 120 { "twi2", 0x01c2b400, 1 * KiB }, 121 { "twi3", 0x01c2b800, 1 * KiB }, 122 { "twi4", 0x01c2c000, 1 * KiB }, 123 { "scr", 0x01c2c400, 1 * KiB }, 124 { "tvd-top", 0x01c30000, 4 * KiB }, 125 { "tvd0", 0x01c31000, 4 * KiB }, 126 { "tvd1", 0x01c32000, 4 * KiB }, 127 { "tvd2", 0x01c33000, 4 * KiB }, 128 { "tvd3", 0x01c34000, 4 * KiB }, 129 { "gpu", 0x01c40000, 64 * KiB }, 130 { "gmac", 0x01c50000, 64 * KiB }, 131 { "hstmr", 0x01c60000, 4 * KiB }, 132 { "dram-com", 0x01c62000, 4 * KiB }, 133 { "dram-ctl", 0x01c63000, 4 * KiB }, 134 { "tcon-top", 0x01c70000, 4 * KiB }, 135 { "lcd0", 0x01c71000, 4 * KiB }, 136 { "lcd1", 0x01c72000, 4 * KiB }, 137 { "tv0", 0x01c73000, 4 * KiB }, 138 { "tv1", 0x01c74000, 4 * KiB }, 139 { "tve-top", 0x01c90000, 16 * KiB }, 140 { "tve0", 0x01c94000, 16 * KiB }, 141 { "tve1", 0x01c98000, 16 * KiB }, 142 { "mipi_dsi", 0x01ca0000, 4 * KiB }, 143 { "mipi_dphy", 0x01ca1000, 4 * KiB }, 144 { "ve", 0x01d00000, 1024 * KiB }, 145 { "mp", 0x01e80000, 128 * KiB }, 146 { "hdmi", 0x01ee0000, 128 * KiB }, 147 { "prcm", 0x01f01400, 1 * KiB }, 148 { "debug", 0x3f500000, 64 * KiB }, 149 { "cpubist", 0x3f501000, 4 * KiB }, 150 { "dcu", 0x3fff0000, 64 * KiB }, 151 { "hstmr", 0x01c60000, 4 * KiB }, 152 { "brom", 0xffff0000, 36 * KiB } 153 }; 154 155 /* Per Processor Interrupts */ 156 enum { 157 AW_R40_GIC_PPI_MAINT = 9, 158 AW_R40_GIC_PPI_HYPTIMER = 10, 159 AW_R40_GIC_PPI_VIRTTIMER = 11, 160 AW_R40_GIC_PPI_SECTIMER = 13, 161 AW_R40_GIC_PPI_PHYSTIMER = 14 162 }; 163 164 /* Shared Processor Interrupts */ 165 enum { 166 AW_R40_GIC_SPI_UART0 = 1, 167 AW_R40_GIC_SPI_UART1 = 2, 168 AW_R40_GIC_SPI_UART2 = 3, 169 AW_R40_GIC_SPI_UART3 = 4, 170 AW_R40_GIC_SPI_TWI0 = 7, 171 AW_R40_GIC_SPI_UART4 = 17, 172 AW_R40_GIC_SPI_UART5 = 18, 173 AW_R40_GIC_SPI_UART6 = 19, 174 AW_R40_GIC_SPI_UART7 = 20, 175 AW_R40_GIC_SPI_TIMER0 = 22, 176 AW_R40_GIC_SPI_TIMER1 = 23, 177 AW_R40_GIC_SPI_MMC0 = 32, 178 AW_R40_GIC_SPI_MMC1 = 33, 179 AW_R40_GIC_SPI_MMC2 = 34, 180 AW_R40_GIC_SPI_MMC3 = 35, 181 }; 182 183 /* Allwinner R40 general constants */ 184 enum { 185 AW_R40_GIC_NUM_SPI = 128 186 }; 187 188 #define BOOT0_MAGIC "eGON.BT0" 189 190 /* The low 8-bits of the 'boot_media' field in the SPL header */ 191 #define SUNXI_BOOTED_FROM_MMC0 0 192 #define SUNXI_BOOTED_FROM_NAND 1 193 #define SUNXI_BOOTED_FROM_MMC2 2 194 #define SUNXI_BOOTED_FROM_SPI 3 195 196 struct boot_file_head { 197 uint32_t b_instruction; 198 uint8_t magic[8]; 199 uint32_t check_sum; 200 uint32_t length; 201 uint32_t pub_head_size; 202 uint32_t fel_script_address; 203 uint32_t fel_uEnv_length; 204 uint32_t dt_name_offset; 205 uint32_t dram_size; 206 uint32_t boot_media; 207 uint32_t string_pool[13]; 208 }; 209 210 bool allwinner_r40_bootrom_setup(AwR40State *s, BlockBackend *blk, int unit) 211 { 212 const int64_t rom_size = 32 * KiB; 213 g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size); 214 struct boot_file_head *head = (struct boot_file_head *)buffer; 215 216 if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) { 217 error_setg(&error_fatal, "%s: failed to read BlockBackend data", 218 __func__); 219 return false; 220 } 221 222 /* we only check the magic string here. */ 223 if (memcmp(head->magic, BOOT0_MAGIC, sizeof(head->magic))) { 224 return false; 225 } 226 227 /* 228 * Simulate the behavior of the bootROM, it will change the boot_media 229 * flag to indicate where the chip is booting from. R40 can boot from 230 * mmc0 or mmc2, the default value of boot_media is zero 231 * (SUNXI_BOOTED_FROM_MMC0), let's fix this flag when it is booting from 232 * the others. 233 */ 234 if (unit == 2) { 235 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC2); 236 } else { 237 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC0); 238 } 239 240 rom_add_blob("allwinner-r40.bootrom", buffer, rom_size, 241 rom_size, s->memmap[AW_R40_DEV_SRAM_A1], 242 NULL, NULL, NULL, NULL, false); 243 return true; 244 } 245 246 static void allwinner_r40_init(Object *obj) 247 { 248 static const char *mmc_names[AW_R40_NUM_MMCS] = { 249 "mmc0", "mmc1", "mmc2", "mmc3" 250 }; 251 AwR40State *s = AW_R40(obj); 252 253 s->memmap = allwinner_r40_memmap; 254 255 for (int i = 0; i < AW_R40_NUM_CPUS; i++) { 256 object_initialize_child(obj, "cpu[*]", &s->cpus[i], 257 ARM_CPU_TYPE_NAME("cortex-a7")); 258 } 259 260 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); 261 262 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT); 263 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer), 264 "clk0-freq"); 265 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), 266 "clk1-freq"); 267 268 object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_R40_CCU); 269 270 for (int i = 0; i < AW_R40_NUM_MMCS; i++) { 271 object_initialize_child(obj, mmc_names[i], &s->mmc[i], 272 TYPE_AW_SDHOST_SUN5I); 273 } 274 275 object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I); 276 } 277 278 static void allwinner_r40_realize(DeviceState *dev, Error **errp) 279 { 280 AwR40State *s = AW_R40(dev); 281 unsigned i; 282 283 /* CPUs */ 284 for (i = 0; i < AW_R40_NUM_CPUS; i++) { 285 286 /* 287 * Disable secondary CPUs. Guest EL3 firmware will start 288 * them via CPU reset control registers. 289 */ 290 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", 291 i > 0); 292 293 /* All exception levels required */ 294 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true); 295 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true); 296 297 /* Mark realized */ 298 qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal); 299 } 300 301 /* Generic Interrupt Controller */ 302 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_R40_GIC_NUM_SPI + 303 GIC_INTERNAL); 304 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 305 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_R40_NUM_CPUS); 306 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false); 307 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true); 308 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal); 309 310 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_R40_DEV_GIC_DIST]); 311 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_R40_DEV_GIC_CPU]); 312 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_R40_DEV_GIC_HYP]); 313 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_R40_DEV_GIC_VCPU]); 314 315 /* 316 * Wire the outputs from each CPU's generic timer and the GICv2 317 * maintenance interrupt signal to the appropriate GIC PPI inputs, 318 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 319 */ 320 for (i = 0; i < AW_R40_NUM_CPUS; i++) { 321 DeviceState *cpudev = DEVICE(&s->cpus[i]); 322 int ppibase = AW_R40_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS; 323 int irq; 324 /* 325 * Mapping from the output timer irq lines from the CPU to the 326 * GIC PPI inputs used for this board. 327 */ 328 const int timer_irq[] = { 329 [GTIMER_PHYS] = AW_R40_GIC_PPI_PHYSTIMER, 330 [GTIMER_VIRT] = AW_R40_GIC_PPI_VIRTTIMER, 331 [GTIMER_HYP] = AW_R40_GIC_PPI_HYPTIMER, 332 [GTIMER_SEC] = AW_R40_GIC_PPI_SECTIMER, 333 }; 334 335 /* Connect CPU timer outputs to GIC PPI inputs */ 336 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 337 qdev_connect_gpio_out(cpudev, irq, 338 qdev_get_gpio_in(DEVICE(&s->gic), 339 ppibase + timer_irq[irq])); 340 } 341 342 /* Connect GIC outputs to CPU interrupt inputs */ 343 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 344 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 345 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_R40_NUM_CPUS, 346 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 347 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_R40_NUM_CPUS), 348 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 349 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_R40_NUM_CPUS), 350 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 351 352 /* GIC maintenance signal */ 353 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_R40_NUM_CPUS), 354 qdev_get_gpio_in(DEVICE(&s->gic), 355 ppibase + AW_R40_GIC_PPI_MAINT)); 356 } 357 358 /* Timer */ 359 sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal); 360 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_R40_DEV_PIT]); 361 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0, 362 qdev_get_gpio_in(DEVICE(&s->gic), 363 AW_R40_GIC_SPI_TIMER0)); 364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1, 365 qdev_get_gpio_in(DEVICE(&s->gic), 366 AW_R40_GIC_SPI_TIMER1)); 367 368 /* SRAM */ 369 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1", 370 16 * KiB, &error_abort); 371 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2", 372 16 * KiB, &error_abort); 373 memory_region_init_ram(&s->sram_a3, OBJECT(dev), "sram A3", 374 13 * KiB, &error_abort); 375 memory_region_init_ram(&s->sram_a4, OBJECT(dev), "sram A4", 376 3 * KiB, &error_abort); 377 memory_region_add_subregion(get_system_memory(), 378 s->memmap[AW_R40_DEV_SRAM_A1], &s->sram_a1); 379 memory_region_add_subregion(get_system_memory(), 380 s->memmap[AW_R40_DEV_SRAM_A2], &s->sram_a2); 381 memory_region_add_subregion(get_system_memory(), 382 s->memmap[AW_R40_DEV_SRAM_A3], &s->sram_a3); 383 memory_region_add_subregion(get_system_memory(), 384 s->memmap[AW_R40_DEV_SRAM_A4], &s->sram_a4); 385 386 /* Clock Control Unit */ 387 sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal); 388 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]); 389 390 /* SD/MMC */ 391 for (int i = 0; i < AW_R40_NUM_MMCS; i++) { 392 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->gic), 393 AW_R40_GIC_SPI_MMC0 + i); 394 const hwaddr addr = s->memmap[AW_R40_DEV_MMC0 + i]; 395 396 object_property_set_link(OBJECT(&s->mmc[i]), "dma-memory", 397 OBJECT(get_system_memory()), &error_fatal); 398 sysbus_realize(SYS_BUS_DEVICE(&s->mmc[i]), &error_fatal); 399 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc[i]), 0, addr); 400 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc[i]), 0, irq); 401 } 402 403 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */ 404 for (int i = 0; i < AW_R40_NUM_UARTS; i++) { 405 static const int uart_irqs[AW_R40_NUM_UARTS] = { 406 AW_R40_GIC_SPI_UART0, 407 AW_R40_GIC_SPI_UART1, 408 AW_R40_GIC_SPI_UART2, 409 AW_R40_GIC_SPI_UART3, 410 AW_R40_GIC_SPI_UART4, 411 AW_R40_GIC_SPI_UART5, 412 AW_R40_GIC_SPI_UART6, 413 AW_R40_GIC_SPI_UART7, 414 }; 415 const hwaddr addr = s->memmap[AW_R40_DEV_UART0 + i]; 416 417 serial_mm_init(get_system_memory(), addr, 2, 418 qdev_get_gpio_in(DEVICE(&s->gic), uart_irqs[i]), 419 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN); 420 } 421 422 /* I2C */ 423 sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal); 424 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_R40_DEV_TWI0]); 425 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, 426 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_TWI0)); 427 428 /* Unimplemented devices */ 429 for (i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) { 430 create_unimplemented_device(r40_unimplemented[i].device_name, 431 r40_unimplemented[i].base, 432 r40_unimplemented[i].size); 433 } 434 } 435 436 static void allwinner_r40_class_init(ObjectClass *oc, void *data) 437 { 438 DeviceClass *dc = DEVICE_CLASS(oc); 439 440 dc->realize = allwinner_r40_realize; 441 /* Reason: uses serial_hd() in realize function */ 442 dc->user_creatable = false; 443 } 444 445 static const TypeInfo allwinner_r40_type_info = { 446 .name = TYPE_AW_R40, 447 .parent = TYPE_DEVICE, 448 .instance_size = sizeof(AwR40State), 449 .instance_init = allwinner_r40_init, 450 .class_init = allwinner_r40_class_init, 451 }; 452 453 static void allwinner_r40_register_types(void) 454 { 455 type_register_static(&allwinner_r40_type_info); 456 } 457 458 type_init(allwinner_r40_register_types) 459