1 /* 2 * Allwinner R40/A40i/T3 System on Chip emulation 3 * 4 * Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/error-report.h" 23 #include "qemu/bswap.h" 24 #include "qemu/module.h" 25 #include "qemu/units.h" 26 #include "hw/boards.h" 27 #include "hw/qdev-core.h" 28 #include "hw/sysbus.h" 29 #include "hw/char/serial.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/usb/hcd-ehci.h" 32 #include "hw/loader.h" 33 #include "sysemu/sysemu.h" 34 #include "hw/arm/allwinner-r40.h" 35 #include "hw/misc/allwinner-r40-dramc.h" 36 37 /* Memory map */ 38 const hwaddr allwinner_r40_memmap[] = { 39 [AW_R40_DEV_SRAM_A1] = 0x00000000, 40 [AW_R40_DEV_SRAM_A2] = 0x00004000, 41 [AW_R40_DEV_SRAM_A3] = 0x00008000, 42 [AW_R40_DEV_SRAM_A4] = 0x0000b400, 43 [AW_R40_DEV_SRAMC] = 0x01c00000, 44 [AW_R40_DEV_EMAC] = 0x01c0b000, 45 [AW_R40_DEV_MMC0] = 0x01c0f000, 46 [AW_R40_DEV_MMC1] = 0x01c10000, 47 [AW_R40_DEV_MMC2] = 0x01c11000, 48 [AW_R40_DEV_MMC3] = 0x01c12000, 49 [AW_R40_DEV_AHCI] = 0x01c18000, 50 [AW_R40_DEV_EHCI1] = 0x01c19000, 51 [AW_R40_DEV_OHCI1] = 0x01c19400, 52 [AW_R40_DEV_EHCI2] = 0x01c1c000, 53 [AW_R40_DEV_OHCI2] = 0x01c1c400, 54 [AW_R40_DEV_CCU] = 0x01c20000, 55 [AW_R40_DEV_PIT] = 0x01c20c00, 56 [AW_R40_DEV_UART0] = 0x01c28000, 57 [AW_R40_DEV_UART1] = 0x01c28400, 58 [AW_R40_DEV_UART2] = 0x01c28800, 59 [AW_R40_DEV_UART3] = 0x01c28c00, 60 [AW_R40_DEV_UART4] = 0x01c29000, 61 [AW_R40_DEV_UART5] = 0x01c29400, 62 [AW_R40_DEV_UART6] = 0x01c29800, 63 [AW_R40_DEV_UART7] = 0x01c29c00, 64 [AW_R40_DEV_TWI0] = 0x01c2ac00, 65 [AW_R40_DEV_GMAC] = 0x01c50000, 66 [AW_R40_DEV_DRAMCOM] = 0x01c62000, 67 [AW_R40_DEV_DRAMCTL] = 0x01c63000, 68 [AW_R40_DEV_DRAMPHY] = 0x01c65000, 69 [AW_R40_DEV_GIC_DIST] = 0x01c81000, 70 [AW_R40_DEV_GIC_CPU] = 0x01c82000, 71 [AW_R40_DEV_GIC_HYP] = 0x01c84000, 72 [AW_R40_DEV_GIC_VCPU] = 0x01c86000, 73 [AW_R40_DEV_SDRAM] = 0x40000000 74 }; 75 76 /* List of unimplemented devices */ 77 struct AwR40Unimplemented { 78 const char *device_name; 79 hwaddr base; 80 hwaddr size; 81 }; 82 83 static struct AwR40Unimplemented r40_unimplemented[] = { 84 { "d-engine", 0x01000000, 4 * MiB }, 85 { "d-inter", 0x01400000, 128 * KiB }, 86 { "dma", 0x01c02000, 4 * KiB }, 87 { "nfdc", 0x01c03000, 4 * KiB }, 88 { "ts", 0x01c04000, 4 * KiB }, 89 { "spi0", 0x01c05000, 4 * KiB }, 90 { "spi1", 0x01c06000, 4 * KiB }, 91 { "cs0", 0x01c09000, 4 * KiB }, 92 { "keymem", 0x01c0a000, 4 * KiB }, 93 { "usb0-otg", 0x01c13000, 4 * KiB }, 94 { "usb0-host", 0x01c14000, 4 * KiB }, 95 { "crypto", 0x01c15000, 4 * KiB }, 96 { "spi2", 0x01c17000, 4 * KiB }, 97 { "usb1-phy", 0x01c19800, 2 * KiB }, 98 { "sid", 0x01c1b000, 4 * KiB }, 99 { "usb2-phy", 0x01c1c800, 2 * KiB }, 100 { "cs1", 0x01c1d000, 4 * KiB }, 101 { "spi3", 0x01c1f000, 4 * KiB }, 102 { "rtc", 0x01c20400, 1 * KiB }, 103 { "pio", 0x01c20800, 1 * KiB }, 104 { "owa", 0x01c21000, 1 * KiB }, 105 { "ac97", 0x01c21400, 1 * KiB }, 106 { "cir0", 0x01c21800, 1 * KiB }, 107 { "cir1", 0x01c21c00, 1 * KiB }, 108 { "pcm0", 0x01c22000, 1 * KiB }, 109 { "pcm1", 0x01c22400, 1 * KiB }, 110 { "pcm2", 0x01c22800, 1 * KiB }, 111 { "audio", 0x01c22c00, 1 * KiB }, 112 { "keypad", 0x01c23000, 1 * KiB }, 113 { "pwm", 0x01c23400, 1 * KiB }, 114 { "keyadc", 0x01c24400, 1 * KiB }, 115 { "ths", 0x01c24c00, 1 * KiB }, 116 { "rtp", 0x01c25000, 1 * KiB }, 117 { "pmu", 0x01c25400, 1 * KiB }, 118 { "cpu-cfg", 0x01c25c00, 1 * KiB }, 119 { "uart0", 0x01c28000, 1 * KiB }, 120 { "uart1", 0x01c28400, 1 * KiB }, 121 { "uart2", 0x01c28800, 1 * KiB }, 122 { "uart3", 0x01c28c00, 1 * KiB }, 123 { "uart4", 0x01c29000, 1 * KiB }, 124 { "uart5", 0x01c29400, 1 * KiB }, 125 { "uart6", 0x01c29800, 1 * KiB }, 126 { "uart7", 0x01c29c00, 1 * KiB }, 127 { "ps20", 0x01c2a000, 1 * KiB }, 128 { "ps21", 0x01c2a400, 1 * KiB }, 129 { "twi1", 0x01c2b000, 1 * KiB }, 130 { "twi2", 0x01c2b400, 1 * KiB }, 131 { "twi3", 0x01c2b800, 1 * KiB }, 132 { "twi4", 0x01c2c000, 1 * KiB }, 133 { "scr", 0x01c2c400, 1 * KiB }, 134 { "tvd-top", 0x01c30000, 4 * KiB }, 135 { "tvd0", 0x01c31000, 4 * KiB }, 136 { "tvd1", 0x01c32000, 4 * KiB }, 137 { "tvd2", 0x01c33000, 4 * KiB }, 138 { "tvd3", 0x01c34000, 4 * KiB }, 139 { "gpu", 0x01c40000, 64 * KiB }, 140 { "hstmr", 0x01c60000, 4 * KiB }, 141 { "tcon-top", 0x01c70000, 4 * KiB }, 142 { "lcd0", 0x01c71000, 4 * KiB }, 143 { "lcd1", 0x01c72000, 4 * KiB }, 144 { "tv0", 0x01c73000, 4 * KiB }, 145 { "tv1", 0x01c74000, 4 * KiB }, 146 { "tve-top", 0x01c90000, 16 * KiB }, 147 { "tve0", 0x01c94000, 16 * KiB }, 148 { "tve1", 0x01c98000, 16 * KiB }, 149 { "mipi_dsi", 0x01ca0000, 4 * KiB }, 150 { "mipi_dphy", 0x01ca1000, 4 * KiB }, 151 { "ve", 0x01d00000, 1024 * KiB }, 152 { "mp", 0x01e80000, 128 * KiB }, 153 { "hdmi", 0x01ee0000, 128 * KiB }, 154 { "prcm", 0x01f01400, 1 * KiB }, 155 { "debug", 0x3f500000, 64 * KiB }, 156 { "cpubist", 0x3f501000, 4 * KiB }, 157 { "dcu", 0x3fff0000, 64 * KiB }, 158 { "hstmr", 0x01c60000, 4 * KiB }, 159 { "brom", 0xffff0000, 36 * KiB } 160 }; 161 162 /* Per Processor Interrupts */ 163 enum { 164 AW_R40_GIC_PPI_MAINT = 9, 165 AW_R40_GIC_PPI_HYPTIMER = 10, 166 AW_R40_GIC_PPI_VIRTTIMER = 11, 167 AW_R40_GIC_PPI_SECTIMER = 13, 168 AW_R40_GIC_PPI_PHYSTIMER = 14 169 }; 170 171 /* Shared Processor Interrupts */ 172 enum { 173 AW_R40_GIC_SPI_UART0 = 1, 174 AW_R40_GIC_SPI_UART1 = 2, 175 AW_R40_GIC_SPI_UART2 = 3, 176 AW_R40_GIC_SPI_UART3 = 4, 177 AW_R40_GIC_SPI_TWI0 = 7, 178 AW_R40_GIC_SPI_UART4 = 17, 179 AW_R40_GIC_SPI_UART5 = 18, 180 AW_R40_GIC_SPI_UART6 = 19, 181 AW_R40_GIC_SPI_UART7 = 20, 182 AW_R40_GIC_SPI_TIMER0 = 22, 183 AW_R40_GIC_SPI_TIMER1 = 23, 184 AW_R40_GIC_SPI_MMC0 = 32, 185 AW_R40_GIC_SPI_MMC1 = 33, 186 AW_R40_GIC_SPI_MMC2 = 34, 187 AW_R40_GIC_SPI_MMC3 = 35, 188 AW_R40_GIC_SPI_EMAC = 55, 189 AW_R40_GIC_SPI_AHCI = 56, 190 AW_R40_GIC_SPI_OHCI1 = 64, 191 AW_R40_GIC_SPI_OHCI2 = 65, 192 AW_R40_GIC_SPI_EHCI1 = 76, 193 AW_R40_GIC_SPI_EHCI2 = 78, 194 AW_R40_GIC_SPI_GMAC = 85, 195 }; 196 197 /* Allwinner R40 general constants */ 198 enum { 199 AW_R40_GIC_NUM_SPI = 128 200 }; 201 202 #define BOOT0_MAGIC "eGON.BT0" 203 204 /* The low 8-bits of the 'boot_media' field in the SPL header */ 205 #define SUNXI_BOOTED_FROM_MMC0 0 206 #define SUNXI_BOOTED_FROM_NAND 1 207 #define SUNXI_BOOTED_FROM_MMC2 2 208 #define SUNXI_BOOTED_FROM_SPI 3 209 210 struct boot_file_head { 211 uint32_t b_instruction; 212 uint8_t magic[8]; 213 uint32_t check_sum; 214 uint32_t length; 215 uint32_t pub_head_size; 216 uint32_t fel_script_address; 217 uint32_t fel_uEnv_length; 218 uint32_t dt_name_offset; 219 uint32_t dram_size; 220 uint32_t boot_media; 221 uint32_t string_pool[13]; 222 }; 223 224 bool allwinner_r40_bootrom_setup(AwR40State *s, BlockBackend *blk, int unit) 225 { 226 const int64_t rom_size = 32 * KiB; 227 g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size); 228 struct boot_file_head *head = (struct boot_file_head *)buffer; 229 230 if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) { 231 error_setg(&error_fatal, "%s: failed to read BlockBackend data", 232 __func__); 233 return false; 234 } 235 236 /* we only check the magic string here. */ 237 if (memcmp(head->magic, BOOT0_MAGIC, sizeof(head->magic))) { 238 return false; 239 } 240 241 /* 242 * Simulate the behavior of the bootROM, it will change the boot_media 243 * flag to indicate where the chip is booting from. R40 can boot from 244 * mmc0 or mmc2, the default value of boot_media is zero 245 * (SUNXI_BOOTED_FROM_MMC0), let's fix this flag when it is booting from 246 * the others. 247 */ 248 if (unit == 2) { 249 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC2); 250 } else { 251 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC0); 252 } 253 254 rom_add_blob("allwinner-r40.bootrom", buffer, rom_size, 255 rom_size, s->memmap[AW_R40_DEV_SRAM_A1], 256 NULL, NULL, NULL, NULL, false); 257 return true; 258 } 259 260 static void allwinner_r40_init(Object *obj) 261 { 262 static const char *mmc_names[AW_R40_NUM_MMCS] = { 263 "mmc0", "mmc1", "mmc2", "mmc3" 264 }; 265 AwR40State *s = AW_R40(obj); 266 267 s->memmap = allwinner_r40_memmap; 268 269 for (int i = 0; i < AW_R40_NUM_CPUS; i++) { 270 object_initialize_child(obj, "cpu[*]", &s->cpus[i], 271 ARM_CPU_TYPE_NAME("cortex-a7")); 272 } 273 274 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); 275 276 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT); 277 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer), 278 "clk0-freq"); 279 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), 280 "clk1-freq"); 281 282 object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_R40_CCU); 283 284 for (int i = 0; i < AW_R40_NUM_MMCS; i++) { 285 object_initialize_child(obj, mmc_names[i], &s->mmc[i], 286 TYPE_AW_SDHOST_SUN50I_A64); 287 } 288 289 object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI); 290 291 for (size_t i = 0; i < AW_R40_NUM_USB; i++) { 292 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 293 TYPE_PLATFORM_EHCI); 294 object_initialize_child(obj, "ohci[*]", &s->ohci[i], 295 TYPE_SYSBUS_OHCI); 296 } 297 298 object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I); 299 300 object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC); 301 object_initialize_child(obj, "gmac", &s->gmac, TYPE_AW_SUN8I_EMAC); 302 object_property_add_alias(obj, "gmac-phy-addr", 303 OBJECT(&s->gmac), "phy-addr"); 304 305 object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_R40_DRAMC); 306 object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc), 307 "ram-addr"); 308 object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc), 309 "ram-size"); 310 311 object_initialize_child(obj, "sramc", &s->sramc, TYPE_AW_SRAMC_SUN8I_R40); 312 } 313 314 static void allwinner_r40_realize(DeviceState *dev, Error **errp) 315 { 316 const char *r40_nic_models[] = { "gmac", "emac", NULL }; 317 AwR40State *s = AW_R40(dev); 318 319 /* CPUs */ 320 for (unsigned i = 0; i < AW_R40_NUM_CPUS; i++) { 321 322 /* 323 * Disable secondary CPUs. Guest EL3 firmware will start 324 * them via CPU reset control registers. 325 */ 326 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", 327 i > 0); 328 329 /* All exception levels required */ 330 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true); 331 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true); 332 333 /* Mark realized */ 334 qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal); 335 } 336 337 /* Generic Interrupt Controller */ 338 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_R40_GIC_NUM_SPI + 339 GIC_INTERNAL); 340 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 341 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_R40_NUM_CPUS); 342 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false); 343 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true); 344 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal); 345 346 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_R40_DEV_GIC_DIST]); 347 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_R40_DEV_GIC_CPU]); 348 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_R40_DEV_GIC_HYP]); 349 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_R40_DEV_GIC_VCPU]); 350 351 /* 352 * Wire the outputs from each CPU's generic timer and the GICv2 353 * maintenance interrupt signal to the appropriate GIC PPI inputs, 354 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 355 */ 356 for (unsigned i = 0; i < AW_R40_NUM_CPUS; i++) { 357 DeviceState *cpudev = DEVICE(&s->cpus[i]); 358 int ppibase = AW_R40_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS; 359 int irq; 360 /* 361 * Mapping from the output timer irq lines from the CPU to the 362 * GIC PPI inputs used for this board. 363 */ 364 const int timer_irq[] = { 365 [GTIMER_PHYS] = AW_R40_GIC_PPI_PHYSTIMER, 366 [GTIMER_VIRT] = AW_R40_GIC_PPI_VIRTTIMER, 367 [GTIMER_HYP] = AW_R40_GIC_PPI_HYPTIMER, 368 [GTIMER_SEC] = AW_R40_GIC_PPI_SECTIMER, 369 }; 370 371 /* Connect CPU timer outputs to GIC PPI inputs */ 372 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 373 qdev_connect_gpio_out(cpudev, irq, 374 qdev_get_gpio_in(DEVICE(&s->gic), 375 ppibase + timer_irq[irq])); 376 } 377 378 /* Connect GIC outputs to CPU interrupt inputs */ 379 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 380 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 381 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_R40_NUM_CPUS, 382 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 383 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_R40_NUM_CPUS), 384 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 385 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_R40_NUM_CPUS), 386 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 387 388 /* GIC maintenance signal */ 389 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_R40_NUM_CPUS), 390 qdev_get_gpio_in(DEVICE(&s->gic), 391 ppibase + AW_R40_GIC_PPI_MAINT)); 392 } 393 394 /* Timer */ 395 sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal); 396 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_R40_DEV_PIT]); 397 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0, 398 qdev_get_gpio_in(DEVICE(&s->gic), 399 AW_R40_GIC_SPI_TIMER0)); 400 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1, 401 qdev_get_gpio_in(DEVICE(&s->gic), 402 AW_R40_GIC_SPI_TIMER1)); 403 404 /* SRAM */ 405 sysbus_realize(SYS_BUS_DEVICE(&s->sramc), &error_fatal); 406 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sramc), 0, s->memmap[AW_R40_DEV_SRAMC]); 407 408 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1", 409 16 * KiB, &error_abort); 410 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2", 411 16 * KiB, &error_abort); 412 memory_region_init_ram(&s->sram_a3, OBJECT(dev), "sram A3", 413 13 * KiB, &error_abort); 414 memory_region_init_ram(&s->sram_a4, OBJECT(dev), "sram A4", 415 3 * KiB, &error_abort); 416 memory_region_add_subregion(get_system_memory(), 417 s->memmap[AW_R40_DEV_SRAM_A1], &s->sram_a1); 418 memory_region_add_subregion(get_system_memory(), 419 s->memmap[AW_R40_DEV_SRAM_A2], &s->sram_a2); 420 memory_region_add_subregion(get_system_memory(), 421 s->memmap[AW_R40_DEV_SRAM_A3], &s->sram_a3); 422 memory_region_add_subregion(get_system_memory(), 423 s->memmap[AW_R40_DEV_SRAM_A4], &s->sram_a4); 424 425 /* Clock Control Unit */ 426 sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal); 427 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]); 428 429 /* SATA / AHCI */ 430 sysbus_realize(SYS_BUS_DEVICE(&s->sata), &error_fatal); 431 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, 432 allwinner_r40_memmap[AW_R40_DEV_AHCI]); 433 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, 434 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_AHCI)); 435 436 /* USB */ 437 for (size_t i = 0; i < AW_R40_NUM_USB; i++) { 438 g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i); 439 440 object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", true, 441 &error_fatal); 442 sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal); 443 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 444 allwinner_r40_memmap[i ? AW_R40_DEV_EHCI2 445 : AW_R40_DEV_EHCI1]); 446 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 447 qdev_get_gpio_in(DEVICE(&s->gic), 448 i ? AW_R40_GIC_SPI_EHCI2 449 : AW_R40_GIC_SPI_EHCI1)); 450 451 object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus, 452 &error_fatal); 453 sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal); 454 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, 455 allwinner_r40_memmap[i ? AW_R40_DEV_OHCI2 456 : AW_R40_DEV_OHCI1]); 457 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0, 458 qdev_get_gpio_in(DEVICE(&s->gic), 459 i ? AW_R40_GIC_SPI_OHCI2 460 : AW_R40_GIC_SPI_OHCI1)); 461 } 462 463 /* SD/MMC */ 464 for (int i = 0; i < AW_R40_NUM_MMCS; i++) { 465 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->gic), 466 AW_R40_GIC_SPI_MMC0 + i); 467 const hwaddr addr = s->memmap[AW_R40_DEV_MMC0 + i]; 468 469 object_property_set_link(OBJECT(&s->mmc[i]), "dma-memory", 470 OBJECT(get_system_memory()), &error_fatal); 471 sysbus_realize(SYS_BUS_DEVICE(&s->mmc[i]), &error_fatal); 472 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc[i]), 0, addr); 473 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc[i]), 0, irq); 474 } 475 476 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */ 477 for (int i = 0; i < AW_R40_NUM_UARTS; i++) { 478 static const int uart_irqs[AW_R40_NUM_UARTS] = { 479 AW_R40_GIC_SPI_UART0, 480 AW_R40_GIC_SPI_UART1, 481 AW_R40_GIC_SPI_UART2, 482 AW_R40_GIC_SPI_UART3, 483 AW_R40_GIC_SPI_UART4, 484 AW_R40_GIC_SPI_UART5, 485 AW_R40_GIC_SPI_UART6, 486 AW_R40_GIC_SPI_UART7, 487 }; 488 const hwaddr addr = s->memmap[AW_R40_DEV_UART0 + i]; 489 490 serial_mm_init(get_system_memory(), addr, 2, 491 qdev_get_gpio_in(DEVICE(&s->gic), uart_irqs[i]), 492 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN); 493 } 494 495 /* I2C */ 496 sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal); 497 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_R40_DEV_TWI0]); 498 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, 499 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_TWI0)); 500 501 /* DRAMC */ 502 sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal); 503 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, 504 s->memmap[AW_R40_DEV_DRAMCOM]); 505 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, 506 s->memmap[AW_R40_DEV_DRAMCTL]); 507 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, 508 s->memmap[AW_R40_DEV_DRAMPHY]); 509 510 /* nic support gmac and emac */ 511 for (int i = 0; i < ARRAY_SIZE(r40_nic_models) - 1; i++) { 512 NICInfo *nic = &nd_table[i]; 513 514 if (!nic->used) { 515 continue; 516 } 517 if (qemu_show_nic_models(nic->model, r40_nic_models)) { 518 exit(0); 519 } 520 521 switch (qemu_find_nic_model(nic, r40_nic_models, r40_nic_models[0])) { 522 case 0: /* gmac */ 523 qdev_set_nic_properties(DEVICE(&s->gmac), nic); 524 break; 525 case 1: /* emac */ 526 qdev_set_nic_properties(DEVICE(&s->emac), nic); 527 break; 528 default: 529 exit(1); 530 break; 531 } 532 } 533 534 /* GMAC */ 535 object_property_set_link(OBJECT(&s->gmac), "dma-memory", 536 OBJECT(get_system_memory()), &error_fatal); 537 sysbus_realize(SYS_BUS_DEVICE(&s->gmac), &error_fatal); 538 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gmac), 0, s->memmap[AW_R40_DEV_GMAC]); 539 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gmac), 0, 540 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_GMAC)); 541 542 /* EMAC */ 543 sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal); 544 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_R40_DEV_EMAC]); 545 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0, 546 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_EMAC)); 547 548 /* Unimplemented devices */ 549 for (unsigned i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) { 550 create_unimplemented_device(r40_unimplemented[i].device_name, 551 r40_unimplemented[i].base, 552 r40_unimplemented[i].size); 553 } 554 } 555 556 static void allwinner_r40_class_init(ObjectClass *oc, void *data) 557 { 558 DeviceClass *dc = DEVICE_CLASS(oc); 559 560 dc->realize = allwinner_r40_realize; 561 /* Reason: uses serial_hd() in realize function */ 562 dc->user_creatable = false; 563 } 564 565 static const TypeInfo allwinner_r40_type_info = { 566 .name = TYPE_AW_R40, 567 .parent = TYPE_DEVICE, 568 .instance_size = sizeof(AwR40State), 569 .instance_init = allwinner_r40_init, 570 .class_init = allwinner_r40_class_init, 571 }; 572 573 static void allwinner_r40_register_types(void) 574 { 575 type_register_static(&allwinner_r40_type_info); 576 } 577 578 type_init(allwinner_r40_register_types) 579