1 /* 2 * Allwinner A10 SoC emulation 3 * 4 * Copyright (C) 2013 Li Guang 5 * Written by Li Guang <lig.fnst@cn.fujitsu.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "exec/address-spaces.h" 20 #include "qapi/error.h" 21 #include "qemu/module.h" 22 #include "cpu.h" 23 #include "hw/sysbus.h" 24 #include "hw/arm/allwinner-a10.h" 25 #include "hw/misc/unimp.h" 26 #include "sysemu/sysemu.h" 27 28 #define AW_A10_PIC_REG_BASE 0x01c20400 29 #define AW_A10_PIT_REG_BASE 0x01c20c00 30 #define AW_A10_UART0_REG_BASE 0x01c28000 31 #define AW_A10_EMAC_BASE 0x01c0b000 32 #define AW_A10_SATA_BASE 0x01c18000 33 34 static void aw_a10_init(Object *obj) 35 { 36 AwA10State *s = AW_A10(obj); 37 38 object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), 39 ARM_CPU_TYPE_NAME("cortex-a8"), 40 &error_abort, NULL); 41 42 sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc), 43 TYPE_AW_A10_PIC); 44 45 sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), 46 TYPE_AW_A10_PIT); 47 48 sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), TYPE_AW_EMAC); 49 50 sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata), 51 TYPE_ALLWINNER_AHCI); 52 } 53 54 static void aw_a10_realize(DeviceState *dev, Error **errp) 55 { 56 AwA10State *s = AW_A10(dev); 57 SysBusDevice *sysbusdev; 58 qemu_irq fiq, irq; 59 Error *err = NULL; 60 61 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 62 if (err != NULL) { 63 error_propagate(errp, err); 64 return; 65 } 66 irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ); 67 fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ); 68 69 object_property_set_bool(OBJECT(&s->intc), true, "realized", &err); 70 if (err != NULL) { 71 error_propagate(errp, err); 72 return; 73 } 74 sysbusdev = SYS_BUS_DEVICE(&s->intc); 75 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE); 76 sysbus_connect_irq(sysbusdev, 0, irq); 77 sysbus_connect_irq(sysbusdev, 1, fiq); 78 qdev_pass_gpios(DEVICE(&s->intc), dev, NULL); 79 80 object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); 81 if (err != NULL) { 82 error_propagate(errp, err); 83 return; 84 } 85 sysbusdev = SYS_BUS_DEVICE(&s->timer); 86 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE); 87 sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22)); 88 sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23)); 89 sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24)); 90 sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25)); 91 sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67)); 92 sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68)); 93 94 memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB, 95 &error_fatal); 96 memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a); 97 create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB); 98 99 /* FIXME use qdev NIC properties instead of nd_table[] */ 100 if (nd_table[0].used) { 101 qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); 102 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); 103 } 104 object_property_set_bool(OBJECT(&s->emac), true, "realized", &err); 105 if (err != NULL) { 106 error_propagate(errp, err); 107 return; 108 } 109 sysbusdev = SYS_BUS_DEVICE(&s->emac); 110 sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE); 111 sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55)); 112 113 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 114 if (err) { 115 error_propagate(errp, err); 116 return; 117 } 118 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE); 119 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56)); 120 121 /* FIXME use a qdev chardev prop instead of serial_hd() */ 122 serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, 123 qdev_get_gpio_in(dev, 1), 124 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 125 } 126 127 static void aw_a10_class_init(ObjectClass *oc, void *data) 128 { 129 DeviceClass *dc = DEVICE_CLASS(oc); 130 131 dc->realize = aw_a10_realize; 132 /* Reason: Uses serial_hds and nd_table in realize function */ 133 dc->user_creatable = false; 134 } 135 136 static const TypeInfo aw_a10_type_info = { 137 .name = TYPE_AW_A10, 138 .parent = TYPE_DEVICE, 139 .instance_size = sizeof(AwA10State), 140 .instance_init = aw_a10_init, 141 .class_init = aw_a10_class_init, 142 }; 143 144 static void aw_a10_register_types(void) 145 { 146 type_register_static(&aw_a10_type_info); 147 } 148 149 type_init(aw_a10_register_types) 150