1 /* 2 * Allwinner A10 SoC emulation 3 * 4 * Copyright (C) 2013 Li Guang 5 * Written by Li Guang <lig.fnst@cn.fujitsu.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "exec/address-spaces.h" 20 #include "qapi/error.h" 21 #include "qemu/module.h" 22 #include "cpu.h" 23 #include "hw/sysbus.h" 24 #include "hw/arm/allwinner-a10.h" 25 #include "hw/misc/unimp.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/boards.h" 28 #include "hw/usb/hcd-ohci.h" 29 30 #define AW_A10_MMC0_BASE 0x01c0f000 31 #define AW_A10_PIC_REG_BASE 0x01c20400 32 #define AW_A10_PIT_REG_BASE 0x01c20c00 33 #define AW_A10_UART0_REG_BASE 0x01c28000 34 #define AW_A10_EMAC_BASE 0x01c0b000 35 #define AW_A10_EHCI_BASE 0x01c14000 36 #define AW_A10_OHCI_BASE 0x01c14400 37 #define AW_A10_SATA_BASE 0x01c18000 38 #define AW_A10_RTC_BASE 0x01c20d00 39 40 static void aw_a10_init(Object *obj) 41 { 42 AwA10State *s = AW_A10(obj); 43 44 object_initialize_child(obj, "cpu", &s->cpu, 45 ARM_CPU_TYPE_NAME("cortex-a8")); 46 47 sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc), 48 TYPE_AW_A10_PIC); 49 50 sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), 51 TYPE_AW_A10_PIT); 52 53 sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), TYPE_AW_EMAC); 54 55 sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata), 56 TYPE_ALLWINNER_AHCI); 57 58 if (machine_usb(current_machine)) { 59 int i; 60 61 for (i = 0; i < AW_A10_NUM_USB; i++) { 62 sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]), 63 sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI); 64 sysbus_init_child_obj(obj, "ohci[*]", OBJECT(&s->ohci[i]), 65 sizeof(s->ohci[i]), TYPE_SYSBUS_OHCI); 66 } 67 } 68 69 sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), 70 TYPE_AW_SDHOST_SUN4I); 71 72 sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc), 73 TYPE_AW_RTC_SUN4I); 74 } 75 76 static void aw_a10_realize(DeviceState *dev, Error **errp) 77 { 78 AwA10State *s = AW_A10(dev); 79 SysBusDevice *sysbusdev; 80 Error *err = NULL; 81 82 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 83 if (err != NULL) { 84 error_propagate(errp, err); 85 return; 86 } 87 88 object_property_set_bool(OBJECT(&s->intc), true, "realized", &err); 89 if (err != NULL) { 90 error_propagate(errp, err); 91 return; 92 } 93 sysbusdev = SYS_BUS_DEVICE(&s->intc); 94 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE); 95 sysbus_connect_irq(sysbusdev, 0, 96 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 97 sysbus_connect_irq(sysbusdev, 1, 98 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 99 qdev_pass_gpios(DEVICE(&s->intc), dev, NULL); 100 101 object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); 102 if (err != NULL) { 103 error_propagate(errp, err); 104 return; 105 } 106 sysbusdev = SYS_BUS_DEVICE(&s->timer); 107 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE); 108 sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22)); 109 sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23)); 110 sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24)); 111 sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25)); 112 sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67)); 113 sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68)); 114 115 memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB, 116 &error_fatal); 117 memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a); 118 create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB); 119 120 /* FIXME use qdev NIC properties instead of nd_table[] */ 121 if (nd_table[0].used) { 122 qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); 123 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); 124 } 125 object_property_set_bool(OBJECT(&s->emac), true, "realized", &err); 126 if (err != NULL) { 127 error_propagate(errp, err); 128 return; 129 } 130 sysbusdev = SYS_BUS_DEVICE(&s->emac); 131 sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE); 132 sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55)); 133 134 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 135 if (err) { 136 error_propagate(errp, err); 137 return; 138 } 139 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE); 140 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56)); 141 142 /* FIXME use a qdev chardev prop instead of serial_hd() */ 143 serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, 144 qdev_get_gpio_in(dev, 1), 145 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 146 147 if (machine_usb(current_machine)) { 148 int i; 149 150 for (i = 0; i < AW_A10_NUM_USB; i++) { 151 char bus[16]; 152 153 sprintf(bus, "usb-bus.%d", i); 154 155 object_property_set_bool(OBJECT(&s->ehci[i]), true, 156 "companion-enable", &error_fatal); 157 object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", 158 &error_fatal); 159 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 160 AW_A10_EHCI_BASE + i * 0x8000); 161 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 162 qdev_get_gpio_in(dev, 39 + i)); 163 164 object_property_set_str(OBJECT(&s->ohci[i]), bus, "masterbus", 165 &error_fatal); 166 object_property_set_bool(OBJECT(&s->ohci[i]), true, "realized", 167 &error_fatal); 168 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, 169 AW_A10_OHCI_BASE + i * 0x8000); 170 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0, 171 qdev_get_gpio_in(dev, 64 + i)); 172 } 173 } 174 175 /* SD/MMC */ 176 qdev_init_nofail(DEVICE(&s->mmc0)); 177 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE); 178 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32)); 179 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), 180 "sd-bus"); 181 182 /* RTC */ 183 qdev_init_nofail(DEVICE(&s->rtc)); 184 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10); 185 } 186 187 static void aw_a10_class_init(ObjectClass *oc, void *data) 188 { 189 DeviceClass *dc = DEVICE_CLASS(oc); 190 191 dc->realize = aw_a10_realize; 192 /* Reason: Uses serial_hds and nd_table in realize function */ 193 dc->user_creatable = false; 194 } 195 196 static const TypeInfo aw_a10_type_info = { 197 .name = TYPE_AW_A10, 198 .parent = TYPE_DEVICE, 199 .instance_size = sizeof(AwA10State), 200 .instance_init = aw_a10_init, 201 .class_init = aw_a10_class_init, 202 }; 203 204 static void aw_a10_register_types(void) 205 { 206 type_register_static(&aw_a10_type_info); 207 } 208 209 type_init(aw_a10_register_types) 210