1 /* 2 * Allwinner A10 SoC emulation 3 * 4 * Copyright (C) 2013 Li Guang 5 * Written by Li Guang <lig.fnst@cn.fujitsu.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "exec/address-spaces.h" 20 #include "qapi/error.h" 21 #include "qemu/module.h" 22 #include "cpu.h" 23 #include "hw/sysbus.h" 24 #include "hw/arm/allwinner-a10.h" 25 #include "hw/misc/unimp.h" 26 #include "sysemu/sysemu.h" 27 28 #define AW_A10_PIC_REG_BASE 0x01c20400 29 #define AW_A10_PIT_REG_BASE 0x01c20c00 30 #define AW_A10_UART0_REG_BASE 0x01c28000 31 #define AW_A10_EMAC_BASE 0x01c0b000 32 #define AW_A10_SATA_BASE 0x01c18000 33 34 static void aw_a10_init(Object *obj) 35 { 36 AwA10State *s = AW_A10(obj); 37 38 object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), 39 ARM_CPU_TYPE_NAME("cortex-a8"), 40 &error_abort, NULL); 41 42 sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc), 43 TYPE_AW_A10_PIC); 44 45 sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), 46 TYPE_AW_A10_PIT); 47 48 sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), TYPE_AW_EMAC); 49 50 sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata), 51 TYPE_ALLWINNER_AHCI); 52 } 53 54 static void aw_a10_realize(DeviceState *dev, Error **errp) 55 { 56 AwA10State *s = AW_A10(dev); 57 SysBusDevice *sysbusdev; 58 uint8_t i; 59 qemu_irq fiq, irq; 60 Error *err = NULL; 61 62 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 63 if (err != NULL) { 64 error_propagate(errp, err); 65 return; 66 } 67 irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ); 68 fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ); 69 70 object_property_set_bool(OBJECT(&s->intc), true, "realized", &err); 71 if (err != NULL) { 72 error_propagate(errp, err); 73 return; 74 } 75 sysbusdev = SYS_BUS_DEVICE(&s->intc); 76 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE); 77 sysbus_connect_irq(sysbusdev, 0, irq); 78 sysbus_connect_irq(sysbusdev, 1, fiq); 79 for (i = 0; i < AW_A10_PIC_INT_NR; i++) { 80 s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i); 81 } 82 83 object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); 84 if (err != NULL) { 85 error_propagate(errp, err); 86 return; 87 } 88 sysbusdev = SYS_BUS_DEVICE(&s->timer); 89 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE); 90 sysbus_connect_irq(sysbusdev, 0, s->irq[22]); 91 sysbus_connect_irq(sysbusdev, 1, s->irq[23]); 92 sysbus_connect_irq(sysbusdev, 2, s->irq[24]); 93 sysbus_connect_irq(sysbusdev, 3, s->irq[25]); 94 sysbus_connect_irq(sysbusdev, 4, s->irq[67]); 95 sysbus_connect_irq(sysbusdev, 5, s->irq[68]); 96 97 memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB, 98 &error_fatal); 99 memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a); 100 create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB); 101 102 /* FIXME use qdev NIC properties instead of nd_table[] */ 103 if (nd_table[0].used) { 104 qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); 105 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); 106 } 107 object_property_set_bool(OBJECT(&s->emac), true, "realized", &err); 108 if (err != NULL) { 109 error_propagate(errp, err); 110 return; 111 } 112 sysbusdev = SYS_BUS_DEVICE(&s->emac); 113 sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE); 114 sysbus_connect_irq(sysbusdev, 0, s->irq[55]); 115 116 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 117 if (err) { 118 error_propagate(errp, err); 119 return; 120 } 121 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE); 122 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]); 123 124 /* FIXME use a qdev chardev prop instead of serial_hd() */ 125 serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1], 126 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 127 } 128 129 static void aw_a10_class_init(ObjectClass *oc, void *data) 130 { 131 DeviceClass *dc = DEVICE_CLASS(oc); 132 133 dc->realize = aw_a10_realize; 134 /* Reason: Uses serial_hds and nd_table in realize function */ 135 dc->user_creatable = false; 136 } 137 138 static const TypeInfo aw_a10_type_info = { 139 .name = TYPE_AW_A10, 140 .parent = TYPE_DEVICE, 141 .instance_size = sizeof(AwA10State), 142 .instance_init = aw_a10_init, 143 .class_init = aw_a10_class_init, 144 }; 145 146 static void aw_a10_register_types(void) 147 { 148 type_register_static(&aw_a10_type_info); 149 } 150 151 type_init(aw_a10_register_types) 152