19158fa54Sliguang /* 29158fa54Sliguang * Allwinner A10 SoC emulation 39158fa54Sliguang * 49158fa54Sliguang * Copyright (C) 2013 Li Guang 59158fa54Sliguang * Written by Li Guang <lig.fnst@cn.fujitsu.com> 69158fa54Sliguang * 79158fa54Sliguang * This program is free software; you can redistribute it and/or modify it 89158fa54Sliguang * under the terms of the GNU General Public License as published by the 99158fa54Sliguang * Free Software Foundation; either version 2 of the License, or 109158fa54Sliguang * (at your option) any later version. 119158fa54Sliguang * 129158fa54Sliguang * This program is distributed in the hope that it will be useful, but WITHOUT 139158fa54Sliguang * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 149158fa54Sliguang * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 159158fa54Sliguang * for more details. 169158fa54Sliguang */ 179158fa54Sliguang 1812b16722SPeter Maydell #include "qemu/osdep.h" 19da34e65cSMarkus Armbruster #include "qapi/error.h" 204771d756SPaolo Bonzini #include "qemu-common.h" 214771d756SPaolo Bonzini #include "cpu.h" 229158fa54Sliguang #include "hw/sysbus.h" 239158fa54Sliguang #include "hw/devices.h" 249158fa54Sliguang #include "hw/arm/allwinner-a10.h" 259158fa54Sliguang 269158fa54Sliguang static void aw_a10_init(Object *obj) 279158fa54Sliguang { 289158fa54Sliguang AwA10State *s = AW_A10(obj); 299158fa54Sliguang 30*cf3fccfaSThomas Huth object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), 31*cf3fccfaSThomas Huth "cortex-a8-" TYPE_ARM_CPU, &error_abort, NULL); 329158fa54Sliguang 33*cf3fccfaSThomas Huth sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc), 34*cf3fccfaSThomas Huth TYPE_AW_A10_PIC); 359158fa54Sliguang 36*cf3fccfaSThomas Huth sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), 37*cf3fccfaSThomas Huth TYPE_AW_A10_PIT); 38db7dfd4cSBeniamino Galvani 39*cf3fccfaSThomas Huth sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), TYPE_AW_EMAC); 40dca62576SPeter Crosthwaite 41*cf3fccfaSThomas Huth sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata), 42*cf3fccfaSThomas Huth TYPE_ALLWINNER_AHCI); 439158fa54Sliguang } 449158fa54Sliguang 459158fa54Sliguang static void aw_a10_realize(DeviceState *dev, Error **errp) 469158fa54Sliguang { 479158fa54Sliguang AwA10State *s = AW_A10(dev); 489158fa54Sliguang SysBusDevice *sysbusdev; 499158fa54Sliguang uint8_t i; 509158fa54Sliguang qemu_irq fiq, irq; 519158fa54Sliguang Error *err = NULL; 529158fa54Sliguang 539158fa54Sliguang object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 549158fa54Sliguang if (err != NULL) { 559158fa54Sliguang error_propagate(errp, err); 569158fa54Sliguang return; 579158fa54Sliguang } 589158fa54Sliguang irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ); 599158fa54Sliguang fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ); 609158fa54Sliguang 619158fa54Sliguang object_property_set_bool(OBJECT(&s->intc), true, "realized", &err); 629158fa54Sliguang if (err != NULL) { 639158fa54Sliguang error_propagate(errp, err); 649158fa54Sliguang return; 659158fa54Sliguang } 669158fa54Sliguang sysbusdev = SYS_BUS_DEVICE(&s->intc); 679158fa54Sliguang sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE); 689158fa54Sliguang sysbus_connect_irq(sysbusdev, 0, irq); 699158fa54Sliguang sysbus_connect_irq(sysbusdev, 1, fiq); 709158fa54Sliguang for (i = 0; i < AW_A10_PIC_INT_NR; i++) { 719158fa54Sliguang s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i); 729158fa54Sliguang } 739158fa54Sliguang 749158fa54Sliguang object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); 759158fa54Sliguang if (err != NULL) { 769158fa54Sliguang error_propagate(errp, err); 779158fa54Sliguang return; 789158fa54Sliguang } 799158fa54Sliguang sysbusdev = SYS_BUS_DEVICE(&s->timer); 809158fa54Sliguang sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE); 819158fa54Sliguang sysbus_connect_irq(sysbusdev, 0, s->irq[22]); 829158fa54Sliguang sysbus_connect_irq(sysbusdev, 1, s->irq[23]); 839158fa54Sliguang sysbus_connect_irq(sysbusdev, 2, s->irq[24]); 849158fa54Sliguang sysbus_connect_irq(sysbusdev, 3, s->irq[25]); 859158fa54Sliguang sysbus_connect_irq(sysbusdev, 4, s->irq[67]); 869158fa54Sliguang sysbus_connect_irq(sysbusdev, 5, s->irq[68]); 879158fa54Sliguang 888aabc543SThomas Huth /* FIXME use qdev NIC properties instead of nd_table[] */ 898aabc543SThomas Huth if (nd_table[0].used) { 908aabc543SThomas Huth qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); 918aabc543SThomas Huth qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); 928aabc543SThomas Huth } 93db7dfd4cSBeniamino Galvani object_property_set_bool(OBJECT(&s->emac), true, "realized", &err); 94db7dfd4cSBeniamino Galvani if (err != NULL) { 95db7dfd4cSBeniamino Galvani error_propagate(errp, err); 96db7dfd4cSBeniamino Galvani return; 97db7dfd4cSBeniamino Galvani } 98db7dfd4cSBeniamino Galvani sysbusdev = SYS_BUS_DEVICE(&s->emac); 99db7dfd4cSBeniamino Galvani sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE); 100db7dfd4cSBeniamino Galvani sysbus_connect_irq(sysbusdev, 0, s->irq[55]); 101db7dfd4cSBeniamino Galvani 102dca62576SPeter Crosthwaite object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 103dca62576SPeter Crosthwaite if (err) { 104dca62576SPeter Crosthwaite error_propagate(errp, err); 105dca62576SPeter Crosthwaite return; 106dca62576SPeter Crosthwaite } 107dca62576SPeter Crosthwaite sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE); 108dca62576SPeter Crosthwaite sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]); 109dca62576SPeter Crosthwaite 1109bca0edbSPeter Maydell /* FIXME use a qdev chardev prop instead of serial_hd() */ 1119158fa54Sliguang serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1], 1129bca0edbSPeter Maydell 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 1139158fa54Sliguang } 1149158fa54Sliguang 1159158fa54Sliguang static void aw_a10_class_init(ObjectClass *oc, void *data) 1169158fa54Sliguang { 1179158fa54Sliguang DeviceClass *dc = DEVICE_CLASS(oc); 1189158fa54Sliguang 1199158fa54Sliguang dc->realize = aw_a10_realize; 1208aabc543SThomas Huth /* Reason: Uses serial_hds and nd_table in realize function */ 121dc89a180SThomas Huth dc->user_creatable = false; 1229158fa54Sliguang } 1239158fa54Sliguang 1249158fa54Sliguang static const TypeInfo aw_a10_type_info = { 1259158fa54Sliguang .name = TYPE_AW_A10, 1269158fa54Sliguang .parent = TYPE_DEVICE, 1279158fa54Sliguang .instance_size = sizeof(AwA10State), 1289158fa54Sliguang .instance_init = aw_a10_init, 1299158fa54Sliguang .class_init = aw_a10_class_init, 1309158fa54Sliguang }; 1319158fa54Sliguang 1329158fa54Sliguang static void aw_a10_register_types(void) 1339158fa54Sliguang { 1349158fa54Sliguang type_register_static(&aw_a10_type_info); 1359158fa54Sliguang } 1369158fa54Sliguang 1379158fa54Sliguang type_init(aw_a10_register_types) 138