19158fa54Sliguang /* 29158fa54Sliguang * Allwinner A10 SoC emulation 39158fa54Sliguang * 49158fa54Sliguang * Copyright (C) 2013 Li Guang 59158fa54Sliguang * Written by Li Guang <lig.fnst@cn.fujitsu.com> 69158fa54Sliguang * 79158fa54Sliguang * This program is free software; you can redistribute it and/or modify it 89158fa54Sliguang * under the terms of the GNU General Public License as published by the 99158fa54Sliguang * Free Software Foundation; either version 2 of the License, or 109158fa54Sliguang * (at your option) any later version. 119158fa54Sliguang * 129158fa54Sliguang * This program is distributed in the hope that it will be useful, but WITHOUT 139158fa54Sliguang * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 149158fa54Sliguang * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 159158fa54Sliguang * for more details. 169158fa54Sliguang */ 179158fa54Sliguang 1812b16722SPeter Maydell #include "qemu/osdep.h" 195a720b1eSMarkus Armbruster #include "exec/address-spaces.h" 20da34e65cSMarkus Armbruster #include "qapi/error.h" 210b8fa32fSMarkus Armbruster #include "qemu/module.h" 224771d756SPaolo Bonzini #include "cpu.h" 239158fa54Sliguang #include "hw/sysbus.h" 249158fa54Sliguang #include "hw/arm/allwinner-a10.h" 25ead07aa4SPhilippe Mathieu-Daudé #include "hw/misc/unimp.h" 2646517dd4SMarkus Armbruster #include "sysemu/sysemu.h" 279158fa54Sliguang 287f0ec989SPhilippe Mathieu-Daudé #define AW_A10_PIC_REG_BASE 0x01c20400 297f0ec989SPhilippe Mathieu-Daudé #define AW_A10_PIT_REG_BASE 0x01c20c00 307f0ec989SPhilippe Mathieu-Daudé #define AW_A10_UART0_REG_BASE 0x01c28000 317f0ec989SPhilippe Mathieu-Daudé #define AW_A10_EMAC_BASE 0x01c0b000 327f0ec989SPhilippe Mathieu-Daudé #define AW_A10_SATA_BASE 0x01c18000 337f0ec989SPhilippe Mathieu-Daudé 349158fa54Sliguang static void aw_a10_init(Object *obj) 359158fa54Sliguang { 369158fa54Sliguang AwA10State *s = AW_A10(obj); 379158fa54Sliguang 38cf3fccfaSThomas Huth object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), 398a863c81SPhilippe Mathieu-Daudé ARM_CPU_TYPE_NAME("cortex-a8"), 408a863c81SPhilippe Mathieu-Daudé &error_abort, NULL); 419158fa54Sliguang 42cf3fccfaSThomas Huth sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc), 43cf3fccfaSThomas Huth TYPE_AW_A10_PIC); 449158fa54Sliguang 45cf3fccfaSThomas Huth sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), 46cf3fccfaSThomas Huth TYPE_AW_A10_PIT); 47db7dfd4cSBeniamino Galvani 48cf3fccfaSThomas Huth sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), TYPE_AW_EMAC); 49dca62576SPeter Crosthwaite 50cf3fccfaSThomas Huth sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata), 51cf3fccfaSThomas Huth TYPE_ALLWINNER_AHCI); 529158fa54Sliguang } 539158fa54Sliguang 549158fa54Sliguang static void aw_a10_realize(DeviceState *dev, Error **errp) 559158fa54Sliguang { 569158fa54Sliguang AwA10State *s = AW_A10(dev); 579158fa54Sliguang SysBusDevice *sysbusdev; 589158fa54Sliguang Error *err = NULL; 599158fa54Sliguang 609158fa54Sliguang object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 619158fa54Sliguang if (err != NULL) { 629158fa54Sliguang error_propagate(errp, err); 639158fa54Sliguang return; 649158fa54Sliguang } 659158fa54Sliguang 669158fa54Sliguang object_property_set_bool(OBJECT(&s->intc), true, "realized", &err); 679158fa54Sliguang if (err != NULL) { 689158fa54Sliguang error_propagate(errp, err); 699158fa54Sliguang return; 709158fa54Sliguang } 719158fa54Sliguang sysbusdev = SYS_BUS_DEVICE(&s->intc); 729158fa54Sliguang sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE); 73*af4ba4edSPhilippe Mathieu-Daudé sysbus_connect_irq(sysbusdev, 0, 74*af4ba4edSPhilippe Mathieu-Daudé qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 75*af4ba4edSPhilippe Mathieu-Daudé sysbus_connect_irq(sysbusdev, 1, 76*af4ba4edSPhilippe Mathieu-Daudé qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 77f8a865d3SPhilippe Mathieu-Daudé qdev_pass_gpios(DEVICE(&s->intc), dev, NULL); 789158fa54Sliguang 799158fa54Sliguang object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); 809158fa54Sliguang if (err != NULL) { 819158fa54Sliguang error_propagate(errp, err); 829158fa54Sliguang return; 839158fa54Sliguang } 849158fa54Sliguang sysbusdev = SYS_BUS_DEVICE(&s->timer); 859158fa54Sliguang sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE); 86f8a865d3SPhilippe Mathieu-Daudé sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22)); 87f8a865d3SPhilippe Mathieu-Daudé sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23)); 88f8a865d3SPhilippe Mathieu-Daudé sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24)); 89f8a865d3SPhilippe Mathieu-Daudé sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25)); 90f8a865d3SPhilippe Mathieu-Daudé sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67)); 91f8a865d3SPhilippe Mathieu-Daudé sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68)); 929158fa54Sliguang 93ead07aa4SPhilippe Mathieu-Daudé memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB, 94ead07aa4SPhilippe Mathieu-Daudé &error_fatal); 95ead07aa4SPhilippe Mathieu-Daudé memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a); 96ead07aa4SPhilippe Mathieu-Daudé create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB); 97ead07aa4SPhilippe Mathieu-Daudé 988aabc543SThomas Huth /* FIXME use qdev NIC properties instead of nd_table[] */ 998aabc543SThomas Huth if (nd_table[0].used) { 1008aabc543SThomas Huth qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); 1018aabc543SThomas Huth qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); 1028aabc543SThomas Huth } 103db7dfd4cSBeniamino Galvani object_property_set_bool(OBJECT(&s->emac), true, "realized", &err); 104db7dfd4cSBeniamino Galvani if (err != NULL) { 105db7dfd4cSBeniamino Galvani error_propagate(errp, err); 106db7dfd4cSBeniamino Galvani return; 107db7dfd4cSBeniamino Galvani } 108db7dfd4cSBeniamino Galvani sysbusdev = SYS_BUS_DEVICE(&s->emac); 109db7dfd4cSBeniamino Galvani sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE); 110f8a865d3SPhilippe Mathieu-Daudé sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55)); 111db7dfd4cSBeniamino Galvani 112dca62576SPeter Crosthwaite object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 113dca62576SPeter Crosthwaite if (err) { 114dca62576SPeter Crosthwaite error_propagate(errp, err); 115dca62576SPeter Crosthwaite return; 116dca62576SPeter Crosthwaite } 117dca62576SPeter Crosthwaite sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE); 118f8a865d3SPhilippe Mathieu-Daudé sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56)); 119dca62576SPeter Crosthwaite 1209bca0edbSPeter Maydell /* FIXME use a qdev chardev prop instead of serial_hd() */ 121f8a865d3SPhilippe Mathieu-Daudé serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, 122f8a865d3SPhilippe Mathieu-Daudé qdev_get_gpio_in(dev, 1), 1239bca0edbSPeter Maydell 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 1249158fa54Sliguang } 1259158fa54Sliguang 1269158fa54Sliguang static void aw_a10_class_init(ObjectClass *oc, void *data) 1279158fa54Sliguang { 1289158fa54Sliguang DeviceClass *dc = DEVICE_CLASS(oc); 1299158fa54Sliguang 1309158fa54Sliguang dc->realize = aw_a10_realize; 1318aabc543SThomas Huth /* Reason: Uses serial_hds and nd_table in realize function */ 132dc89a180SThomas Huth dc->user_creatable = false; 1339158fa54Sliguang } 1349158fa54Sliguang 1359158fa54Sliguang static const TypeInfo aw_a10_type_info = { 1369158fa54Sliguang .name = TYPE_AW_A10, 1379158fa54Sliguang .parent = TYPE_DEVICE, 1389158fa54Sliguang .instance_size = sizeof(AwA10State), 1399158fa54Sliguang .instance_init = aw_a10_init, 1409158fa54Sliguang .class_init = aw_a10_class_init, 1419158fa54Sliguang }; 1429158fa54Sliguang 1439158fa54Sliguang static void aw_a10_register_types(void) 1449158fa54Sliguang { 1459158fa54Sliguang type_register_static(&aw_a10_type_info); 1469158fa54Sliguang } 1479158fa54Sliguang 1489158fa54Sliguang type_init(aw_a10_register_types) 149