xref: /qemu/hw/arm/allwinner-a10.c (revision 5a720b1ed55a80672fdacf340fda0224f17146f3)
19158fa54Sliguang /*
29158fa54Sliguang  * Allwinner A10 SoC emulation
39158fa54Sliguang  *
49158fa54Sliguang  * Copyright (C) 2013 Li Guang
59158fa54Sliguang  * Written by Li Guang <lig.fnst@cn.fujitsu.com>
69158fa54Sliguang  *
79158fa54Sliguang  * This program is free software; you can redistribute it and/or modify it
89158fa54Sliguang  * under the terms of the GNU General Public License as published by the
99158fa54Sliguang  * Free Software Foundation; either version 2 of the License, or
109158fa54Sliguang  * (at your option) any later version.
119158fa54Sliguang  *
129158fa54Sliguang  * This program is distributed in the hope that it will be useful, but WITHOUT
139158fa54Sliguang  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
149158fa54Sliguang  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
159158fa54Sliguang  * for more details.
169158fa54Sliguang  */
179158fa54Sliguang 
1812b16722SPeter Maydell #include "qemu/osdep.h"
19*5a720b1eSMarkus Armbruster #include "exec/address-spaces.h"
20da34e65cSMarkus Armbruster #include "qapi/error.h"
210b8fa32fSMarkus Armbruster #include "qemu/module.h"
224771d756SPaolo Bonzini #include "cpu.h"
239158fa54Sliguang #include "hw/sysbus.h"
249158fa54Sliguang #include "hw/arm/allwinner-a10.h"
25ead07aa4SPhilippe Mathieu-Daudé #include "hw/misc/unimp.h"
269158fa54Sliguang 
279158fa54Sliguang static void aw_a10_init(Object *obj)
289158fa54Sliguang {
299158fa54Sliguang     AwA10State *s = AW_A10(obj);
309158fa54Sliguang 
31cf3fccfaSThomas Huth     object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
32cf3fccfaSThomas Huth                             "cortex-a8-" TYPE_ARM_CPU, &error_abort, NULL);
339158fa54Sliguang 
34cf3fccfaSThomas Huth     sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
35cf3fccfaSThomas Huth                           TYPE_AW_A10_PIC);
369158fa54Sliguang 
37cf3fccfaSThomas Huth     sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
38cf3fccfaSThomas Huth                           TYPE_AW_A10_PIT);
39db7dfd4cSBeniamino Galvani 
40cf3fccfaSThomas Huth     sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), TYPE_AW_EMAC);
41dca62576SPeter Crosthwaite 
42cf3fccfaSThomas Huth     sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata),
43cf3fccfaSThomas Huth                           TYPE_ALLWINNER_AHCI);
449158fa54Sliguang }
459158fa54Sliguang 
469158fa54Sliguang static void aw_a10_realize(DeviceState *dev, Error **errp)
479158fa54Sliguang {
489158fa54Sliguang     AwA10State *s = AW_A10(dev);
499158fa54Sliguang     SysBusDevice *sysbusdev;
509158fa54Sliguang     uint8_t i;
519158fa54Sliguang     qemu_irq fiq, irq;
529158fa54Sliguang     Error *err = NULL;
539158fa54Sliguang 
549158fa54Sliguang     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
559158fa54Sliguang     if (err != NULL) {
569158fa54Sliguang         error_propagate(errp, err);
579158fa54Sliguang         return;
589158fa54Sliguang     }
599158fa54Sliguang     irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ);
609158fa54Sliguang     fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ);
619158fa54Sliguang 
629158fa54Sliguang     object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
639158fa54Sliguang     if (err != NULL) {
649158fa54Sliguang         error_propagate(errp, err);
659158fa54Sliguang         return;
669158fa54Sliguang     }
679158fa54Sliguang     sysbusdev = SYS_BUS_DEVICE(&s->intc);
689158fa54Sliguang     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
699158fa54Sliguang     sysbus_connect_irq(sysbusdev, 0, irq);
709158fa54Sliguang     sysbus_connect_irq(sysbusdev, 1, fiq);
719158fa54Sliguang     for (i = 0; i < AW_A10_PIC_INT_NR; i++) {
729158fa54Sliguang         s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);
739158fa54Sliguang     }
749158fa54Sliguang 
759158fa54Sliguang     object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
769158fa54Sliguang     if (err != NULL) {
779158fa54Sliguang         error_propagate(errp, err);
789158fa54Sliguang         return;
799158fa54Sliguang     }
809158fa54Sliguang     sysbusdev = SYS_BUS_DEVICE(&s->timer);
819158fa54Sliguang     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
829158fa54Sliguang     sysbus_connect_irq(sysbusdev, 0, s->irq[22]);
839158fa54Sliguang     sysbus_connect_irq(sysbusdev, 1, s->irq[23]);
849158fa54Sliguang     sysbus_connect_irq(sysbusdev, 2, s->irq[24]);
859158fa54Sliguang     sysbus_connect_irq(sysbusdev, 3, s->irq[25]);
869158fa54Sliguang     sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
879158fa54Sliguang     sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
889158fa54Sliguang 
89ead07aa4SPhilippe Mathieu-Daudé     memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
90ead07aa4SPhilippe Mathieu-Daudé                            &error_fatal);
91ead07aa4SPhilippe Mathieu-Daudé     memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
92ead07aa4SPhilippe Mathieu-Daudé     create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
93ead07aa4SPhilippe Mathieu-Daudé 
948aabc543SThomas Huth     /* FIXME use qdev NIC properties instead of nd_table[] */
958aabc543SThomas Huth     if (nd_table[0].used) {
968aabc543SThomas Huth         qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
978aabc543SThomas Huth         qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
988aabc543SThomas Huth     }
99db7dfd4cSBeniamino Galvani     object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
100db7dfd4cSBeniamino Galvani     if (err != NULL) {
101db7dfd4cSBeniamino Galvani         error_propagate(errp, err);
102db7dfd4cSBeniamino Galvani         return;
103db7dfd4cSBeniamino Galvani     }
104db7dfd4cSBeniamino Galvani     sysbusdev = SYS_BUS_DEVICE(&s->emac);
105db7dfd4cSBeniamino Galvani     sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
106db7dfd4cSBeniamino Galvani     sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
107db7dfd4cSBeniamino Galvani 
108dca62576SPeter Crosthwaite     object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
109dca62576SPeter Crosthwaite     if (err) {
110dca62576SPeter Crosthwaite         error_propagate(errp, err);
111dca62576SPeter Crosthwaite         return;
112dca62576SPeter Crosthwaite     }
113dca62576SPeter Crosthwaite     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
114dca62576SPeter Crosthwaite     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]);
115dca62576SPeter Crosthwaite 
1169bca0edbSPeter Maydell     /* FIXME use a qdev chardev prop instead of serial_hd() */
1179158fa54Sliguang     serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
1189bca0edbSPeter Maydell                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
1199158fa54Sliguang }
1209158fa54Sliguang 
1219158fa54Sliguang static void aw_a10_class_init(ObjectClass *oc, void *data)
1229158fa54Sliguang {
1239158fa54Sliguang     DeviceClass *dc = DEVICE_CLASS(oc);
1249158fa54Sliguang 
1259158fa54Sliguang     dc->realize = aw_a10_realize;
1268aabc543SThomas Huth     /* Reason: Uses serial_hds and nd_table in realize function */
127dc89a180SThomas Huth     dc->user_creatable = false;
1289158fa54Sliguang }
1299158fa54Sliguang 
1309158fa54Sliguang static const TypeInfo aw_a10_type_info = {
1319158fa54Sliguang     .name = TYPE_AW_A10,
1329158fa54Sliguang     .parent = TYPE_DEVICE,
1339158fa54Sliguang     .instance_size = sizeof(AwA10State),
1349158fa54Sliguang     .instance_init = aw_a10_init,
1359158fa54Sliguang     .class_init = aw_a10_class_init,
1369158fa54Sliguang };
1379158fa54Sliguang 
1389158fa54Sliguang static void aw_a10_register_types(void)
1399158fa54Sliguang {
1409158fa54Sliguang     type_register_static(&aw_a10_type_info);
1419158fa54Sliguang }
1429158fa54Sliguang 
1439158fa54Sliguang type_init(aw_a10_register_types)
144