1 /* 2 * QEMU<->ACPI BIOS PCI hotplug interface 3 * 4 * QEMU supports PCI hotplug via ACPI. This module 5 * implements the interface between QEMU and the ACPI BIOS. 6 * Interface specification - see docs/specs/acpi_pci_hotplug.txt 7 * 8 * Copyright (c) 2013, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com) 9 * Copyright (c) 2006 Fabrice Bellard 10 * 11 * This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU Lesser General Public 13 * License version 2.1 as published by the Free Software Foundation. 14 * 15 * This library is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * Lesser General Public License for more details. 19 * 20 * You should have received a copy of the GNU Lesser General Public 21 * License along with this library; if not, see <http://www.gnu.org/licenses/> 22 * 23 * Contributions after 2012-01-13 are licensed under the terms of the 24 * GNU GPL, version 2 or (at your option) any later version. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/acpi/pcihp.h" 29 30 #include "hw/pci-host/i440fx.h" 31 #include "hw/pci/pci.h" 32 #include "hw/pci/pci_bridge.h" 33 #include "hw/acpi/acpi.h" 34 #include "hw/pci/pci_bus.h" 35 #include "migration/vmstate.h" 36 #include "qapi/error.h" 37 #include "qom/qom-qobject.h" 38 #include "trace.h" 39 40 #define ACPI_PCIHP_SIZE 0x0018 41 #define PCI_UP_BASE 0x0000 42 #define PCI_DOWN_BASE 0x0004 43 #define PCI_EJ_BASE 0x0008 44 #define PCI_RMV_BASE 0x000c 45 #define PCI_SEL_BASE 0x0010 46 #define PCI_AIDX_BASE 0x0014 47 48 typedef struct AcpiPciHpFind { 49 int bsel; 50 PCIBus *bus; 51 } AcpiPciHpFind; 52 53 static gint g_cmp_uint32(gconstpointer a, gconstpointer b, gpointer user_data) 54 { 55 return a - b; 56 } 57 58 static GSequence *pci_acpi_index_list(void) 59 { 60 static GSequence *used_acpi_index_list; 61 62 if (!used_acpi_index_list) { 63 used_acpi_index_list = g_sequence_new(NULL); 64 } 65 return used_acpi_index_list; 66 } 67 68 static int acpi_pcihp_get_bsel(PCIBus *bus) 69 { 70 Error *local_err = NULL; 71 uint64_t bsel = object_property_get_uint(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, 72 &local_err); 73 74 if (local_err || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) { 75 if (local_err) { 76 error_free(local_err); 77 } 78 return -1; 79 } else { 80 return bsel; 81 } 82 } 83 84 /* Assign BSEL property to all buses. In the future, this can be changed 85 * to only assign to buses that support hotplug. 86 */ 87 static void *acpi_set_bsel(PCIBus *bus, void *opaque) 88 { 89 unsigned *bsel_alloc = opaque; 90 unsigned *bus_bsel; 91 92 if (qbus_is_hotpluggable(BUS(bus))) { 93 bus_bsel = g_malloc(sizeof *bus_bsel); 94 95 *bus_bsel = (*bsel_alloc)++; 96 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, 97 bus_bsel, OBJ_PROP_FLAG_READ); 98 } 99 100 return bsel_alloc; 101 } 102 103 static void acpi_set_pci_info(void) 104 { 105 static bool bsel_is_set; 106 PCIBus *bus; 107 unsigned bsel_alloc = ACPI_PCIHP_BSEL_DEFAULT; 108 109 if (bsel_is_set) { 110 return; 111 } 112 bsel_is_set = true; 113 114 bus = find_i440fx(); /* TODO: Q35 support */ 115 if (bus) { 116 /* Scan all PCI buses. Set property to enable acpi based hotplug. */ 117 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); 118 } 119 } 120 121 static void acpi_pcihp_disable_root_bus(void) 122 { 123 static bool root_hp_disabled; 124 PCIBus *bus; 125 126 if (root_hp_disabled) { 127 return; 128 } 129 130 bus = find_i440fx(); 131 if (bus) { 132 /* setting the hotplug handler to NULL makes the bus non-hotpluggable */ 133 qbus_set_hotplug_handler(BUS(bus), NULL); 134 } 135 root_hp_disabled = true; 136 return; 137 } 138 139 static void acpi_pcihp_test_hotplug_bus(PCIBus *bus, void *opaque) 140 { 141 AcpiPciHpFind *find = opaque; 142 if (find->bsel == acpi_pcihp_get_bsel(bus)) { 143 find->bus = bus; 144 } 145 } 146 147 static PCIBus *acpi_pcihp_find_hotplug_bus(AcpiPciHpState *s, int bsel) 148 { 149 AcpiPciHpFind find = { .bsel = bsel, .bus = NULL }; 150 151 if (bsel < 0) { 152 return NULL; 153 } 154 155 pci_for_each_bus(s->root, acpi_pcihp_test_hotplug_bus, &find); 156 157 /* Make bsel 0 eject root bus if bsel property is not set, 158 * for compatibility with non acpi setups. 159 * TODO: really needed? 160 */ 161 if (!bsel && !find.bus) { 162 find.bus = s->root; 163 } 164 165 /* 166 * Check if find.bus is actually hotpluggable. If bsel is set to 167 * NULL for example on the root bus in order to make it 168 * non-hotpluggable, find.bus will match the root bus when bsel 169 * is 0. See acpi_pcihp_test_hotplug_bus() above. Since the 170 * bus is not hotpluggable however, we should not select the bus. 171 * Instead, we should set find.bus to NULL in that case. In the check 172 * below, we generalize this case for all buses, not just the root bus. 173 * The callers of this function check for a null return value and 174 * handle them appropriately. 175 */ 176 if (find.bus && !qbus_is_hotpluggable(BUS(find.bus))) { 177 find.bus = NULL; 178 } 179 return find.bus; 180 } 181 182 static bool acpi_pcihp_pc_no_hotplug(AcpiPciHpState *s, PCIDevice *dev) 183 { 184 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 185 DeviceClass *dc = DEVICE_GET_CLASS(dev); 186 /* 187 * ACPI doesn't allow hotplug of bridge devices. Don't allow 188 * hot-unplug of bridge devices unless they were added by hotplug 189 * (and so, not described by acpi). 190 */ 191 return (pc->is_bridge && !dev->qdev.hotplugged) || !dc->hotpluggable; 192 } 193 194 static void acpi_pcihp_eject_slot(AcpiPciHpState *s, unsigned bsel, unsigned slots) 195 { 196 HotplugHandler *hotplug_ctrl; 197 BusChild *kid, *next; 198 int slot = ctz32(slots); 199 PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel); 200 201 trace_acpi_pci_eject_slot(bsel, slot); 202 203 if (!bus || slot > 31) { 204 return; 205 } 206 207 /* Mark request as complete */ 208 s->acpi_pcihp_pci_status[bsel].down &= ~(1U << slot); 209 s->acpi_pcihp_pci_status[bsel].up &= ~(1U << slot); 210 211 QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) { 212 DeviceState *qdev = kid->child; 213 PCIDevice *dev = PCI_DEVICE(qdev); 214 if (PCI_SLOT(dev->devfn) == slot) { 215 if (!acpi_pcihp_pc_no_hotplug(s, dev)) { 216 hotplug_ctrl = qdev_get_hotplug_handler(qdev); 217 hotplug_handler_unplug(hotplug_ctrl, qdev, &error_abort); 218 object_unparent(OBJECT(qdev)); 219 } 220 } 221 } 222 } 223 224 static void acpi_pcihp_update_hotplug_bus(AcpiPciHpState *s, int bsel) 225 { 226 BusChild *kid, *next; 227 PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel); 228 229 /* Execute any pending removes during reset */ 230 while (s->acpi_pcihp_pci_status[bsel].down) { 231 acpi_pcihp_eject_slot(s, bsel, s->acpi_pcihp_pci_status[bsel].down); 232 } 233 234 s->acpi_pcihp_pci_status[bsel].hotplug_enable = ~0; 235 236 if (!bus) { 237 return; 238 } 239 QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) { 240 DeviceState *qdev = kid->child; 241 PCIDevice *pdev = PCI_DEVICE(qdev); 242 int slot = PCI_SLOT(pdev->devfn); 243 244 if (acpi_pcihp_pc_no_hotplug(s, pdev)) { 245 s->acpi_pcihp_pci_status[bsel].hotplug_enable &= ~(1U << slot); 246 } 247 } 248 } 249 250 static void acpi_pcihp_update(AcpiPciHpState *s) 251 { 252 int i; 253 254 for (i = 0; i < ACPI_PCIHP_MAX_HOTPLUG_BUS; ++i) { 255 acpi_pcihp_update_hotplug_bus(s, i); 256 } 257 } 258 259 void acpi_pcihp_reset(AcpiPciHpState *s, bool acpihp_root_off) 260 { 261 if (acpihp_root_off) { 262 acpi_pcihp_disable_root_bus(); 263 } 264 acpi_set_pci_info(); 265 acpi_pcihp_update(s); 266 } 267 268 #define ONBOARD_INDEX_MAX (16 * 1024 - 1) 269 270 void acpi_pcihp_device_pre_plug_cb(HotplugHandler *hotplug_dev, 271 DeviceState *dev, Error **errp) 272 { 273 PCIDevice *pdev = PCI_DEVICE(dev); 274 275 /* Only hotplugged devices need the hotplug capability. */ 276 if (dev->hotplugged && 277 acpi_pcihp_get_bsel(pci_get_bus(PCI_DEVICE(dev))) < 0) { 278 error_setg(errp, "Unsupported bus. Bus doesn't have property '" 279 ACPI_PCIHP_PROP_BSEL "' set"); 280 return; 281 } 282 283 /* 284 * capped by systemd (see: udev-builtin-net_id.c) 285 * as it's the only known user honor it to avoid users 286 * misconfigure QEMU and then wonder why acpi-index doesn't work 287 */ 288 if (pdev->acpi_index > ONBOARD_INDEX_MAX) { 289 error_setg(errp, "acpi-index should be less or equal to %u", 290 ONBOARD_INDEX_MAX); 291 return; 292 } 293 294 /* 295 * make sure that acpi-index is unique across all present PCI devices 296 */ 297 if (pdev->acpi_index) { 298 GSequence *used_indexes = pci_acpi_index_list(); 299 300 if (g_sequence_lookup(used_indexes, GINT_TO_POINTER(pdev->acpi_index), 301 g_cmp_uint32, NULL)) { 302 error_setg(errp, "a PCI device with acpi-index = %" PRIu32 303 " already exist", pdev->acpi_index); 304 return; 305 } 306 g_sequence_insert_sorted(used_indexes, 307 GINT_TO_POINTER(pdev->acpi_index), 308 g_cmp_uint32, NULL); 309 } 310 } 311 312 void acpi_pcihp_device_plug_cb(HotplugHandler *hotplug_dev, AcpiPciHpState *s, 313 DeviceState *dev, Error **errp) 314 { 315 PCIDevice *pdev = PCI_DEVICE(dev); 316 int slot = PCI_SLOT(pdev->devfn); 317 int bsel; 318 319 /* Don't send event when device is enabled during qemu machine creation: 320 * it is present on boot, no hotplug event is necessary. We do send an 321 * event when the device is disabled later. */ 322 if (!dev->hotplugged) { 323 /* 324 * Overwrite the default hotplug handler with the ACPI PCI one 325 * for cold plugged bridges only. 326 */ 327 if (!s->legacy_piix && 328 object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 329 PCIBus *sec = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 330 331 qbus_set_hotplug_handler(BUS(sec), OBJECT(hotplug_dev)); 332 /* We don't have to overwrite any other hotplug handler yet */ 333 assert(QLIST_EMPTY(&sec->child)); 334 } 335 336 return; 337 } 338 339 bsel = acpi_pcihp_get_bsel(pci_get_bus(pdev)); 340 g_assert(bsel >= 0); 341 s->acpi_pcihp_pci_status[bsel].up |= (1U << slot); 342 acpi_send_event(DEVICE(hotplug_dev), ACPI_PCI_HOTPLUG_STATUS); 343 } 344 345 void acpi_pcihp_device_unplug_cb(HotplugHandler *hotplug_dev, AcpiPciHpState *s, 346 DeviceState *dev, Error **errp) 347 { 348 PCIDevice *pdev = PCI_DEVICE(dev); 349 350 trace_acpi_pci_unplug(PCI_SLOT(PCI_DEVICE(dev)->devfn), 351 acpi_pcihp_get_bsel(pci_get_bus(PCI_DEVICE(dev)))); 352 353 /* 354 * clean up acpi-index so it could reused by another device 355 */ 356 if (pdev->acpi_index) { 357 GSequence *used_indexes = pci_acpi_index_list(); 358 359 g_sequence_remove(g_sequence_lookup(used_indexes, 360 GINT_TO_POINTER(pdev->acpi_index), 361 g_cmp_uint32, NULL)); 362 } 363 364 qdev_unrealize(dev); 365 } 366 367 void acpi_pcihp_device_unplug_request_cb(HotplugHandler *hotplug_dev, 368 AcpiPciHpState *s, DeviceState *dev, 369 Error **errp) 370 { 371 PCIDevice *pdev = PCI_DEVICE(dev); 372 int slot = PCI_SLOT(pdev->devfn); 373 int bsel = acpi_pcihp_get_bsel(pci_get_bus(pdev)); 374 375 trace_acpi_pci_unplug_request(bsel, slot); 376 377 if (bsel < 0) { 378 error_setg(errp, "Unsupported bus. Bus doesn't have property '" 379 ACPI_PCIHP_PROP_BSEL "' set"); 380 return; 381 } 382 383 s->acpi_pcihp_pci_status[bsel].down |= (1U << slot); 384 acpi_send_event(DEVICE(hotplug_dev), ACPI_PCI_HOTPLUG_STATUS); 385 } 386 387 static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) 388 { 389 AcpiPciHpState *s = opaque; 390 uint32_t val = 0; 391 int bsel = s->hotplug_select; 392 393 if (bsel < 0 || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) { 394 return 0; 395 } 396 397 switch (addr) { 398 case PCI_UP_BASE: 399 val = s->acpi_pcihp_pci_status[bsel].up; 400 if (!s->legacy_piix) { 401 s->acpi_pcihp_pci_status[bsel].up = 0; 402 } 403 trace_acpi_pci_up_read(val); 404 break; 405 case PCI_DOWN_BASE: 406 val = s->acpi_pcihp_pci_status[bsel].down; 407 trace_acpi_pci_down_read(val); 408 break; 409 case PCI_EJ_BASE: 410 trace_acpi_pci_features_read(val); 411 break; 412 case PCI_RMV_BASE: 413 val = s->acpi_pcihp_pci_status[bsel].hotplug_enable; 414 trace_acpi_pci_rmv_read(val); 415 break; 416 case PCI_SEL_BASE: 417 val = s->hotplug_select; 418 trace_acpi_pci_sel_read(val); 419 break; 420 case PCI_AIDX_BASE: 421 val = s->acpi_index; 422 s->acpi_index = 0; 423 trace_acpi_pci_acpi_index_read(val); 424 break; 425 default: 426 break; 427 } 428 429 return val; 430 } 431 432 static void pci_write(void *opaque, hwaddr addr, uint64_t data, 433 unsigned int size) 434 { 435 int slot; 436 PCIBus *bus; 437 BusChild *kid, *next; 438 AcpiPciHpState *s = opaque; 439 440 s->acpi_index = 0; 441 switch (addr) { 442 case PCI_AIDX_BASE: 443 /* 444 * fetch acpi-index for specified slot so that follow up read from 445 * PCI_AIDX_BASE can return it to guest 446 */ 447 slot = ctz32(data); 448 449 if (s->hotplug_select >= ACPI_PCIHP_MAX_HOTPLUG_BUS) { 450 break; 451 } 452 453 bus = acpi_pcihp_find_hotplug_bus(s, s->hotplug_select); 454 QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) { 455 Object *o = OBJECT(kid->child); 456 PCIDevice *dev = PCI_DEVICE(o); 457 if (PCI_SLOT(dev->devfn) == slot) { 458 s->acpi_index = object_property_get_uint(o, "acpi-index", NULL); 459 break; 460 } 461 } 462 trace_acpi_pci_acpi_index_write(s->hotplug_select, slot, s->acpi_index); 463 break; 464 case PCI_EJ_BASE: 465 if (s->hotplug_select >= ACPI_PCIHP_MAX_HOTPLUG_BUS) { 466 break; 467 } 468 acpi_pcihp_eject_slot(s, s->hotplug_select, data); 469 trace_acpi_pci_ej_write(addr, data); 470 break; 471 case PCI_SEL_BASE: 472 s->hotplug_select = s->legacy_piix ? ACPI_PCIHP_BSEL_DEFAULT : data; 473 trace_acpi_pci_sel_write(addr, data); 474 default: 475 break; 476 } 477 } 478 479 static const MemoryRegionOps acpi_pcihp_io_ops = { 480 .read = pci_read, 481 .write = pci_write, 482 .endianness = DEVICE_LITTLE_ENDIAN, 483 .valid = { 484 .min_access_size = 4, 485 .max_access_size = 4, 486 }, 487 }; 488 489 void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus, 490 MemoryRegion *address_space_io, bool bridges_enabled, 491 uint16_t io_base) 492 { 493 s->io_len = ACPI_PCIHP_SIZE; 494 s->io_base = io_base; 495 496 s->root = root_bus; 497 s->legacy_piix = !bridges_enabled; 498 499 memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s, 500 "acpi-pci-hotplug", s->io_len); 501 memory_region_add_subregion(address_space_io, s->io_base, &s->io); 502 503 object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_BASE_PROP, &s->io_base, 504 OBJ_PROP_FLAG_READ); 505 object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_LEN_PROP, &s->io_len, 506 OBJ_PROP_FLAG_READ); 507 } 508 509 bool vmstate_acpi_pcihp_use_acpi_index(void *opaque, int version_id) 510 { 511 AcpiPciHpState *s = opaque; 512 return s->acpi_index; 513 } 514 515 const VMStateDescription vmstate_acpi_pcihp_pci_status = { 516 .name = "acpi_pcihp_pci_status", 517 .version_id = 1, 518 .minimum_version_id = 1, 519 .fields = (VMStateField[]) { 520 VMSTATE_UINT32(up, AcpiPciHpPciStatus), 521 VMSTATE_UINT32(down, AcpiPciHpPciStatus), 522 VMSTATE_END_OF_LIST() 523 } 524 }; 525