1 /* 2 * QEMU ICH9 TCO emulation 3 * 4 * Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 #include "qemu/osdep.h" 10 #include "sysemu/watchdog.h" 11 #include "hw/i386/ich9.h" 12 13 #include "hw/acpi/tco.h" 14 #include "trace.h" 15 16 //#define DEBUG 17 18 #ifdef DEBUG 19 #define TCO_DEBUG(fmt, ...) \ 20 do { \ 21 fprintf(stderr, "%s "fmt, __func__, ## __VA_ARGS__); \ 22 } while (0) 23 #else 24 #define TCO_DEBUG(fmt, ...) do { } while (0) 25 #endif 26 27 enum { 28 TCO_RLD_DEFAULT = 0x0000, 29 TCO_DAT_IN_DEFAULT = 0x00, 30 TCO_DAT_OUT_DEFAULT = 0x00, 31 TCO1_STS_DEFAULT = 0x0000, 32 TCO2_STS_DEFAULT = 0x0000, 33 TCO1_CNT_DEFAULT = 0x0000, 34 TCO2_CNT_DEFAULT = 0x0008, 35 TCO_MESSAGE1_DEFAULT = 0x00, 36 TCO_MESSAGE2_DEFAULT = 0x00, 37 TCO_WDCNT_DEFAULT = 0x00, 38 TCO_TMR_DEFAULT = 0x0004, 39 SW_IRQ_GEN_DEFAULT = 0x03, 40 }; 41 42 static inline void tco_timer_reload(TCOIORegs *tr) 43 { 44 int ticks = tr->tco.tmr & TCO_TMR_MASK; 45 int64_t nsec = (int64_t)ticks * TCO_TICK_NSEC; 46 47 trace_tco_timer_reload(ticks, nsec / 1000000); 48 tr->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + nsec; 49 timer_mod(tr->tco_timer, tr->expire_time); 50 } 51 52 static inline void tco_timer_stop(TCOIORegs *tr) 53 { 54 tr->expire_time = -1; 55 timer_del(tr->tco_timer); 56 } 57 58 static void tco_timer_expired(void *opaque) 59 { 60 TCOIORegs *tr = opaque; 61 ICH9LPCPMRegs *pm = container_of(tr, ICH9LPCPMRegs, tco_regs); 62 ICH9LPCState *lpc = container_of(pm, ICH9LPCState, pm); 63 uint32_t gcs = pci_get_long(lpc->chip_config + ICH9_CC_GCS); 64 65 trace_tco_timer_expired(tr->timeouts_no, 66 lpc->pin_strap.spkr_hi, 67 !!(gcs & ICH9_CC_GCS_NO_REBOOT)); 68 tr->tco.rld = 0; 69 tr->tco.sts1 |= TCO_TIMEOUT; 70 if (++tr->timeouts_no == 2) { 71 tr->tco.sts2 |= TCO_SECOND_TO_STS; 72 tr->tco.sts2 |= TCO_BOOT_STS; 73 tr->timeouts_no = 0; 74 75 if (!lpc->pin_strap.spkr_hi && !(gcs & ICH9_CC_GCS_NO_REBOOT)) { 76 watchdog_perform_action(); 77 tco_timer_stop(tr); 78 return; 79 } 80 } 81 82 if (pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN) { 83 ich9_generate_smi(); 84 } 85 tr->tco.rld = tr->tco.tmr; 86 tco_timer_reload(tr); 87 } 88 89 /* NOTE: values of 0 or 1 will be ignored by ICH */ 90 static inline int can_start_tco_timer(TCOIORegs *tr) 91 { 92 return !(tr->tco.cnt1 & TCO_TMR_HLT) && tr->tco.tmr > 1; 93 } 94 95 static uint32_t tco_ioport_readw(TCOIORegs *tr, uint32_t addr) 96 { 97 uint16_t rld; 98 99 switch (addr) { 100 case TCO_RLD: 101 if (tr->expire_time != -1) { 102 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 103 int64_t elapsed = (tr->expire_time - now) / TCO_TICK_NSEC; 104 rld = (uint16_t)elapsed | (tr->tco.rld & ~TCO_RLD_MASK); 105 } else { 106 rld = tr->tco.rld; 107 } 108 return rld; 109 case TCO_DAT_IN: 110 return tr->tco.din; 111 case TCO_DAT_OUT: 112 return tr->tco.dout; 113 case TCO1_STS: 114 return tr->tco.sts1; 115 case TCO2_STS: 116 return tr->tco.sts2; 117 case TCO1_CNT: 118 return tr->tco.cnt1; 119 case TCO2_CNT: 120 return tr->tco.cnt2; 121 case TCO_MESSAGE1: 122 return tr->tco.msg1; 123 case TCO_MESSAGE2: 124 return tr->tco.msg2; 125 case TCO_WDCNT: 126 return tr->tco.wdcnt; 127 case TCO_TMR: 128 return tr->tco.tmr; 129 case SW_IRQ_GEN: 130 return tr->sw_irq_gen; 131 } 132 return 0; 133 } 134 135 static void tco_ioport_writew(TCOIORegs *tr, uint32_t addr, uint32_t val) 136 { 137 switch (addr) { 138 case TCO_RLD: 139 tr->timeouts_no = 0; 140 if (can_start_tco_timer(tr)) { 141 tr->tco.rld = tr->tco.tmr; 142 tco_timer_reload(tr); 143 } else { 144 tr->tco.rld = val; 145 } 146 break; 147 case TCO_DAT_IN: 148 tr->tco.din = val; 149 tr->tco.sts1 |= SW_TCO_SMI; 150 ich9_generate_smi(); 151 break; 152 case TCO_DAT_OUT: 153 tr->tco.dout = val; 154 tr->tco.sts1 |= TCO_INT_STS; 155 /* TODO: cause an interrupt, as selected by the TCO_INT_SEL bits */ 156 break; 157 case TCO1_STS: 158 tr->tco.sts1 = val & TCO1_STS_MASK; 159 break; 160 case TCO2_STS: 161 tr->tco.sts2 = val & TCO2_STS_MASK; 162 break; 163 case TCO1_CNT: 164 val &= TCO1_CNT_MASK; 165 /* 166 * once TCO_LOCK bit is set, it can not be cleared by software. a reset 167 * is required to change this bit from 1 to 0 -- it defaults to 0. 168 */ 169 tr->tco.cnt1 = val | (tr->tco.cnt1 & TCO_LOCK); 170 if (can_start_tco_timer(tr)) { 171 tr->tco.rld = tr->tco.tmr; 172 tco_timer_reload(tr); 173 } else { 174 tco_timer_stop(tr); 175 } 176 break; 177 case TCO2_CNT: 178 tr->tco.cnt2 = val; 179 break; 180 case TCO_MESSAGE1: 181 tr->tco.msg1 = val; 182 break; 183 case TCO_MESSAGE2: 184 tr->tco.msg2 = val; 185 break; 186 case TCO_WDCNT: 187 tr->tco.wdcnt = val; 188 break; 189 case TCO_TMR: 190 tr->tco.tmr = val; 191 break; 192 case SW_IRQ_GEN: 193 tr->sw_irq_gen = val; 194 break; 195 } 196 } 197 198 static uint64_t tco_io_readw(void *opaque, hwaddr addr, unsigned width) 199 { 200 TCOIORegs *tr = opaque; 201 return tco_ioport_readw(tr, addr); 202 } 203 204 static void tco_io_writew(void *opaque, hwaddr addr, uint64_t val, 205 unsigned width) 206 { 207 TCOIORegs *tr = opaque; 208 tco_ioport_writew(tr, addr, val); 209 } 210 211 static const MemoryRegionOps tco_io_ops = { 212 .read = tco_io_readw, 213 .write = tco_io_writew, 214 .valid.min_access_size = 1, 215 .valid.max_access_size = 4, 216 .impl.min_access_size = 1, 217 .impl.max_access_size = 2, 218 .endianness = DEVICE_LITTLE_ENDIAN, 219 }; 220 221 void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent) 222 { 223 *tr = (TCOIORegs) { 224 .tco = { 225 .rld = TCO_RLD_DEFAULT, 226 .din = TCO_DAT_IN_DEFAULT, 227 .dout = TCO_DAT_OUT_DEFAULT, 228 .sts1 = TCO1_STS_DEFAULT, 229 .sts2 = TCO2_STS_DEFAULT, 230 .cnt1 = TCO1_CNT_DEFAULT, 231 .cnt2 = TCO2_CNT_DEFAULT, 232 .msg1 = TCO_MESSAGE1_DEFAULT, 233 .msg2 = TCO_MESSAGE2_DEFAULT, 234 .wdcnt = TCO_WDCNT_DEFAULT, 235 .tmr = TCO_TMR_DEFAULT, 236 }, 237 .sw_irq_gen = SW_IRQ_GEN_DEFAULT, 238 .tco_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tco_timer_expired, tr), 239 .expire_time = -1, 240 .timeouts_no = 0, 241 }; 242 memory_region_init_io(&tr->io, memory_region_owner(parent), 243 &tco_io_ops, tr, "sm-tco", ICH9_PMIO_TCO_LEN); 244 memory_region_add_subregion(parent, ICH9_PMIO_TCO_RLD, &tr->io); 245 } 246 247 const VMStateDescription vmstate_tco_io_sts = { 248 .name = "tco io device status", 249 .version_id = 1, 250 .minimum_version_id = 1, 251 .minimum_version_id_old = 1, 252 .fields = (VMStateField[]) { 253 VMSTATE_UINT16(tco.rld, TCOIORegs), 254 VMSTATE_UINT8(tco.din, TCOIORegs), 255 VMSTATE_UINT8(tco.dout, TCOIORegs), 256 VMSTATE_UINT16(tco.sts1, TCOIORegs), 257 VMSTATE_UINT16(tco.sts2, TCOIORegs), 258 VMSTATE_UINT16(tco.cnt1, TCOIORegs), 259 VMSTATE_UINT16(tco.cnt2, TCOIORegs), 260 VMSTATE_UINT8(tco.msg1, TCOIORegs), 261 VMSTATE_UINT8(tco.msg2, TCOIORegs), 262 VMSTATE_UINT8(tco.wdcnt, TCOIORegs), 263 VMSTATE_UINT16(tco.tmr, TCOIORegs), 264 VMSTATE_UINT8(sw_irq_gen, TCOIORegs), 265 VMSTATE_TIMER_PTR(tco_timer, TCOIORegs), 266 VMSTATE_INT64(expire_time, TCOIORegs), 267 VMSTATE_UINT8(timeouts_no, TCOIORegs), 268 VMSTATE_END_OF_LIST() 269 } 270 }; 271