xref: /qemu/docs/specs/pvpanic.rst (revision 945f3fd4e46405ed37b035922eebe2bfad6bc11e)
1b42ffe60SHu TaoPVPANIC DEVICE
2b42ffe60SHu Tao==============
3b42ffe60SHu Tao
4cb2cc206SMihai Carabaspvpanic device is a simulated device, through which a guest panic
5b42ffe60SHu Taoevent is sent to qemu, and a QMP event is generated. This allows
6b42ffe60SHu Taomanagement apps (e.g. libvirt) to be notified and respond to the event.
7b42ffe60SHu Tao
8b42ffe60SHu TaoThe management app has the option of waiting for GUEST_PANICKED events,
9b42ffe60SHu Taoand/or polling for guest-panicked RunState, to learn when the pvpanic
10b42ffe60SHu Taodevice has fired a panic event.
11b42ffe60SHu Tao
12cb2cc206SMihai CarabasThe pvpanic device can be implemented as an ISA device (using IOPORT) or as a
13cb2cc206SMihai CarabasPCI device.
14cb2cc206SMihai Carabas
15b42ffe60SHu TaoISA Interface
16b42ffe60SHu Tao-------------
17b42ffe60SHu Tao
18b42ffe60SHu Taopvpanic exposes a single I/O port, by default 0x505. On read, the bits
19b42ffe60SHu Taorecognized by the device are set. Software should ignore bits it doesn't
20b42ffe60SHu Taorecognize. On write, the bits not recognized by the device are ignored.
21b42ffe60SHu TaoSoftware should set only bits both itself and the device recognize.
22600d7b47Szhenwei pi
23600d7b47Szhenwei piBit Definition
24*945f3fd4SPeter Maydell~~~~~~~~~~~~~~
25*945f3fd4SPeter Maydell
26*945f3fd4SPeter Maydellbit 0
27*945f3fd4SPeter Maydell  a guest panic has happened and should be processed by the host
28*945f3fd4SPeter Maydellbit 1
29*945f3fd4SPeter Maydell  a guest panic has happened and will be handled by the guest;
307dc58deeSzhenwei pi  the host should record it or report it, but should not affect
317dc58deeSzhenwei pi  the execution of the guest.
32b42ffe60SHu Tao
33cb2cc206SMihai CarabasPCI Interface
34cb2cc206SMihai Carabas-------------
35cb2cc206SMihai Carabas
36cb2cc206SMihai CarabasThe PCI interface is similar to the ISA interface except that it uses an MMIO
37cb2cc206SMihai Carabasaddress space provided by its BAR0, 1 byte long. Any machine with a PCI bus
38*945f3fd4SPeter Maydellcan enable a pvpanic device by adding ``-device pvpanic-pci`` to the command
39cb2cc206SMihai Carabasline.
40cb2cc206SMihai Carabas
41b42ffe60SHu TaoACPI Interface
42b42ffe60SHu Tao--------------
43b42ffe60SHu Tao
44b42ffe60SHu Taopvpanic device is defined with ACPI ID "QEMU0001". Custom methods:
45b42ffe60SHu Tao
46*945f3fd4SPeter MaydellRDPT
47*945f3fd4SPeter Maydell~~~~
48b42ffe60SHu Tao
49*945f3fd4SPeter MaydellTo determine whether guest panic notification is supported.
50*945f3fd4SPeter Maydell
51*945f3fd4SPeter MaydellArguments
52*945f3fd4SPeter Maydell  None
53*945f3fd4SPeter MaydellReturn
54*945f3fd4SPeter Maydell  Returns a byte, with the same semantics as the I/O port interface.
55*945f3fd4SPeter Maydell
56*945f3fd4SPeter MaydellWRPT
57*945f3fd4SPeter Maydell~~~~
58*945f3fd4SPeter Maydell
59*945f3fd4SPeter MaydellTo send a guest panic event.
60*945f3fd4SPeter Maydell
61*945f3fd4SPeter MaydellArguments
62*945f3fd4SPeter Maydell  Arg0 is a byte to be written, with the same semantics as the I/O interface.
63*945f3fd4SPeter MaydellReturn
64*945f3fd4SPeter Maydell  None
65b42ffe60SHu Tao
66b42ffe60SHu TaoThe ACPI device will automatically refer to the right port in case it
67b42ffe60SHu Taois modified.
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