xref: /qemu/accel/tcg/translate-all.c (revision 68df8c8dba57f539d24f1a92a8699a179d9bb6fb)
1 /*
2  *  Host code generation
3  *
4  *  Copyright (c) 2003 Fabrice Bellard
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 
22 #include "trace.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg.h"
26 #if defined(CONFIG_USER_ONLY)
27 #include "qemu.h"
28 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
29 #include <sys/param.h>
30 #if __FreeBSD_version >= 700104
31 #define HAVE_KINFO_GETVMMAP
32 #define sigqueue sigqueue_freebsd  /* avoid redefinition */
33 #include <sys/proc.h>
34 #include <machine/profile.h>
35 #define _KERNEL
36 #include <sys/user.h>
37 #undef _KERNEL
38 #undef sigqueue
39 #include <libutil.h>
40 #endif
41 #endif
42 #else
43 #include "exec/ram_addr.h"
44 #endif
45 
46 #include "exec/cputlb.h"
47 #include "exec/page-protection.h"
48 #include "tb-internal.h"
49 #include "exec/translator.h"
50 #include "exec/tb-flush.h"
51 #include "qemu/bitmap.h"
52 #include "qemu/qemu-print.h"
53 #include "qemu/main-loop.h"
54 #include "qemu/cacheinfo.h"
55 #include "qemu/timer.h"
56 #include "exec/log.h"
57 #include "system/cpus.h"
58 #include "system/cpu-timers.h"
59 #include "system/tcg.h"
60 #include "qapi/error.h"
61 #include "hw/core/tcg-cpu-ops.h"
62 #include "tb-jmp-cache.h"
63 #include "tb-hash.h"
64 #include "tb-context.h"
65 #include "tb-internal.h"
66 #include "internal-common.h"
67 #include "internal-target.h"
68 #include "tcg/perf.h"
69 #include "tcg/insn-start-words.h"
70 
71 TBContext tb_ctx;
72 
73 /*
74  * Encode VAL as a signed leb128 sequence at P.
75  * Return P incremented past the encoded value.
76  */
77 static uint8_t *encode_sleb128(uint8_t *p, int64_t val)
78 {
79     int more, byte;
80 
81     do {
82         byte = val & 0x7f;
83         val >>= 7;
84         more = !((val == 0 && (byte & 0x40) == 0)
85                  || (val == -1 && (byte & 0x40) != 0));
86         if (more) {
87             byte |= 0x80;
88         }
89         *p++ = byte;
90     } while (more);
91 
92     return p;
93 }
94 
95 /*
96  * Decode a signed leb128 sequence at *PP; increment *PP past the
97  * decoded value.  Return the decoded value.
98  */
99 static int64_t decode_sleb128(const uint8_t **pp)
100 {
101     const uint8_t *p = *pp;
102     int64_t val = 0;
103     int byte, shift = 0;
104 
105     do {
106         byte = *p++;
107         val |= (int64_t)(byte & 0x7f) << shift;
108         shift += 7;
109     } while (byte & 0x80);
110     if (shift < TARGET_LONG_BITS && (byte & 0x40)) {
111         val |= -(int64_t)1 << shift;
112     }
113 
114     *pp = p;
115     return val;
116 }
117 
118 /* Encode the data collected about the instructions while compiling TB.
119    Place the data at BLOCK, and return the number of bytes consumed.
120 
121    The logical table consists of TARGET_INSN_START_WORDS target_ulong's,
122    which come from the target's insn_start data, followed by a uintptr_t
123    which comes from the host pc of the end of the code implementing the insn.
124 
125    Each line of the table is encoded as sleb128 deltas from the previous
126    line.  The seed for the first line is { tb->pc, 0..., tb->tc.ptr }.
127    That is, the first column is seeded with the guest pc, the last column
128    with the host pc, and the middle columns with zeros.  */
129 
130 static int encode_search(TranslationBlock *tb, uint8_t *block)
131 {
132     uint8_t *highwater = tcg_ctx->code_gen_highwater;
133     uint64_t *insn_data = tcg_ctx->gen_insn_data;
134     uint16_t *insn_end_off = tcg_ctx->gen_insn_end_off;
135     uint8_t *p = block;
136     int i, j, n;
137 
138     for (i = 0, n = tb->icount; i < n; ++i) {
139         uint64_t prev, curr;
140 
141         for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
142             if (i == 0) {
143                 prev = (!(tb_cflags(tb) & CF_PCREL) && j == 0 ? tb->pc : 0);
144             } else {
145                 prev = insn_data[(i - 1) * TARGET_INSN_START_WORDS + j];
146             }
147             curr = insn_data[i * TARGET_INSN_START_WORDS + j];
148             p = encode_sleb128(p, curr - prev);
149         }
150         prev = (i == 0 ? 0 : insn_end_off[i - 1]);
151         curr = insn_end_off[i];
152         p = encode_sleb128(p, curr - prev);
153 
154         /* Test for (pending) buffer overflow.  The assumption is that any
155            one row beginning below the high water mark cannot overrun
156            the buffer completely.  Thus we can test for overflow after
157            encoding a row without having to check during encoding.  */
158         if (unlikely(p > highwater)) {
159             return -1;
160         }
161     }
162 
163     return p - block;
164 }
165 
166 static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
167                                    uint64_t *data)
168 {
169     uintptr_t iter_pc = (uintptr_t)tb->tc.ptr;
170     const uint8_t *p = tb->tc.ptr + tb->tc.size;
171     int i, j, num_insns = tb->icount;
172 
173     host_pc -= GETPC_ADJ;
174 
175     if (host_pc < iter_pc) {
176         return -1;
177     }
178 
179     memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS);
180     if (!(tb_cflags(tb) & CF_PCREL)) {
181         data[0] = tb->pc;
182     }
183 
184     /*
185      * Reconstruct the stored insn data while looking for the point
186      * at which the end of the insn exceeds host_pc.
187      */
188     for (i = 0; i < num_insns; ++i) {
189         for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
190             data[j] += decode_sleb128(&p);
191         }
192         iter_pc += decode_sleb128(&p);
193         if (iter_pc > host_pc) {
194             return num_insns - i;
195         }
196     }
197     return -1;
198 }
199 
200 /*
201  * The cpu state corresponding to 'host_pc' is restored in
202  * preparation for exiting the TB.
203  */
204 void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
205                                uintptr_t host_pc)
206 {
207     uint64_t data[TARGET_INSN_START_WORDS];
208     int insns_left = cpu_unwind_data_from_tb(tb, host_pc, data);
209 
210     if (insns_left < 0) {
211         return;
212     }
213 
214     if (tb_cflags(tb) & CF_USE_ICOUNT) {
215         assert(icount_enabled());
216         /*
217          * Reset the cycle counter to the start of the block and
218          * shift if to the number of actually executed instructions.
219          */
220         cpu->neg.icount_decr.u16.low += insns_left;
221     }
222 
223     cpu->cc->tcg_ops->restore_state_to_opc(cpu, tb, data);
224 }
225 
226 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc)
227 {
228     /*
229      * The host_pc has to be in the rx region of the code buffer.
230      * If it is not we will not be able to resolve it here.
231      * The two cases where host_pc will not be correct are:
232      *
233      *  - fault during translation (instruction fetch)
234      *  - fault from helper (not using GETPC() macro)
235      *
236      * Either way we need return early as we can't resolve it here.
237      */
238     if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) {
239         TranslationBlock *tb = tcg_tb_lookup(host_pc);
240         if (tb) {
241             cpu_restore_state_from_tb(cpu, tb, host_pc);
242             return true;
243         }
244     }
245     return false;
246 }
247 
248 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data)
249 {
250     if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) {
251         TranslationBlock *tb = tcg_tb_lookup(host_pc);
252         if (tb) {
253             return cpu_unwind_data_from_tb(tb, host_pc, data) >= 0;
254         }
255     }
256     return false;
257 }
258 
259 void page_init(void)
260 {
261     page_table_config_init();
262 }
263 
264 /*
265  * Isolate the portion of code gen which can setjmp/longjmp.
266  * Return the size of the generated code, or negative on error.
267  */
268 static int setjmp_gen_code(CPUArchState *env, TranslationBlock *tb,
269                            vaddr pc, void *host_pc,
270                            int *max_insns, int64_t *ti)
271 {
272     int ret = sigsetjmp(tcg_ctx->jmp_trans, 0);
273     if (unlikely(ret != 0)) {
274         return ret;
275     }
276 
277     tcg_func_start(tcg_ctx);
278 
279     tcg_ctx->cpu = env_cpu(env);
280     gen_intermediate_code(env_cpu(env), tb, max_insns, pc, host_pc);
281     assert(tb->size != 0);
282     tcg_ctx->cpu = NULL;
283     *max_insns = tb->icount;
284 
285     return tcg_gen_code(tcg_ctx, tb, pc);
286 }
287 
288 /* Called with mmap_lock held for user mode emulation.  */
289 TranslationBlock *tb_gen_code(CPUState *cpu,
290                               vaddr pc, uint64_t cs_base,
291                               uint32_t flags, int cflags)
292 {
293     CPUArchState *env = cpu_env(cpu);
294     TranslationBlock *tb, *existing_tb;
295     tb_page_addr_t phys_pc, phys_p2;
296     tcg_insn_unit *gen_code_buf;
297     int gen_code_size, search_size, max_insns;
298     int64_t ti;
299     void *host_pc;
300 
301     assert_memory_lock();
302     qemu_thread_jit_write();
303 
304     phys_pc = get_page_addr_code_hostp(env, pc, &host_pc);
305 
306     if (phys_pc == -1) {
307         /* Generate a one-shot TB with 1 insn in it */
308         cflags = (cflags & ~CF_COUNT_MASK) | 1;
309     }
310 
311     max_insns = cflags & CF_COUNT_MASK;
312     if (max_insns == 0) {
313         max_insns = TCG_MAX_INSNS;
314     }
315     QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 != TCG_MAX_INSNS);
316 
317  buffer_overflow:
318     assert_no_pages_locked();
319     tb = tcg_tb_alloc(tcg_ctx);
320     if (unlikely(!tb)) {
321         /* flush must be done */
322         tb_flush(cpu);
323         mmap_unlock();
324         /* Make the execution loop process the flush as soon as possible.  */
325         cpu->exception_index = EXCP_INTERRUPT;
326         cpu_loop_exit(cpu);
327     }
328 
329     gen_code_buf = tcg_ctx->code_gen_ptr;
330     tb->tc.ptr = tcg_splitwx_to_rx(gen_code_buf);
331     if (!(cflags & CF_PCREL)) {
332         tb->pc = pc;
333     }
334     tb->cs_base = cs_base;
335     tb->flags = flags;
336     tb->cflags = cflags;
337     tb_set_page_addr0(tb, phys_pc);
338     tb_set_page_addr1(tb, -1);
339     if (phys_pc != -1) {
340         tb_lock_page0(phys_pc);
341     }
342 
343     tcg_ctx->gen_tb = tb;
344     tcg_ctx->addr_type = TARGET_LONG_BITS == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64;
345 #ifdef CONFIG_SOFTMMU
346     tcg_ctx->page_bits = TARGET_PAGE_BITS;
347     tcg_ctx->page_mask = TARGET_PAGE_MASK;
348     tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS;
349 #endif
350     tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;
351 #ifdef TCG_GUEST_DEFAULT_MO
352     tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO;
353 #else
354     tcg_ctx->guest_mo = TCG_MO_ALL;
355 #endif
356 
357  restart_translate:
358     trace_translate_block(tb, pc, tb->tc.ptr);
359 
360     gen_code_size = setjmp_gen_code(env, tb, pc, host_pc, &max_insns, &ti);
361     if (unlikely(gen_code_size < 0)) {
362         switch (gen_code_size) {
363         case -1:
364             /*
365              * Overflow of code_gen_buffer, or the current slice of it.
366              *
367              * TODO: We don't need to re-do gen_intermediate_code, nor
368              * should we re-do the tcg optimization currently hidden
369              * inside tcg_gen_code.  All that should be required is to
370              * flush the TBs, allocate a new TB, re-initialize it per
371              * above, and re-do the actual code generation.
372              */
373             qemu_log_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT,
374                           "Restarting code generation for "
375                           "code_gen_buffer overflow\n");
376             tb_unlock_pages(tb);
377             tcg_ctx->gen_tb = NULL;
378             goto buffer_overflow;
379 
380         case -2:
381             /*
382              * The code generated for the TranslationBlock is too large.
383              * The maximum size allowed by the unwind info is 64k.
384              * There may be stricter constraints from relocations
385              * in the tcg backend.
386              *
387              * Try again with half as many insns as we attempted this time.
388              * If a single insn overflows, there's a bug somewhere...
389              */
390             assert(max_insns > 1);
391             max_insns /= 2;
392             qemu_log_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT,
393                           "Restarting code generation with "
394                           "smaller translation block (max %d insns)\n",
395                           max_insns);
396 
397             /*
398              * The half-sized TB may not cross pages.
399              * TODO: Fix all targets that cross pages except with
400              * the first insn, at which point this can't be reached.
401              */
402             phys_p2 = tb_page_addr1(tb);
403             if (unlikely(phys_p2 != -1)) {
404                 tb_unlock_page1(phys_pc, phys_p2);
405                 tb_set_page_addr1(tb, -1);
406             }
407             goto restart_translate;
408 
409         case -3:
410             /*
411              * We had a page lock ordering problem.  In order to avoid
412              * deadlock we had to drop the lock on page0, which means
413              * that everything we translated so far is compromised.
414              * Restart with locks held on both pages.
415              */
416             qemu_log_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT,
417                           "Restarting code generation with re-locked pages");
418             goto restart_translate;
419 
420         default:
421             g_assert_not_reached();
422         }
423     }
424     tcg_ctx->gen_tb = NULL;
425 
426     search_size = encode_search(tb, (void *)gen_code_buf + gen_code_size);
427     if (unlikely(search_size < 0)) {
428         tb_unlock_pages(tb);
429         goto buffer_overflow;
430     }
431     tb->tc.size = gen_code_size;
432 
433     /*
434      * For CF_PCREL, attribute all executions of the generated code
435      * to its first mapping.
436      */
437     perf_report_code(pc, tb, tcg_splitwx_to_rx(gen_code_buf));
438 
439     if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) &&
440         qemu_log_in_addr_range(pc)) {
441         FILE *logfile = qemu_log_trylock();
442         if (logfile) {
443             int code_size, data_size;
444             const tcg_target_ulong *rx_data_gen_ptr;
445             size_t chunk_start;
446             int insn = 0;
447 
448             if (tcg_ctx->data_gen_ptr) {
449                 rx_data_gen_ptr = tcg_splitwx_to_rx(tcg_ctx->data_gen_ptr);
450                 code_size = (const void *)rx_data_gen_ptr - tb->tc.ptr;
451                 data_size = gen_code_size - code_size;
452             } else {
453                 rx_data_gen_ptr = 0;
454                 code_size = gen_code_size;
455                 data_size = 0;
456             }
457 
458             /* Dump header and the first instruction */
459             fprintf(logfile, "OUT: [size=%d]\n", gen_code_size);
460             fprintf(logfile,
461                     "  -- guest addr 0x%016" PRIx64 " + tb prologue\n",
462                     tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]);
463             chunk_start = tcg_ctx->gen_insn_end_off[insn];
464             disas(logfile, tb->tc.ptr, chunk_start);
465 
466             /*
467              * Dump each instruction chunk, wrapping up empty chunks into
468              * the next instruction. The whole array is offset so the
469              * first entry is the beginning of the 2nd instruction.
470              */
471             while (insn < tb->icount) {
472                 size_t chunk_end = tcg_ctx->gen_insn_end_off[insn];
473                 if (chunk_end > chunk_start) {
474                     fprintf(logfile, "  -- guest addr 0x%016" PRIx64 "\n",
475                             tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]);
476                     disas(logfile, tb->tc.ptr + chunk_start,
477                           chunk_end - chunk_start);
478                     chunk_start = chunk_end;
479                 }
480                 insn++;
481             }
482 
483             if (chunk_start < code_size) {
484                 fprintf(logfile, "  -- tb slow paths + alignment\n");
485                 disas(logfile, tb->tc.ptr + chunk_start,
486                       code_size - chunk_start);
487             }
488 
489             /* Finally dump any data we may have after the block */
490             if (data_size) {
491                 int i;
492                 fprintf(logfile, "  data: [size=%d]\n", data_size);
493                 for (i = 0; i < data_size / sizeof(tcg_target_ulong); i++) {
494                     if (sizeof(tcg_target_ulong) == 8) {
495                         fprintf(logfile,
496                                 "0x%08" PRIxPTR ":  .quad  0x%016" TCG_PRIlx "\n",
497                                 (uintptr_t)&rx_data_gen_ptr[i], rx_data_gen_ptr[i]);
498                     } else if (sizeof(tcg_target_ulong) == 4) {
499                         fprintf(logfile,
500                                 "0x%08" PRIxPTR ":  .long  0x%08" TCG_PRIlx "\n",
501                                 (uintptr_t)&rx_data_gen_ptr[i], rx_data_gen_ptr[i]);
502                     } else {
503                         qemu_build_not_reached();
504                     }
505                 }
506             }
507             fprintf(logfile, "\n");
508             qemu_log_unlock(logfile);
509         }
510     }
511 
512     qatomic_set(&tcg_ctx->code_gen_ptr, (void *)
513         ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size,
514                  CODE_GEN_ALIGN));
515 
516     /* init jump list */
517     qemu_spin_init(&tb->jmp_lock);
518     tb->jmp_list_head = (uintptr_t)NULL;
519     tb->jmp_list_next[0] = (uintptr_t)NULL;
520     tb->jmp_list_next[1] = (uintptr_t)NULL;
521     tb->jmp_dest[0] = (uintptr_t)NULL;
522     tb->jmp_dest[1] = (uintptr_t)NULL;
523 
524     /* init original jump addresses which have been set during tcg_gen_code() */
525     if (tb->jmp_reset_offset[0] != TB_JMP_OFFSET_INVALID) {
526         tb_reset_jump(tb, 0);
527     }
528     if (tb->jmp_reset_offset[1] != TB_JMP_OFFSET_INVALID) {
529         tb_reset_jump(tb, 1);
530     }
531 
532     /*
533      * If the TB is not associated with a physical RAM page then it must be
534      * a temporary one-insn TB, and we have nothing left to do. Return early
535      * before attempting to link to other TBs or add to the lookup table.
536      */
537     if (tb_page_addr0(tb) == -1) {
538         assert_no_pages_locked();
539         return tb;
540     }
541 
542     /*
543      * Insert TB into the corresponding region tree before publishing it
544      * through QHT. Otherwise rewinding happened in the TB might fail to
545      * lookup itself using host PC.
546      */
547     tcg_tb_insert(tb);
548 
549     /*
550      * No explicit memory barrier is required -- tb_link_page() makes the
551      * TB visible in a consistent state.
552      */
553     existing_tb = tb_link_page(tb);
554     assert_no_pages_locked();
555 
556     /* if the TB already exists, discard what we just translated */
557     if (unlikely(existing_tb != tb)) {
558         uintptr_t orig_aligned = (uintptr_t)gen_code_buf;
559 
560         orig_aligned -= ROUND_UP(sizeof(*tb), qemu_icache_linesize);
561         qatomic_set(&tcg_ctx->code_gen_ptr, (void *)orig_aligned);
562         tcg_tb_remove(tb);
563         return existing_tb;
564     }
565     return tb;
566 }
567 
568 /* user-mode: call with mmap_lock held */
569 void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr)
570 {
571     TranslationBlock *tb;
572 
573     assert_memory_lock();
574 
575     tb = tcg_tb_lookup(retaddr);
576     if (tb) {
577         /* We can use retranslation to find the PC.  */
578         cpu_restore_state_from_tb(cpu, tb, retaddr);
579         tb_phys_invalidate(tb, -1);
580     } else {
581         /* The exception probably happened in a helper.  The CPU state should
582            have been saved before calling it. Fetch the PC from there.  */
583         CPUArchState *env = cpu_env(cpu);
584         vaddr pc;
585         uint64_t cs_base;
586         tb_page_addr_t addr;
587         uint32_t flags;
588 
589         cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
590         addr = get_page_addr_code(env, pc);
591         if (addr != -1) {
592             tb_invalidate_phys_range(addr, addr);
593         }
594     }
595 }
596 
597 #ifndef CONFIG_USER_ONLY
598 /*
599  * In deterministic execution mode, instructions doing device I/Os
600  * must be at the end of the TB.
601  *
602  * Called by softmmu_template.h, with iothread mutex not held.
603  */
604 void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
605 {
606     TranslationBlock *tb;
607     CPUClass *cc;
608     uint32_t n;
609 
610     tb = tcg_tb_lookup(retaddr);
611     if (!tb) {
612         cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p",
613                   (void *)retaddr);
614     }
615     cpu_restore_state_from_tb(cpu, tb, retaddr);
616 
617     /*
618      * Some guests must re-execute the branch when re-executing a delay
619      * slot instruction.  When this is the case, adjust icount and N
620      * to account for the re-execution of the branch.
621      */
622     n = 1;
623     cc = CPU_GET_CLASS(cpu);
624     if (cc->tcg_ops->io_recompile_replay_branch &&
625         cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) {
626         cpu->neg.icount_decr.u16.low++;
627         n = 2;
628     }
629 
630     /*
631      * Exit the loop and potentially generate a new TB executing the
632      * just the I/O insns. We also limit instrumentation to memory
633      * operations only (which execute after completion) so we don't
634      * double instrument the instruction.
635      */
636     cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | n;
637 
638     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
639         vaddr pc = cpu->cc->get_pc(cpu);
640         if (qemu_log_in_addr_range(pc)) {
641             qemu_log("cpu_io_recompile: rewound execution of TB to %016"
642                      VADDR_PRIx "\n", pc);
643         }
644     }
645 
646     cpu_loop_exit_noexc(cpu);
647 }
648 
649 #endif /* CONFIG_USER_ONLY */
650 
651 /*
652  * Called by generic code at e.g. cpu reset after cpu creation,
653  * therefore we must be prepared to allocate the jump cache.
654  */
655 void tcg_flush_jmp_cache(CPUState *cpu)
656 {
657     CPUJumpCache *jc = cpu->tb_jmp_cache;
658 
659     /* During early initialization, the cache may not yet be allocated. */
660     if (unlikely(jc == NULL)) {
661         return;
662     }
663 
664     for (int i = 0; i < TB_JMP_CACHE_SIZE; i++) {
665         qatomic_set(&jc->array[i].tb, NULL);
666     }
667 }
668