1 /* 2 * Host code generation 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 22 #include "trace.h" 23 #include "disas/disas.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg.h" 26 #if defined(CONFIG_USER_ONLY) 27 #include "qemu.h" 28 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) 29 #include <sys/param.h> 30 #if __FreeBSD_version >= 700104 31 #define HAVE_KINFO_GETVMMAP 32 #define sigqueue sigqueue_freebsd /* avoid redefinition */ 33 #include <sys/proc.h> 34 #include <machine/profile.h> 35 #define _KERNEL 36 #include <sys/user.h> 37 #undef _KERNEL 38 #undef sigqueue 39 #include <libutil.h> 40 #endif 41 #endif 42 #else 43 #include "system/ram_addr.h" 44 #endif 45 46 #include "cpu-param.h" 47 #include "exec/cputlb.h" 48 #include "exec/page-protection.h" 49 #include "exec/mmap-lock.h" 50 #include "tb-internal.h" 51 #include "tlb-bounds.h" 52 #include "exec/translator.h" 53 #include "exec/tb-flush.h" 54 #include "qemu/bitmap.h" 55 #include "qemu/qemu-print.h" 56 #include "qemu/main-loop.h" 57 #include "qemu/cacheinfo.h" 58 #include "qemu/timer.h" 59 #include "exec/log.h" 60 #include "exec/icount.h" 61 #include "system/tcg.h" 62 #include "qapi/error.h" 63 #include "accel/tcg/cpu-ops.h" 64 #include "tb-jmp-cache.h" 65 #include "tb-hash.h" 66 #include "tb-context.h" 67 #include "tb-internal.h" 68 #include "internal-common.h" 69 #include "internal-target.h" 70 #include "tcg/perf.h" 71 #include "tcg/insn-start-words.h" 72 #include "cpu.h" 73 74 TBContext tb_ctx; 75 76 /* 77 * Encode VAL as a signed leb128 sequence at P. 78 * Return P incremented past the encoded value. 79 */ 80 static uint8_t *encode_sleb128(uint8_t *p, int64_t val) 81 { 82 int more, byte; 83 84 do { 85 byte = val & 0x7f; 86 val >>= 7; 87 more = !((val == 0 && (byte & 0x40) == 0) 88 || (val == -1 && (byte & 0x40) != 0)); 89 if (more) { 90 byte |= 0x80; 91 } 92 *p++ = byte; 93 } while (more); 94 95 return p; 96 } 97 98 /* 99 * Decode a signed leb128 sequence at *PP; increment *PP past the 100 * decoded value. Return the decoded value. 101 */ 102 static int64_t decode_sleb128(const uint8_t **pp) 103 { 104 const uint8_t *p = *pp; 105 int64_t val = 0; 106 int byte, shift = 0; 107 108 do { 109 byte = *p++; 110 val |= (int64_t)(byte & 0x7f) << shift; 111 shift += 7; 112 } while (byte & 0x80); 113 if (shift < TARGET_LONG_BITS && (byte & 0x40)) { 114 val |= -(int64_t)1 << shift; 115 } 116 117 *pp = p; 118 return val; 119 } 120 121 /* Encode the data collected about the instructions while compiling TB. 122 Place the data at BLOCK, and return the number of bytes consumed. 123 124 The logical table consists of TARGET_INSN_START_WORDS target_ulong's, 125 which come from the target's insn_start data, followed by a uintptr_t 126 which comes from the host pc of the end of the code implementing the insn. 127 128 Each line of the table is encoded as sleb128 deltas from the previous 129 line. The seed for the first line is { tb->pc, 0..., tb->tc.ptr }. 130 That is, the first column is seeded with the guest pc, the last column 131 with the host pc, and the middle columns with zeros. */ 132 133 static int encode_search(TranslationBlock *tb, uint8_t *block) 134 { 135 uint8_t *highwater = tcg_ctx->code_gen_highwater; 136 uint64_t *insn_data = tcg_ctx->gen_insn_data; 137 uint16_t *insn_end_off = tcg_ctx->gen_insn_end_off; 138 uint8_t *p = block; 139 int i, j, n; 140 141 for (i = 0, n = tb->icount; i < n; ++i) { 142 uint64_t prev, curr; 143 144 for (j = 0; j < TARGET_INSN_START_WORDS; ++j) { 145 if (i == 0) { 146 prev = (!(tb_cflags(tb) & CF_PCREL) && j == 0 ? tb->pc : 0); 147 } else { 148 prev = insn_data[(i - 1) * TARGET_INSN_START_WORDS + j]; 149 } 150 curr = insn_data[i * TARGET_INSN_START_WORDS + j]; 151 p = encode_sleb128(p, curr - prev); 152 } 153 prev = (i == 0 ? 0 : insn_end_off[i - 1]); 154 curr = insn_end_off[i]; 155 p = encode_sleb128(p, curr - prev); 156 157 /* Test for (pending) buffer overflow. The assumption is that any 158 one row beginning below the high water mark cannot overrun 159 the buffer completely. Thus we can test for overflow after 160 encoding a row without having to check during encoding. */ 161 if (unlikely(p > highwater)) { 162 return -1; 163 } 164 } 165 166 return p - block; 167 } 168 169 static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc, 170 uint64_t *data) 171 { 172 uintptr_t iter_pc = (uintptr_t)tb->tc.ptr; 173 const uint8_t *p = tb->tc.ptr + tb->tc.size; 174 int i, j, num_insns = tb->icount; 175 176 host_pc -= GETPC_ADJ; 177 178 if (host_pc < iter_pc) { 179 return -1; 180 } 181 182 memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS); 183 if (!(tb_cflags(tb) & CF_PCREL)) { 184 data[0] = tb->pc; 185 } 186 187 /* 188 * Reconstruct the stored insn data while looking for the point 189 * at which the end of the insn exceeds host_pc. 190 */ 191 for (i = 0; i < num_insns; ++i) { 192 for (j = 0; j < TARGET_INSN_START_WORDS; ++j) { 193 data[j] += decode_sleb128(&p); 194 } 195 iter_pc += decode_sleb128(&p); 196 if (iter_pc > host_pc) { 197 return num_insns - i; 198 } 199 } 200 return -1; 201 } 202 203 /* 204 * The cpu state corresponding to 'host_pc' is restored in 205 * preparation for exiting the TB. 206 */ 207 void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, 208 uintptr_t host_pc) 209 { 210 uint64_t data[TARGET_INSN_START_WORDS]; 211 int insns_left = cpu_unwind_data_from_tb(tb, host_pc, data); 212 213 if (insns_left < 0) { 214 return; 215 } 216 217 if (tb_cflags(tb) & CF_USE_ICOUNT) { 218 assert(icount_enabled()); 219 /* 220 * Reset the cycle counter to the start of the block and 221 * shift if to the number of actually executed instructions. 222 */ 223 cpu->neg.icount_decr.u16.low += insns_left; 224 } 225 226 cpu->cc->tcg_ops->restore_state_to_opc(cpu, tb, data); 227 } 228 229 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc) 230 { 231 /* 232 * The host_pc has to be in the rx region of the code buffer. 233 * If it is not we will not be able to resolve it here. 234 * The two cases where host_pc will not be correct are: 235 * 236 * - fault during translation (instruction fetch) 237 * - fault from helper (not using GETPC() macro) 238 * 239 * Either way we need return early as we can't resolve it here. 240 */ 241 if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) { 242 TranslationBlock *tb = tcg_tb_lookup(host_pc); 243 if (tb) { 244 cpu_restore_state_from_tb(cpu, tb, host_pc); 245 return true; 246 } 247 } 248 return false; 249 } 250 251 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data) 252 { 253 if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) { 254 TranslationBlock *tb = tcg_tb_lookup(host_pc); 255 if (tb) { 256 return cpu_unwind_data_from_tb(tb, host_pc, data) >= 0; 257 } 258 } 259 return false; 260 } 261 262 void page_init(void) 263 { 264 page_table_config_init(); 265 } 266 267 /* 268 * Isolate the portion of code gen which can setjmp/longjmp. 269 * Return the size of the generated code, or negative on error. 270 */ 271 static int setjmp_gen_code(CPUArchState *env, TranslationBlock *tb, 272 vaddr pc, void *host_pc, 273 int *max_insns, int64_t *ti) 274 { 275 int ret = sigsetjmp(tcg_ctx->jmp_trans, 0); 276 if (unlikely(ret != 0)) { 277 return ret; 278 } 279 280 tcg_func_start(tcg_ctx); 281 282 CPUState *cs = env_cpu(env); 283 tcg_ctx->cpu = cs; 284 cs->cc->tcg_ops->translate_code(cs, tb, max_insns, pc, host_pc); 285 286 assert(tb->size != 0); 287 tcg_ctx->cpu = NULL; 288 *max_insns = tb->icount; 289 290 return tcg_gen_code(tcg_ctx, tb, pc); 291 } 292 293 /* Called with mmap_lock held for user mode emulation. */ 294 TranslationBlock *tb_gen_code(CPUState *cpu, 295 vaddr pc, uint64_t cs_base, 296 uint32_t flags, int cflags) 297 { 298 CPUArchState *env = cpu_env(cpu); 299 TranslationBlock *tb, *existing_tb; 300 tb_page_addr_t phys_pc, phys_p2; 301 tcg_insn_unit *gen_code_buf; 302 int gen_code_size, search_size, max_insns; 303 int64_t ti; 304 void *host_pc; 305 306 assert_memory_lock(); 307 qemu_thread_jit_write(); 308 309 phys_pc = get_page_addr_code_hostp(env, pc, &host_pc); 310 311 if (phys_pc == -1) { 312 /* Generate a one-shot TB with 1 insn in it */ 313 cflags = (cflags & ~CF_COUNT_MASK) | 1; 314 } 315 316 max_insns = cflags & CF_COUNT_MASK; 317 if (max_insns == 0) { 318 max_insns = TCG_MAX_INSNS; 319 } 320 QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 != TCG_MAX_INSNS); 321 322 buffer_overflow: 323 assert_no_pages_locked(); 324 tb = tcg_tb_alloc(tcg_ctx); 325 if (unlikely(!tb)) { 326 /* flush must be done */ 327 tb_flush(cpu); 328 mmap_unlock(); 329 /* Make the execution loop process the flush as soon as possible. */ 330 cpu->exception_index = EXCP_INTERRUPT; 331 cpu_loop_exit(cpu); 332 } 333 334 gen_code_buf = tcg_ctx->code_gen_ptr; 335 tb->tc.ptr = tcg_splitwx_to_rx(gen_code_buf); 336 if (!(cflags & CF_PCREL)) { 337 tb->pc = pc; 338 } 339 tb->cs_base = cs_base; 340 tb->flags = flags; 341 tb->cflags = cflags; 342 tb_set_page_addr0(tb, phys_pc); 343 tb_set_page_addr1(tb, -1); 344 if (phys_pc != -1) { 345 tb_lock_page0(phys_pc); 346 } 347 348 tcg_ctx->gen_tb = tb; 349 tcg_ctx->addr_type = TARGET_LONG_BITS == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64; 350 #ifdef CONFIG_SOFTMMU 351 tcg_ctx->page_bits = TARGET_PAGE_BITS; 352 tcg_ctx->page_mask = TARGET_PAGE_MASK; 353 tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS; 354 #endif 355 tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS; 356 #ifdef TCG_GUEST_DEFAULT_MO 357 tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO; 358 #else 359 tcg_ctx->guest_mo = TCG_MO_ALL; 360 #endif 361 362 restart_translate: 363 trace_translate_block(tb, pc, tb->tc.ptr); 364 365 gen_code_size = setjmp_gen_code(env, tb, pc, host_pc, &max_insns, &ti); 366 if (unlikely(gen_code_size < 0)) { 367 switch (gen_code_size) { 368 case -1: 369 /* 370 * Overflow of code_gen_buffer, or the current slice of it. 371 * 372 * TODO: We don't need to re-do tcg_ops->translate_code, nor 373 * should we re-do the tcg optimization currently hidden 374 * inside tcg_gen_code. All that should be required is to 375 * flush the TBs, allocate a new TB, re-initialize it per 376 * above, and re-do the actual code generation. 377 */ 378 qemu_log_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT, 379 "Restarting code generation for " 380 "code_gen_buffer overflow\n"); 381 tb_unlock_pages(tb); 382 tcg_ctx->gen_tb = NULL; 383 goto buffer_overflow; 384 385 case -2: 386 /* 387 * The code generated for the TranslationBlock is too large. 388 * The maximum size allowed by the unwind info is 64k. 389 * There may be stricter constraints from relocations 390 * in the tcg backend. 391 * 392 * Try again with half as many insns as we attempted this time. 393 * If a single insn overflows, there's a bug somewhere... 394 */ 395 assert(max_insns > 1); 396 max_insns /= 2; 397 qemu_log_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT, 398 "Restarting code generation with " 399 "smaller translation block (max %d insns)\n", 400 max_insns); 401 402 /* 403 * The half-sized TB may not cross pages. 404 * TODO: Fix all targets that cross pages except with 405 * the first insn, at which point this can't be reached. 406 */ 407 phys_p2 = tb_page_addr1(tb); 408 if (unlikely(phys_p2 != -1)) { 409 tb_unlock_page1(phys_pc, phys_p2); 410 tb_set_page_addr1(tb, -1); 411 } 412 goto restart_translate; 413 414 case -3: 415 /* 416 * We had a page lock ordering problem. In order to avoid 417 * deadlock we had to drop the lock on page0, which means 418 * that everything we translated so far is compromised. 419 * Restart with locks held on both pages. 420 */ 421 qemu_log_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT, 422 "Restarting code generation with re-locked pages"); 423 goto restart_translate; 424 425 default: 426 g_assert_not_reached(); 427 } 428 } 429 tcg_ctx->gen_tb = NULL; 430 431 search_size = encode_search(tb, (void *)gen_code_buf + gen_code_size); 432 if (unlikely(search_size < 0)) { 433 tb_unlock_pages(tb); 434 goto buffer_overflow; 435 } 436 tb->tc.size = gen_code_size; 437 438 /* 439 * For CF_PCREL, attribute all executions of the generated code 440 * to its first mapping. 441 */ 442 perf_report_code(pc, tb, tcg_splitwx_to_rx(gen_code_buf)); 443 444 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && 445 qemu_log_in_addr_range(pc)) { 446 FILE *logfile = qemu_log_trylock(); 447 if (logfile) { 448 int code_size, data_size; 449 const tcg_target_ulong *rx_data_gen_ptr; 450 size_t chunk_start; 451 int insn = 0; 452 453 if (tcg_ctx->data_gen_ptr) { 454 rx_data_gen_ptr = tcg_splitwx_to_rx(tcg_ctx->data_gen_ptr); 455 code_size = (const void *)rx_data_gen_ptr - tb->tc.ptr; 456 data_size = gen_code_size - code_size; 457 } else { 458 rx_data_gen_ptr = 0; 459 code_size = gen_code_size; 460 data_size = 0; 461 } 462 463 /* Dump header and the first instruction */ 464 fprintf(logfile, "OUT: [size=%d]\n", gen_code_size); 465 fprintf(logfile, 466 " -- guest addr 0x%016" PRIx64 " + tb prologue\n", 467 tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]); 468 chunk_start = tcg_ctx->gen_insn_end_off[insn]; 469 disas(logfile, tb->tc.ptr, chunk_start); 470 471 /* 472 * Dump each instruction chunk, wrapping up empty chunks into 473 * the next instruction. The whole array is offset so the 474 * first entry is the beginning of the 2nd instruction. 475 */ 476 while (insn < tb->icount) { 477 size_t chunk_end = tcg_ctx->gen_insn_end_off[insn]; 478 if (chunk_end > chunk_start) { 479 fprintf(logfile, " -- guest addr 0x%016" PRIx64 "\n", 480 tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]); 481 disas(logfile, tb->tc.ptr + chunk_start, 482 chunk_end - chunk_start); 483 chunk_start = chunk_end; 484 } 485 insn++; 486 } 487 488 if (chunk_start < code_size) { 489 fprintf(logfile, " -- tb slow paths + alignment\n"); 490 disas(logfile, tb->tc.ptr + chunk_start, 491 code_size - chunk_start); 492 } 493 494 /* Finally dump any data we may have after the block */ 495 if (data_size) { 496 int i; 497 fprintf(logfile, " data: [size=%d]\n", data_size); 498 for (i = 0; i < data_size / sizeof(tcg_target_ulong); i++) { 499 if (sizeof(tcg_target_ulong) == 8) { 500 fprintf(logfile, 501 "0x%08" PRIxPTR ": .quad 0x%016" TCG_PRIlx "\n", 502 (uintptr_t)&rx_data_gen_ptr[i], rx_data_gen_ptr[i]); 503 } else if (sizeof(tcg_target_ulong) == 4) { 504 fprintf(logfile, 505 "0x%08" PRIxPTR ": .long 0x%08" TCG_PRIlx "\n", 506 (uintptr_t)&rx_data_gen_ptr[i], rx_data_gen_ptr[i]); 507 } else { 508 qemu_build_not_reached(); 509 } 510 } 511 } 512 fprintf(logfile, "\n"); 513 qemu_log_unlock(logfile); 514 } 515 } 516 517 qatomic_set(&tcg_ctx->code_gen_ptr, (void *) 518 ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size, 519 CODE_GEN_ALIGN)); 520 521 /* init jump list */ 522 qemu_spin_init(&tb->jmp_lock); 523 tb->jmp_list_head = (uintptr_t)NULL; 524 tb->jmp_list_next[0] = (uintptr_t)NULL; 525 tb->jmp_list_next[1] = (uintptr_t)NULL; 526 tb->jmp_dest[0] = (uintptr_t)NULL; 527 tb->jmp_dest[1] = (uintptr_t)NULL; 528 529 /* init original jump addresses which have been set during tcg_gen_code() */ 530 if (tb->jmp_reset_offset[0] != TB_JMP_OFFSET_INVALID) { 531 tb_reset_jump(tb, 0); 532 } 533 if (tb->jmp_reset_offset[1] != TB_JMP_OFFSET_INVALID) { 534 tb_reset_jump(tb, 1); 535 } 536 537 /* 538 * Insert TB into the corresponding region tree before publishing it 539 * through QHT. Otherwise rewinding happened in the TB might fail to 540 * lookup itself using host PC. 541 */ 542 tcg_tb_insert(tb); 543 544 /* 545 * If the TB is not associated with a physical RAM page then it must be 546 * a temporary one-insn TB. 547 * 548 * Such TBs must be added to region trees in order to make sure that 549 * restore_state_to_opc() - which on some architectures is not limited to 550 * rewinding, but also affects exception handling! - is called when such a 551 * TB causes an exception. 552 * 553 * At the same time, temporary one-insn TBs must be executed at most once, 554 * because subsequent reads from, e.g., I/O memory may return different 555 * values. So return early before attempting to link to other TBs or add 556 * to the QHT. 557 */ 558 if (tb_page_addr0(tb) == -1) { 559 assert_no_pages_locked(); 560 return tb; 561 } 562 563 /* 564 * No explicit memory barrier is required -- tb_link_page() makes the 565 * TB visible in a consistent state. 566 */ 567 existing_tb = tb_link_page(tb); 568 assert_no_pages_locked(); 569 570 /* if the TB already exists, discard what we just translated */ 571 if (unlikely(existing_tb != tb)) { 572 uintptr_t orig_aligned = (uintptr_t)gen_code_buf; 573 574 orig_aligned -= ROUND_UP(sizeof(*tb), qemu_icache_linesize); 575 qatomic_set(&tcg_ctx->code_gen_ptr, (void *)orig_aligned); 576 tcg_tb_remove(tb); 577 return existing_tb; 578 } 579 return tb; 580 } 581 582 /* user-mode: call with mmap_lock held */ 583 void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr) 584 { 585 TranslationBlock *tb; 586 587 assert_memory_lock(); 588 589 tb = tcg_tb_lookup(retaddr); 590 if (tb) { 591 /* We can use retranslation to find the PC. */ 592 cpu_restore_state_from_tb(cpu, tb, retaddr); 593 tb_phys_invalidate(tb, -1); 594 } else { 595 /* The exception probably happened in a helper. The CPU state should 596 have been saved before calling it. Fetch the PC from there. */ 597 CPUArchState *env = cpu_env(cpu); 598 vaddr pc; 599 uint64_t cs_base; 600 tb_page_addr_t addr; 601 uint32_t flags; 602 603 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); 604 addr = get_page_addr_code(env, pc); 605 if (addr != -1) { 606 tb_invalidate_phys_range(addr, addr); 607 } 608 } 609 } 610 611 #ifndef CONFIG_USER_ONLY 612 /* 613 * In deterministic execution mode, instructions doing device I/Os 614 * must be at the end of the TB. 615 * 616 * Called by softmmu_template.h, with iothread mutex not held. 617 */ 618 void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) 619 { 620 TranslationBlock *tb; 621 CPUClass *cc; 622 uint32_t n; 623 624 tb = tcg_tb_lookup(retaddr); 625 if (!tb) { 626 cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p", 627 (void *)retaddr); 628 } 629 cpu_restore_state_from_tb(cpu, tb, retaddr); 630 631 /* 632 * Some guests must re-execute the branch when re-executing a delay 633 * slot instruction. When this is the case, adjust icount and N 634 * to account for the re-execution of the branch. 635 */ 636 n = 1; 637 cc = cpu->cc; 638 if (cc->tcg_ops->io_recompile_replay_branch && 639 cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) { 640 cpu->neg.icount_decr.u16.low++; 641 n = 2; 642 } 643 644 /* 645 * Exit the loop and potentially generate a new TB executing the 646 * just the I/O insns. We also limit instrumentation to memory 647 * operations only (which execute after completion) so we don't 648 * double instrument the instruction. Also don't let an IRQ sneak 649 * in before we execute it. 650 */ 651 cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | CF_NOIRQ | n; 652 653 if (qemu_loglevel_mask(CPU_LOG_EXEC)) { 654 vaddr pc = cpu->cc->get_pc(cpu); 655 if (qemu_log_in_addr_range(pc)) { 656 qemu_log("cpu_io_recompile: rewound execution of TB to %016" 657 VADDR_PRIx "\n", pc); 658 } 659 } 660 661 cpu_loop_exit_noexc(cpu); 662 } 663 664 #endif /* CONFIG_USER_ONLY */ 665 666 /* 667 * Called by generic code at e.g. cpu reset after cpu creation, 668 * therefore we must be prepared to allocate the jump cache. 669 */ 670 void tcg_flush_jmp_cache(CPUState *cpu) 671 { 672 CPUJumpCache *jc = cpu->tb_jmp_cache; 673 674 /* During early initialization, the cache may not yet be allocated. */ 675 if (unlikely(jc == NULL)) { 676 return; 677 } 678 679 for (int i = 0; i < TB_JMP_CACHE_SIZE; i++) { 680 qatomic_set(&jc->array[i].tb, NULL); 681 } 682 } 683