1 /* 2 * Host code generation 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 22 #include "trace.h" 23 #include "disas/disas.h" 24 #include "tcg/tcg.h" 25 #if defined(CONFIG_USER_ONLY) 26 #include "qemu.h" 27 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) 28 #include <sys/param.h> 29 #if __FreeBSD_version >= 700104 30 #define HAVE_KINFO_GETVMMAP 31 #define sigqueue sigqueue_freebsd /* avoid redefinition */ 32 #include <sys/proc.h> 33 #include <machine/profile.h> 34 #define _KERNEL 35 #include <sys/user.h> 36 #undef _KERNEL 37 #undef sigqueue 38 #include <libutil.h> 39 #endif 40 #endif 41 #else 42 #include "system/ram_addr.h" 43 #endif 44 45 #include "cpu-param.h" 46 #include "exec/cputlb.h" 47 #include "exec/page-protection.h" 48 #include "exec/mmap-lock.h" 49 #include "tb-internal.h" 50 #include "tlb-bounds.h" 51 #include "exec/translator.h" 52 #include "exec/tb-flush.h" 53 #include "qemu/bitmap.h" 54 #include "qemu/qemu-print.h" 55 #include "qemu/main-loop.h" 56 #include "qemu/cacheinfo.h" 57 #include "qemu/timer.h" 58 #include "exec/log.h" 59 #include "exec/icount.h" 60 #include "system/tcg.h" 61 #include "qapi/error.h" 62 #include "accel/tcg/cpu-ops.h" 63 #include "accel/tcg/getpc.h" 64 #include "tb-jmp-cache.h" 65 #include "tb-hash.h" 66 #include "tb-context.h" 67 #include "tb-internal.h" 68 #include "internal-common.h" 69 #include "tcg/perf.h" 70 #include "tcg/insn-start-words.h" 71 #include "cpu.h" 72 73 TBContext tb_ctx; 74 75 /* 76 * Encode VAL as a signed leb128 sequence at P. 77 * Return P incremented past the encoded value. 78 */ 79 static uint8_t *encode_sleb128(uint8_t *p, int64_t val) 80 { 81 int more, byte; 82 83 do { 84 byte = val & 0x7f; 85 val >>= 7; 86 more = !((val == 0 && (byte & 0x40) == 0) 87 || (val == -1 && (byte & 0x40) != 0)); 88 if (more) { 89 byte |= 0x80; 90 } 91 *p++ = byte; 92 } while (more); 93 94 return p; 95 } 96 97 /* 98 * Decode a signed leb128 sequence at *PP; increment *PP past the 99 * decoded value. Return the decoded value. 100 */ 101 static int64_t decode_sleb128(const uint8_t **pp) 102 { 103 const uint8_t *p = *pp; 104 int64_t val = 0; 105 int byte, shift = 0; 106 107 do { 108 byte = *p++; 109 val |= (int64_t)(byte & 0x7f) << shift; 110 shift += 7; 111 } while (byte & 0x80); 112 if (shift < TARGET_LONG_BITS && (byte & 0x40)) { 113 val |= -(int64_t)1 << shift; 114 } 115 116 *pp = p; 117 return val; 118 } 119 120 /* Encode the data collected about the instructions while compiling TB. 121 Place the data at BLOCK, and return the number of bytes consumed. 122 123 The logical table consists of TARGET_INSN_START_WORDS target_ulong's, 124 which come from the target's insn_start data, followed by a uintptr_t 125 which comes from the host pc of the end of the code implementing the insn. 126 127 Each line of the table is encoded as sleb128 deltas from the previous 128 line. The seed for the first line is { tb->pc, 0..., tb->tc.ptr }. 129 That is, the first column is seeded with the guest pc, the last column 130 with the host pc, and the middle columns with zeros. */ 131 132 static int encode_search(TranslationBlock *tb, uint8_t *block) 133 { 134 uint8_t *highwater = tcg_ctx->code_gen_highwater; 135 uint64_t *insn_data = tcg_ctx->gen_insn_data; 136 uint16_t *insn_end_off = tcg_ctx->gen_insn_end_off; 137 uint8_t *p = block; 138 int i, j, n; 139 140 for (i = 0, n = tb->icount; i < n; ++i) { 141 uint64_t prev, curr; 142 143 for (j = 0; j < TARGET_INSN_START_WORDS; ++j) { 144 if (i == 0) { 145 prev = (!(tb_cflags(tb) & CF_PCREL) && j == 0 ? tb->pc : 0); 146 } else { 147 prev = insn_data[(i - 1) * TARGET_INSN_START_WORDS + j]; 148 } 149 curr = insn_data[i * TARGET_INSN_START_WORDS + j]; 150 p = encode_sleb128(p, curr - prev); 151 } 152 prev = (i == 0 ? 0 : insn_end_off[i - 1]); 153 curr = insn_end_off[i]; 154 p = encode_sleb128(p, curr - prev); 155 156 /* Test for (pending) buffer overflow. The assumption is that any 157 one row beginning below the high water mark cannot overrun 158 the buffer completely. Thus we can test for overflow after 159 encoding a row without having to check during encoding. */ 160 if (unlikely(p > highwater)) { 161 return -1; 162 } 163 } 164 165 return p - block; 166 } 167 168 static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc, 169 uint64_t *data) 170 { 171 uintptr_t iter_pc = (uintptr_t)tb->tc.ptr; 172 const uint8_t *p = tb->tc.ptr + tb->tc.size; 173 int i, j, num_insns = tb->icount; 174 175 host_pc -= GETPC_ADJ; 176 177 if (host_pc < iter_pc) { 178 return -1; 179 } 180 181 memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS); 182 if (!(tb_cflags(tb) & CF_PCREL)) { 183 data[0] = tb->pc; 184 } 185 186 /* 187 * Reconstruct the stored insn data while looking for the point 188 * at which the end of the insn exceeds host_pc. 189 */ 190 for (i = 0; i < num_insns; ++i) { 191 for (j = 0; j < TARGET_INSN_START_WORDS; ++j) { 192 data[j] += decode_sleb128(&p); 193 } 194 iter_pc += decode_sleb128(&p); 195 if (iter_pc > host_pc) { 196 return num_insns - i; 197 } 198 } 199 return -1; 200 } 201 202 /* 203 * The cpu state corresponding to 'host_pc' is restored in 204 * preparation for exiting the TB. 205 */ 206 void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, 207 uintptr_t host_pc) 208 { 209 uint64_t data[TARGET_INSN_START_WORDS]; 210 int insns_left = cpu_unwind_data_from_tb(tb, host_pc, data); 211 212 if (insns_left < 0) { 213 return; 214 } 215 216 if (tb_cflags(tb) & CF_USE_ICOUNT) { 217 assert(icount_enabled()); 218 /* 219 * Reset the cycle counter to the start of the block and 220 * shift if to the number of actually executed instructions. 221 */ 222 cpu->neg.icount_decr.u16.low += insns_left; 223 } 224 225 cpu->cc->tcg_ops->restore_state_to_opc(cpu, tb, data); 226 } 227 228 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc) 229 { 230 /* 231 * The host_pc has to be in the rx region of the code buffer. 232 * If it is not we will not be able to resolve it here. 233 * The two cases where host_pc will not be correct are: 234 * 235 * - fault during translation (instruction fetch) 236 * - fault from helper (not using GETPC() macro) 237 * 238 * Either way we need return early as we can't resolve it here. 239 */ 240 if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) { 241 TranslationBlock *tb = tcg_tb_lookup(host_pc); 242 if (tb) { 243 cpu_restore_state_from_tb(cpu, tb, host_pc); 244 return true; 245 } 246 } 247 return false; 248 } 249 250 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data) 251 { 252 if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) { 253 TranslationBlock *tb = tcg_tb_lookup(host_pc); 254 if (tb) { 255 return cpu_unwind_data_from_tb(tb, host_pc, data) >= 0; 256 } 257 } 258 return false; 259 } 260 261 void page_init(void) 262 { 263 page_table_config_init(); 264 } 265 266 /* 267 * Isolate the portion of code gen which can setjmp/longjmp. 268 * Return the size of the generated code, or negative on error. 269 */ 270 static int setjmp_gen_code(CPUArchState *env, TranslationBlock *tb, 271 vaddr pc, void *host_pc, 272 int *max_insns, int64_t *ti) 273 { 274 int ret = sigsetjmp(tcg_ctx->jmp_trans, 0); 275 if (unlikely(ret != 0)) { 276 return ret; 277 } 278 279 tcg_func_start(tcg_ctx); 280 281 CPUState *cs = env_cpu(env); 282 tcg_ctx->cpu = cs; 283 cs->cc->tcg_ops->translate_code(cs, tb, max_insns, pc, host_pc); 284 285 assert(tb->size != 0); 286 tcg_ctx->cpu = NULL; 287 *max_insns = tb->icount; 288 289 return tcg_gen_code(tcg_ctx, tb, pc); 290 } 291 292 /* Called with mmap_lock held for user mode emulation. */ 293 TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s) 294 { 295 CPUArchState *env = cpu_env(cpu); 296 TranslationBlock *tb, *existing_tb; 297 tb_page_addr_t phys_pc, phys_p2; 298 tcg_insn_unit *gen_code_buf; 299 int gen_code_size, search_size, max_insns; 300 int64_t ti; 301 void *host_pc; 302 303 assert_memory_lock(); 304 qemu_thread_jit_write(); 305 306 phys_pc = get_page_addr_code_hostp(env, s.pc, &host_pc); 307 308 if (phys_pc == -1) { 309 /* Generate a one-shot TB with 1 insn in it */ 310 s.cflags = (s.cflags & ~CF_COUNT_MASK) | 1; 311 } 312 313 max_insns = s.cflags & CF_COUNT_MASK; 314 if (max_insns == 0) { 315 max_insns = TCG_MAX_INSNS; 316 } 317 QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 != TCG_MAX_INSNS); 318 319 buffer_overflow: 320 assert_no_pages_locked(); 321 tb = tcg_tb_alloc(tcg_ctx); 322 if (unlikely(!tb)) { 323 /* flush must be done */ 324 tb_flush(cpu); 325 mmap_unlock(); 326 /* Make the execution loop process the flush as soon as possible. */ 327 cpu->exception_index = EXCP_INTERRUPT; 328 cpu_loop_exit(cpu); 329 } 330 331 gen_code_buf = tcg_ctx->code_gen_ptr; 332 tb->tc.ptr = tcg_splitwx_to_rx(gen_code_buf); 333 if (!(s.cflags & CF_PCREL)) { 334 tb->pc = s.pc; 335 } 336 tb->cs_base = s.cs_base; 337 tb->flags = s.flags; 338 tb->cflags = s.cflags; 339 tb_set_page_addr0(tb, phys_pc); 340 tb_set_page_addr1(tb, -1); 341 if (phys_pc != -1) { 342 tb_lock_page0(phys_pc); 343 } 344 345 tcg_ctx->gen_tb = tb; 346 tcg_ctx->addr_type = TARGET_LONG_BITS == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64; 347 #ifdef CONFIG_SOFTMMU 348 tcg_ctx->page_bits = TARGET_PAGE_BITS; 349 tcg_ctx->page_mask = TARGET_PAGE_MASK; 350 tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS; 351 #endif 352 tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS; 353 tcg_ctx->guest_mo = cpu->cc->tcg_ops->guest_default_memory_order; 354 355 restart_translate: 356 trace_translate_block(tb, s.pc, tb->tc.ptr); 357 358 gen_code_size = setjmp_gen_code(env, tb, s.pc, host_pc, &max_insns, &ti); 359 if (unlikely(gen_code_size < 0)) { 360 switch (gen_code_size) { 361 case -1: 362 /* 363 * Overflow of code_gen_buffer, or the current slice of it. 364 * 365 * TODO: We don't need to re-do tcg_ops->translate_code, nor 366 * should we re-do the tcg optimization currently hidden 367 * inside tcg_gen_code. All that should be required is to 368 * flush the TBs, allocate a new TB, re-initialize it per 369 * above, and re-do the actual code generation. 370 */ 371 qemu_log_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT, 372 "Restarting code generation for " 373 "code_gen_buffer overflow\n"); 374 tb_unlock_pages(tb); 375 tcg_ctx->gen_tb = NULL; 376 goto buffer_overflow; 377 378 case -2: 379 /* 380 * The code generated for the TranslationBlock is too large. 381 * The maximum size allowed by the unwind info is 64k. 382 * There may be stricter constraints from relocations 383 * in the tcg backend. 384 * 385 * Try again with half as many insns as we attempted this time. 386 * If a single insn overflows, there's a bug somewhere... 387 */ 388 assert(max_insns > 1); 389 max_insns /= 2; 390 qemu_log_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT, 391 "Restarting code generation with " 392 "smaller translation block (max %d insns)\n", 393 max_insns); 394 395 /* 396 * The half-sized TB may not cross pages. 397 * TODO: Fix all targets that cross pages except with 398 * the first insn, at which point this can't be reached. 399 */ 400 phys_p2 = tb_page_addr1(tb); 401 if (unlikely(phys_p2 != -1)) { 402 tb_unlock_page1(phys_pc, phys_p2); 403 tb_set_page_addr1(tb, -1); 404 } 405 goto restart_translate; 406 407 case -3: 408 /* 409 * We had a page lock ordering problem. In order to avoid 410 * deadlock we had to drop the lock on page0, which means 411 * that everything we translated so far is compromised. 412 * Restart with locks held on both pages. 413 */ 414 qemu_log_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT, 415 "Restarting code generation with re-locked pages"); 416 goto restart_translate; 417 418 default: 419 g_assert_not_reached(); 420 } 421 } 422 tcg_ctx->gen_tb = NULL; 423 424 search_size = encode_search(tb, (void *)gen_code_buf + gen_code_size); 425 if (unlikely(search_size < 0)) { 426 tb_unlock_pages(tb); 427 goto buffer_overflow; 428 } 429 tb->tc.size = gen_code_size; 430 431 /* 432 * For CF_PCREL, attribute all executions of the generated code 433 * to its first mapping. 434 */ 435 perf_report_code(s.pc, tb, tcg_splitwx_to_rx(gen_code_buf)); 436 437 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && 438 qemu_log_in_addr_range(s.pc)) { 439 FILE *logfile = qemu_log_trylock(); 440 if (logfile) { 441 int code_size, data_size; 442 const tcg_target_ulong *rx_data_gen_ptr; 443 size_t chunk_start; 444 int insn = 0; 445 446 if (tcg_ctx->data_gen_ptr) { 447 rx_data_gen_ptr = tcg_splitwx_to_rx(tcg_ctx->data_gen_ptr); 448 code_size = (const void *)rx_data_gen_ptr - tb->tc.ptr; 449 data_size = gen_code_size - code_size; 450 } else { 451 rx_data_gen_ptr = 0; 452 code_size = gen_code_size; 453 data_size = 0; 454 } 455 456 /* Dump header and the first instruction */ 457 fprintf(logfile, "OUT: [size=%d]\n", gen_code_size); 458 fprintf(logfile, 459 " -- guest addr 0x%016" PRIx64 " + tb prologue\n", 460 tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]); 461 chunk_start = tcg_ctx->gen_insn_end_off[insn]; 462 disas(logfile, tb->tc.ptr, chunk_start); 463 464 /* 465 * Dump each instruction chunk, wrapping up empty chunks into 466 * the next instruction. The whole array is offset so the 467 * first entry is the beginning of the 2nd instruction. 468 */ 469 while (insn < tb->icount) { 470 size_t chunk_end = tcg_ctx->gen_insn_end_off[insn]; 471 if (chunk_end > chunk_start) { 472 fprintf(logfile, " -- guest addr 0x%016" PRIx64 "\n", 473 tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]); 474 disas(logfile, tb->tc.ptr + chunk_start, 475 chunk_end - chunk_start); 476 chunk_start = chunk_end; 477 } 478 insn++; 479 } 480 481 if (chunk_start < code_size) { 482 fprintf(logfile, " -- tb slow paths + alignment\n"); 483 disas(logfile, tb->tc.ptr + chunk_start, 484 code_size - chunk_start); 485 } 486 487 /* Finally dump any data we may have after the block */ 488 if (data_size) { 489 int i; 490 fprintf(logfile, " data: [size=%d]\n", data_size); 491 for (i = 0; i < data_size / sizeof(tcg_target_ulong); i++) { 492 if (sizeof(tcg_target_ulong) == 8) { 493 fprintf(logfile, 494 "0x%08" PRIxPTR ": .quad 0x%016" TCG_PRIlx "\n", 495 (uintptr_t)&rx_data_gen_ptr[i], rx_data_gen_ptr[i]); 496 } else if (sizeof(tcg_target_ulong) == 4) { 497 fprintf(logfile, 498 "0x%08" PRIxPTR ": .long 0x%08" TCG_PRIlx "\n", 499 (uintptr_t)&rx_data_gen_ptr[i], rx_data_gen_ptr[i]); 500 } else { 501 qemu_build_not_reached(); 502 } 503 } 504 } 505 fprintf(logfile, "\n"); 506 qemu_log_unlock(logfile); 507 } 508 } 509 510 qatomic_set(&tcg_ctx->code_gen_ptr, (void *) 511 ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size, 512 CODE_GEN_ALIGN)); 513 514 /* init jump list */ 515 qemu_spin_init(&tb->jmp_lock); 516 tb->jmp_list_head = (uintptr_t)NULL; 517 tb->jmp_list_next[0] = (uintptr_t)NULL; 518 tb->jmp_list_next[1] = (uintptr_t)NULL; 519 tb->jmp_dest[0] = (uintptr_t)NULL; 520 tb->jmp_dest[1] = (uintptr_t)NULL; 521 522 /* init original jump addresses which have been set during tcg_gen_code() */ 523 if (tb->jmp_reset_offset[0] != TB_JMP_OFFSET_INVALID) { 524 tb_reset_jump(tb, 0); 525 } 526 if (tb->jmp_reset_offset[1] != TB_JMP_OFFSET_INVALID) { 527 tb_reset_jump(tb, 1); 528 } 529 530 /* 531 * Insert TB into the corresponding region tree before publishing it 532 * through QHT. Otherwise rewinding happened in the TB might fail to 533 * lookup itself using host PC. 534 */ 535 tcg_tb_insert(tb); 536 537 /* 538 * If the TB is not associated with a physical RAM page then it must be 539 * a temporary one-insn TB. 540 * 541 * Such TBs must be added to region trees in order to make sure that 542 * restore_state_to_opc() - which on some architectures is not limited to 543 * rewinding, but also affects exception handling! - is called when such a 544 * TB causes an exception. 545 * 546 * At the same time, temporary one-insn TBs must be executed at most once, 547 * because subsequent reads from, e.g., I/O memory may return different 548 * values. So return early before attempting to link to other TBs or add 549 * to the QHT. 550 */ 551 if (tb_page_addr0(tb) == -1) { 552 assert_no_pages_locked(); 553 return tb; 554 } 555 556 /* 557 * No explicit memory barrier is required -- tb_link_page() makes the 558 * TB visible in a consistent state. 559 */ 560 existing_tb = tb_link_page(tb); 561 assert_no_pages_locked(); 562 563 /* if the TB already exists, discard what we just translated */ 564 if (unlikely(existing_tb != tb)) { 565 uintptr_t orig_aligned = (uintptr_t)gen_code_buf; 566 567 orig_aligned -= ROUND_UP(sizeof(*tb), qemu_icache_linesize); 568 qatomic_set(&tcg_ctx->code_gen_ptr, (void *)orig_aligned); 569 tcg_tb_remove(tb); 570 return existing_tb; 571 } 572 return tb; 573 } 574 575 /* user-mode: call with mmap_lock held */ 576 void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr) 577 { 578 TranslationBlock *tb; 579 580 assert_memory_lock(); 581 582 tb = tcg_tb_lookup(retaddr); 583 if (tb) { 584 /* We can use retranslation to find the PC. */ 585 cpu_restore_state_from_tb(cpu, tb, retaddr); 586 tb_phys_invalidate(tb, -1); 587 } else { 588 /* The exception probably happened in a helper. The CPU state should 589 have been saved before calling it. Fetch the PC from there. */ 590 CPUArchState *env = cpu_env(cpu); 591 TCGTBCPUState s = cpu->cc->tcg_ops->get_tb_cpu_state(cpu); 592 tb_page_addr_t addr = get_page_addr_code(env, s.pc); 593 594 if (addr != -1) { 595 tb_invalidate_phys_range(cpu, addr, addr); 596 } 597 } 598 } 599 600 #ifndef CONFIG_USER_ONLY 601 /* 602 * In deterministic execution mode, instructions doing device I/Os 603 * must be at the end of the TB. 604 * 605 * Called by softmmu_template.h, with iothread mutex not held. 606 */ 607 void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) 608 { 609 TranslationBlock *tb; 610 CPUClass *cc; 611 uint32_t n; 612 613 tb = tcg_tb_lookup(retaddr); 614 if (!tb) { 615 cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p", 616 (void *)retaddr); 617 } 618 cpu_restore_state_from_tb(cpu, tb, retaddr); 619 620 /* 621 * Some guests must re-execute the branch when re-executing a delay 622 * slot instruction. When this is the case, adjust icount and N 623 * to account for the re-execution of the branch. 624 */ 625 n = 1; 626 cc = cpu->cc; 627 if (cc->tcg_ops->io_recompile_replay_branch && 628 cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) { 629 cpu->neg.icount_decr.u16.low++; 630 n = 2; 631 } 632 633 /* 634 * Exit the loop and potentially generate a new TB executing the 635 * just the I/O insns. We also limit instrumentation to memory 636 * operations only (which execute after completion) so we don't 637 * double instrument the instruction. Also don't let an IRQ sneak 638 * in before we execute it. 639 */ 640 cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | CF_NOIRQ | n; 641 642 if (qemu_loglevel_mask(CPU_LOG_EXEC)) { 643 vaddr pc = cpu->cc->get_pc(cpu); 644 if (qemu_log_in_addr_range(pc)) { 645 qemu_log("cpu_io_recompile: rewound execution of TB to %016" 646 VADDR_PRIx "\n", pc); 647 } 648 } 649 650 cpu_loop_exit_noexc(cpu); 651 } 652 653 #endif /* CONFIG_USER_ONLY */ 654 655 /* 656 * Called by generic code at e.g. cpu reset after cpu creation, 657 * therefore we must be prepared to allocate the jump cache. 658 */ 659 void tcg_flush_jmp_cache(CPUState *cpu) 660 { 661 CPUJumpCache *jc = cpu->tb_jmp_cache; 662 663 /* During early initialization, the cache may not yet be allocated. */ 664 if (unlikely(jc == NULL)) { 665 return; 666 } 667 668 for (int i = 0; i < TB_JMP_CACHE_SIZE; i++) { 669 qatomic_set(&jc->array[i].tb, NULL); 670 } 671 } 672