1 /* 2 * softmmu size bounds 3 * SPDX-License-Identifier: LGPL-2.1-or-later 4 */ 5 6 #ifndef ACCEL_TCG_TLB_BOUNDS_H 7 #define ACCEL_TCG_TLB_BOUNDS_H 8 9 #define CPU_TLB_DYN_MIN_BITS 6 10 #define CPU_TLB_DYN_DEFAULT_BITS 8 11 12 # if HOST_LONG_BITS == 32 13 /* Make sure we do not require a double-word shift for the TLB load */ 14 # define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) 15 # else /* HOST_LONG_BITS == 64 */ 16 /* 17 * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == 18 * 2**34 == 16G of address space. This is roughly what one would expect a 19 * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel 20 * Skylake's Level-2 STLB has 16 1G entries. 21 * Also, make sure we do not size the TLB past the guest's address space. 22 */ 23 # ifdef TARGET_PAGE_BITS_VARY 24 # define CPU_TLB_DYN_MAX_BITS \ 25 MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 26 # else 27 # define CPU_TLB_DYN_MAX_BITS \ 28 MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 29 # endif 30 # endif 31 32 #endif /* ACCEL_TCG_TLB_BOUNDS_H */ 33