xref: /qemu/accel/tcg/tb-internal.h (revision 7cef6d686309e2792186504ae17cf4f3eb57ef68)
193ef2c2fSPhilippe Mathieu-Daudé /*
293ef2c2fSPhilippe Mathieu-Daudé  * TranslationBlock internal declarations (target specific)
393ef2c2fSPhilippe Mathieu-Daudé  *
493ef2c2fSPhilippe Mathieu-Daudé  *  Copyright (c) 2003 Fabrice Bellard
593ef2c2fSPhilippe Mathieu-Daudé  *
693ef2c2fSPhilippe Mathieu-Daudé  * SPDX-License-Identifier: LGPL-2.1-or-later
793ef2c2fSPhilippe Mathieu-Daudé  */
893ef2c2fSPhilippe Mathieu-Daudé 
993ef2c2fSPhilippe Mathieu-Daudé #ifndef ACCEL_TCG_TB_INTERNAL_TARGET_H
1093ef2c2fSPhilippe Mathieu-Daudé #define ACCEL_TCG_TB_INTERNAL_TARGET_H
1193ef2c2fSPhilippe Mathieu-Daudé 
123e6bfabfSPhilippe Mathieu-Daudé #include "exec/translation-block.h"
133e6bfabfSPhilippe Mathieu-Daudé 
14bf4a155bSPhilippe Mathieu-Daudé /*
15bf4a155bSPhilippe Mathieu-Daudé  * The true return address will often point to a host insn that is part of
16bf4a155bSPhilippe Mathieu-Daudé  * the next translated guest insn.  Adjust the address backward to point to
17bf4a155bSPhilippe Mathieu-Daudé  * the middle of the call insn.  Subtracting one would do the job except for
18bf4a155bSPhilippe Mathieu-Daudé  * several compressed mode architectures (arm, mips) which set the low bit
19bf4a155bSPhilippe Mathieu-Daudé  * to indicate the compressed mode; subtracting two works around that.  It
20bf4a155bSPhilippe Mathieu-Daudé  * is also the case that there are no host isas that contain a call insn
21bf4a155bSPhilippe Mathieu-Daudé  * smaller than 4 bytes, so we don't worry about special-casing this.
22bf4a155bSPhilippe Mathieu-Daudé  */
23bf4a155bSPhilippe Mathieu-Daudé #define GETPC_ADJ   2
24bf4a155bSPhilippe Mathieu-Daudé 
25b103cc6eSRichard Henderson void tb_lock_page0(tb_page_addr_t);
26b103cc6eSRichard Henderson 
273e6bfabfSPhilippe Mathieu-Daudé #ifdef CONFIG_USER_ONLY
283e6bfabfSPhilippe Mathieu-Daudé /*
293e6bfabfSPhilippe Mathieu-Daudé  * For user-only, page_protect sets the page read-only.
303e6bfabfSPhilippe Mathieu-Daudé  * Since most execution is already on read-only pages, and we'd need to
313e6bfabfSPhilippe Mathieu-Daudé  * account for other TBs on the same page, defer undoing any page protection
323e6bfabfSPhilippe Mathieu-Daudé  * until we receive the write fault.
333e6bfabfSPhilippe Mathieu-Daudé  */
tb_lock_page1(tb_page_addr_t p0,tb_page_addr_t p1)343e6bfabfSPhilippe Mathieu-Daudé static inline void tb_lock_page1(tb_page_addr_t p0, tb_page_addr_t p1)
353e6bfabfSPhilippe Mathieu-Daudé {
36b103cc6eSRichard Henderson     tb_lock_page0(p1);
373e6bfabfSPhilippe Mathieu-Daudé }
383e6bfabfSPhilippe Mathieu-Daudé 
tb_unlock_page1(tb_page_addr_t p0,tb_page_addr_t p1)393e6bfabfSPhilippe Mathieu-Daudé static inline void tb_unlock_page1(tb_page_addr_t p0, tb_page_addr_t p1) { }
tb_unlock_pages(TranslationBlock * tb)403e6bfabfSPhilippe Mathieu-Daudé static inline void tb_unlock_pages(TranslationBlock *tb) { }
413e6bfabfSPhilippe Mathieu-Daudé #else
423e6bfabfSPhilippe Mathieu-Daudé void tb_lock_page1(tb_page_addr_t, tb_page_addr_t);
433e6bfabfSPhilippe Mathieu-Daudé void tb_unlock_page1(tb_page_addr_t, tb_page_addr_t);
443e6bfabfSPhilippe Mathieu-Daudé void tb_unlock_pages(TranslationBlock *);
453e6bfabfSPhilippe Mathieu-Daudé #endif
463e6bfabfSPhilippe Mathieu-Daudé 
473e6bfabfSPhilippe Mathieu-Daudé #ifdef CONFIG_SOFTMMU
48*7fa0f4a7SRichard Henderson void tb_invalidate_phys_range_fast(CPUState *cpu, ram_addr_t ram_addr,
49*7fa0f4a7SRichard Henderson                                    unsigned size, uintptr_t retaddr);
503e6bfabfSPhilippe Mathieu-Daudé #endif /* CONFIG_SOFTMMU */
513e6bfabfSPhilippe Mathieu-Daudé 
5200f70884SRichard Henderson bool tb_invalidate_phys_page_unwind(CPUState *cpu, tb_page_addr_t addr,
5300f70884SRichard Henderson                                     uintptr_t pc);
543e6bfabfSPhilippe Mathieu-Daudé 
5593ef2c2fSPhilippe Mathieu-Daudé #endif
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