xref: /qemu/accel/tcg/internal-common.h (revision b103cc6e74ac92f070a0e004bd84334e845c20b5)
1 /*
2  * Internal execution defines for qemu (target agnostic)
3  *
4  *  Copyright (c) 2003 Fabrice Bellard
5  *
6  * SPDX-License-Identifier: LGPL-2.1-or-later
7  */
8 
9 #ifndef ACCEL_TCG_INTERNAL_COMMON_H
10 #define ACCEL_TCG_INTERNAL_COMMON_H
11 
12 #include "exec/cpu-common.h"
13 #include "exec/translation-block.h"
14 
15 extern int64_t max_delay;
16 extern int64_t max_advance;
17 
18 extern bool one_insn_per_tb;
19 
20 extern bool icount_align_option;
21 
22 /*
23  * Return true if CS is not running in parallel with other cpus, either
24  * because there are no other cpus or we are within an exclusive context.
25  */
26 static inline bool cpu_in_serial_context(CPUState *cs)
27 {
28     return !tcg_cflags_has(cs, CF_PARALLEL) || cpu_in_exclusive_context(cs);
29 }
30 
31 /**
32  * cpu_plugin_mem_cbs_enabled() - are plugin memory callbacks enabled?
33  * @cs: CPUState pointer
34  *
35  * The memory callbacks are installed if a plugin has instrumented an
36  * instruction for memory. This can be useful to know if you want to
37  * force a slow path for a series of memory accesses.
38  */
39 static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu)
40 {
41 #ifdef CONFIG_PLUGIN
42     return !!cpu->neg.plugin_mem_cbs;
43 #else
44     return false;
45 #endif
46 }
47 
48 TranslationBlock *tb_gen_code(CPUState *cpu, vaddr pc,
49                               uint64_t cs_base, uint32_t flags,
50                               int cflags);
51 void page_init(void);
52 void tb_htable_init(void);
53 void tb_reset_jump(TranslationBlock *tb, int n);
54 TranslationBlock *tb_link_page(TranslationBlock *tb);
55 void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
56                                uintptr_t host_pc);
57 
58 /**
59  * tlb_init - initialize a CPU's TLB
60  * @cpu: CPU whose TLB should be initialized
61  */
62 void tlb_init(CPUState *cpu);
63 /**
64  * tlb_destroy - destroy a CPU's TLB
65  * @cpu: CPU whose TLB should be destroyed
66  */
67 void tlb_destroy(CPUState *cpu);
68 
69 bool tcg_exec_realizefn(CPUState *cpu, Error **errp);
70 void tcg_exec_unrealizefn(CPUState *cpu);
71 
72 /* current cflags for hashing/comparison */
73 uint32_t curr_cflags(CPUState *cpu);
74 
75 void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr);
76 
77 /**
78  * get_page_addr_code_hostp()
79  * @env: CPUArchState
80  * @addr: guest virtual address of guest code
81  *
82  * See get_page_addr_code() (full-system version) for documentation on the
83  * return value.
84  *
85  * Sets *@hostp (when @hostp is non-NULL) as follows.
86  * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp
87  * to the host address where @addr's content is kept.
88  *
89  * Note: this function can trigger an exception.
90  */
91 tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr,
92                                         void **hostp);
93 
94 /**
95  * get_page_addr_code()
96  * @env: CPUArchState
97  * @addr: guest virtual address of guest code
98  *
99  * If we cannot translate and execute from the entire RAM page, or if
100  * the region is not backed by RAM, returns -1. Otherwise, returns the
101  * ram_addr_t corresponding to the guest code at @addr.
102  *
103  * Note: this function can trigger an exception.
104  */
105 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
106                                                 vaddr addr)
107 {
108     return get_page_addr_code_hostp(env, addr, NULL);
109 }
110 
111 #endif
112