171b7ff5eSAndrea ParriC LB+fencembonceonce+ctrlonceonce 21c27b644SPaul E. McKenney 38f32543bSPaul E. McKenney(* 48f32543bSPaul E. McKenney * Result: Never 58f32543bSPaul E. McKenney * 68f32543bSPaul E. McKenney * This litmus test demonstrates that lightweight ordering suffices for 78f32543bSPaul E. McKenney * the load-buffering pattern, in other words, preventing all processes 88f32543bSPaul E. McKenney * reading from the preceding process's write. In this example, the 98f32543bSPaul E. McKenney * combination of a control dependency and a full memory barrier are enough 108f32543bSPaul E. McKenney * to do the trick. (But the full memory barrier could be replaced with 118f32543bSPaul E. McKenney * another control dependency and order would still be maintained.) 128f32543bSPaul E. McKenney *) 138f32543bSPaul E. McKenney 145c587f9bSAkira Yokosawa{} 151c27b644SPaul E. McKenney 161c27b644SPaul E. McKenneyP0(int *x, int *y) 171c27b644SPaul E. McKenney{ 181c27b644SPaul E. McKenney int r0; 191c27b644SPaul E. McKenney 201c27b644SPaul E. McKenney r0 = READ_ONCE(*x); 211c27b644SPaul E. McKenney if (r0) 221c27b644SPaul E. McKenney WRITE_ONCE(*y, 1); 231c27b644SPaul E. McKenney} 241c27b644SPaul E. McKenney 251c27b644SPaul E. McKenneyP1(int *x, int *y) 261c27b644SPaul E. McKenney{ 271c27b644SPaul E. McKenney int r0; 281c27b644SPaul E. McKenney 291c27b644SPaul E. McKenney r0 = READ_ONCE(*y); 301c27b644SPaul E. McKenney smp_mb(); 311c27b644SPaul E. McKenney WRITE_ONCE(*x, 1); 321c27b644SPaul E. McKenney} 331c27b644SPaul E. McKenney 341c27b644SPaul E. McKenneyexists (0:r0=1 /\ 1:r0=1) 35