1*05bb3d5eSSameer Pujar /* SPDX-License-Identifier: GPL-2.0-only */ 2*05bb3d5eSSameer Pujar /* 3*05bb3d5eSSameer Pujar * tegra210_mixer.h - Definitions for Tegra210 MIXER driver 4*05bb3d5eSSameer Pujar * 5*05bb3d5eSSameer Pujar * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. 6*05bb3d5eSSameer Pujar * 7*05bb3d5eSSameer Pujar */ 8*05bb3d5eSSameer Pujar 9*05bb3d5eSSameer Pujar #ifndef __TEGRA210_MIXER_H__ 10*05bb3d5eSSameer Pujar #define __TEGRA210_MIXER_H__ 11*05bb3d5eSSameer Pujar 12*05bb3d5eSSameer Pujar /* XBAR_RX related MIXER offsets */ 13*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_RX1_SOFT_RESET 0x04 14*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_RX1_STATUS 0x10 15*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_RX1_CIF_CTRL 0x24 16*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_RX1_CTRL 0x28 17*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_RX1_PEAK_CTRL 0x2c 18*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_RX1_SAMPLE_COUNT 0x30 19*05bb3d5eSSameer Pujar 20*05bb3d5eSSameer Pujar /* XBAR_TX related MIXER offsets */ 21*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX1_ENABLE 0x280 22*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX1_SOFT_RESET 0x284 23*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX1_STATUS 0x290 24*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX1_INT_STATUS 0x294 25*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX1_INT_MASK 0x298 26*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX1_INT_SET 0x29c 27*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX1_INT_CLEAR 0x2a0 28*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX1_CIF_CTRL 0x2a4 29*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX1_ADDER_CONFIG 0x2a8 30*05bb3d5eSSameer Pujar 31*05bb3d5eSSameer Pujar /* MIXER related offsets */ 32*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_ENABLE 0x400 33*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_SOFT_RESET 0x404 34*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_CG 0x408 35*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_STATUS 0x410 36*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_INT_STATUS 0x414 37*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_GAIN_CFG_RAM_CTRL 0x42c 38*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_GAIN_CFG_RAM_DATA 0x430 39*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_PEAKM_RAM_CTRL 0x434 40*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_PEAKM_RAM_DATA 0x438 41*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_CTRL 0x43c 42*05bb3d5eSSameer Pujar 43*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX2_ADDER_CONFIG (TEGRA210_MIXER_TX1_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE) 44*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX3_ADDER_CONFIG (TEGRA210_MIXER_TX2_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE) 45*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX4_ADDER_CONFIG (TEGRA210_MIXER_TX3_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE) 46*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX5_ADDER_CONFIG (TEGRA210_MIXER_TX4_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE) 47*05bb3d5eSSameer Pujar 48*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX2_ENABLE (TEGRA210_MIXER_TX1_ENABLE + TEGRA210_MIXER_REG_STRIDE) 49*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX3_ENABLE (TEGRA210_MIXER_TX2_ENABLE + TEGRA210_MIXER_REG_STRIDE) 50*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX4_ENABLE (TEGRA210_MIXER_TX3_ENABLE + TEGRA210_MIXER_REG_STRIDE) 51*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX5_ENABLE (TEGRA210_MIXER_TX4_ENABLE + TEGRA210_MIXER_REG_STRIDE) 52*05bb3d5eSSameer Pujar 53*05bb3d5eSSameer Pujar /* Fields in TEGRA210_MIXER_ENABLE */ 54*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_ENABLE_SHIFT 0 55*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_ENABLE_MASK (1 << TEGRA210_MIXER_ENABLE_SHIFT) 56*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_EN (1 << TEGRA210_MIXER_ENABLE_SHIFT) 57*05bb3d5eSSameer Pujar 58*05bb3d5eSSameer Pujar /* Fields in TEGRA210_MIXER_GAIN_CFG_RAM_CTRL */ 59*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_0 0x0 60*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_STRIDE 0x10 61*05bb3d5eSSameer Pujar 62*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_GAIN_CFG_RAM_RW_SHIFT 14 63*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_GAIN_CFG_RAM_RW_MASK (1 << TEGRA210_MIXER_GAIN_CFG_RAM_RW_SHIFT) 64*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_GAIN_CFG_RAM_RW_WRITE (1 << TEGRA210_MIXER_GAIN_CFG_RAM_RW_SHIFT) 65*05bb3d5eSSameer Pujar 66*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_SHIFT 13 67*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_MASK (1 << TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_SHIFT) 68*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN (1 << TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_SHIFT) 69*05bb3d5eSSameer Pujar 70*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_SHIFT 12 71*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_MASK (1 << TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_SHIFT) 72*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN (1 << TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_SHIFT) 73*05bb3d5eSSameer Pujar 74*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_SHIFT 0 75*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_MASK (0x1ff << TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_SHIFT) 76*05bb3d5eSSameer Pujar 77*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_REG_STRIDE 0x40 78*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_RX_MAX 10 79*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_RX_LIMIT (TEGRA210_MIXER_RX_MAX * TEGRA210_MIXER_REG_STRIDE) 80*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX_MAX 5 81*05bb3d5eSSameer Pujar #define TEGRA210_MIXER_TX_LIMIT (TEGRA210_MIXER_RX_LIMIT + (TEGRA210_MIXER_TX_MAX * TEGRA210_MIXER_REG_STRIDE)) 82*05bb3d5eSSameer Pujar 83*05bb3d5eSSameer Pujar #define REG_CFG_DONE_TRIGGER 0xf 84*05bb3d5eSSameer Pujar #define VAL_CFG_DONE_TRIGGER 0x1 85*05bb3d5eSSameer Pujar 86*05bb3d5eSSameer Pujar #define NUM_GAIN_POLY_COEFFS 9 87*05bb3d5eSSameer Pujar #define NUM_DURATION_PARMS 4 88*05bb3d5eSSameer Pujar 89*05bb3d5eSSameer Pujar struct tegra210_mixer_gain_params { 90*05bb3d5eSSameer Pujar int poly_coeff[NUM_GAIN_POLY_COEFFS]; 91*05bb3d5eSSameer Pujar int gain_value; 92*05bb3d5eSSameer Pujar int duration[NUM_DURATION_PARMS]; 93*05bb3d5eSSameer Pujar }; 94*05bb3d5eSSameer Pujar 95*05bb3d5eSSameer Pujar struct tegra210_mixer { 96*05bb3d5eSSameer Pujar int gain_value[TEGRA210_MIXER_RX_MAX]; 97*05bb3d5eSSameer Pujar struct regmap *regmap; 98*05bb3d5eSSameer Pujar }; 99*05bb3d5eSSameer Pujar 100*05bb3d5eSSameer Pujar #endif 101