1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2021 Mediatek Inc. All rights reserved. 4 // 5 // Author: YC Hung <yc.hung@mediatek.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on mt8195 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/firmware.h> 14 #include <linux/io.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_platform.h> 18 #include <linux/of_reserved_mem.h> 19 #include <linux/module.h> 20 21 #include <sound/sof.h> 22 #include <sound/sof/xtensa.h> 23 #include "../../ops.h" 24 #include "../../sof-of-dev.h" 25 #include "../adsp_helper.h" 26 #include "../mtk-adsp-common.h" 27 #include "mt8195.h" 28 #include "mt8195-clk.h" 29 30 static int mt8195_get_mailbox_offset(struct snd_sof_dev *sdev) 31 { 32 return MBOX_OFFSET; 33 } 34 35 static int mt8195_get_window_offset(struct snd_sof_dev *sdev, u32 id) 36 { 37 return MBOX_OFFSET; 38 } 39 40 static const struct mtk_adsp_ipc_ops dsp_ops = { 41 .handle_reply = mtk_adsp_handle_reply, 42 .handle_request = mtk_adsp_handle_request, 43 }; 44 45 static int platform_parse_resource(struct platform_device *pdev, void *data) 46 { 47 struct resource *mmio; 48 struct resource res; 49 struct device_node *mem_region; 50 struct device *dev = &pdev->dev; 51 struct mtk_adsp_chip_info *adsp = data; 52 int ret; 53 54 ret = of_reserved_mem_device_init(dev); 55 if (ret) { 56 dev_err(dev, "of_reserved_mem_device_init failed\n"); 57 return ret; 58 } 59 60 mem_region = of_parse_phandle(dev->of_node, "memory-region", 1); 61 if (!mem_region) { 62 dev_err(dev, "no memory-region sysmem phandle\n"); 63 return -ENODEV; 64 } 65 66 ret = of_address_to_resource(mem_region, 0, &res); 67 of_node_put(mem_region); 68 if (ret) { 69 dev_err(dev, "of_address_to_resource sysmem failed\n"); 70 return ret; 71 } 72 73 adsp->pa_dram = (phys_addr_t)res.start; 74 adsp->dramsize = resource_size(&res); 75 if (adsp->pa_dram & DRAM_REMAP_MASK) { 76 dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n", 77 (u32)adsp->pa_dram); 78 return -EINVAL; 79 } 80 81 if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) { 82 dev_err(dev, "adsp memory(%#x) is not enough for share\n", 83 adsp->dramsize); 84 return -EINVAL; 85 } 86 87 dev_dbg(dev, "dram pbase=%pa, dramsize=%#x\n", 88 &adsp->pa_dram, adsp->dramsize); 89 90 /* Parse CFG base */ 91 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); 92 if (!mmio) { 93 dev_err(dev, "no ADSP-CFG register resource\n"); 94 return -ENXIO; 95 } 96 /* remap for DSP register accessing */ 97 adsp->va_cfgreg = devm_ioremap_resource(dev, mmio); 98 if (IS_ERR(adsp->va_cfgreg)) 99 return PTR_ERR(adsp->va_cfgreg); 100 101 adsp->pa_cfgreg = (phys_addr_t)mmio->start; 102 adsp->cfgregsize = resource_size(mmio); 103 104 dev_dbg(dev, "cfgreg-vbase=%p, cfgregsize=%#x\n", 105 adsp->va_cfgreg, adsp->cfgregsize); 106 107 /* Parse SRAM */ 108 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); 109 if (!mmio) { 110 dev_err(dev, "no SRAM resource\n"); 111 return -ENXIO; 112 } 113 114 adsp->pa_sram = (phys_addr_t)mmio->start; 115 adsp->sramsize = resource_size(mmio); 116 117 dev_dbg(dev, "sram pbase=%pa,%#x\n", &adsp->pa_sram, adsp->sramsize); 118 119 return ret; 120 } 121 122 static int adsp_sram_power_on(struct device *dev, bool on) 123 { 124 void __iomem *va_dspsysreg; 125 u32 srampool_con; 126 127 va_dspsysreg = ioremap(ADSP_SRAM_POOL_CON, 0x4); 128 if (!va_dspsysreg) { 129 dev_err(dev, "failed to ioremap sram pool base %#x\n", 130 ADSP_SRAM_POOL_CON); 131 return -ENOMEM; 132 } 133 134 srampool_con = readl(va_dspsysreg); 135 if (on) 136 writel(srampool_con & ~DSP_SRAM_POOL_PD_MASK, va_dspsysreg); 137 else 138 writel(srampool_con | DSP_SRAM_POOL_PD_MASK, va_dspsysreg); 139 140 iounmap(va_dspsysreg); 141 return 0; 142 } 143 144 /* Init the basic DSP DRAM address */ 145 static int adsp_memory_remap_init(struct device *dev, struct mtk_adsp_chip_info *adsp) 146 { 147 void __iomem *vaddr_emi_map; 148 int offset; 149 150 if (!adsp) 151 return -ENXIO; 152 153 vaddr_emi_map = devm_ioremap(dev, DSP_EMI_MAP_ADDR, 0x4); 154 if (!vaddr_emi_map) { 155 dev_err(dev, "failed to ioremap emi map base %#x\n", 156 DSP_EMI_MAP_ADDR); 157 return -ENOMEM; 158 } 159 160 offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW; 161 adsp->dram_offset = offset; 162 offset >>= DRAM_REMAP_SHIFT; 163 dev_dbg(dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset); 164 writel(offset, vaddr_emi_map); 165 if (offset != readl(vaddr_emi_map)) { 166 dev_err(dev, "write emi map fail : %#x\n", readl(vaddr_emi_map)); 167 return -EIO; 168 } 169 170 return 0; 171 } 172 173 static int mt8195_run(struct snd_sof_dev *sdev) 174 { 175 u32 adsp_bootup_addr; 176 177 adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW; 178 dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr); 179 sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr); 180 181 return 0; 182 } 183 184 static int mt8195_dsp_probe(struct snd_sof_dev *sdev) 185 { 186 struct platform_device *pdev = to_platform_device(sdev->dev); 187 struct adsp_priv *priv; 188 int ret; 189 190 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 191 if (!priv) 192 return -ENOMEM; 193 194 sdev->pdata->hw_pdata = priv; 195 priv->dev = sdev->dev; 196 priv->sdev = sdev; 197 198 priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL); 199 if (!priv->adsp) 200 return -ENOMEM; 201 202 ret = platform_parse_resource(pdev, priv->adsp); 203 if (ret) 204 return ret; 205 206 ret = mt8195_adsp_init_clock(sdev); 207 if (ret) { 208 dev_err(sdev->dev, "mt8195_adsp_init_clock failed\n"); 209 return -EINVAL; 210 } 211 212 ret = adsp_clock_on(sdev); 213 if (ret) { 214 dev_err(sdev->dev, "adsp_clock_on fail!\n"); 215 return -EINVAL; 216 } 217 218 ret = adsp_sram_power_on(sdev->dev, true); 219 if (ret) { 220 dev_err(sdev->dev, "adsp_sram_power_on fail!\n"); 221 goto exit_clk_disable; 222 } 223 224 ret = adsp_memory_remap_init(&pdev->dev, priv->adsp); 225 if (ret) { 226 dev_err(sdev->dev, "adsp_memory_remap_init fail!\n"); 227 goto err_adsp_sram_power_off; 228 } 229 230 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, 231 priv->adsp->pa_sram, 232 priv->adsp->sramsize); 233 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) { 234 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n", 235 &priv->adsp->pa_sram, priv->adsp->sramsize); 236 ret = -EINVAL; 237 goto err_adsp_sram_power_off; 238 } 239 240 priv->adsp->va_sram = sdev->bar[SOF_FW_BLK_TYPE_IRAM]; 241 242 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap(sdev->dev, 243 priv->adsp->pa_dram, 244 priv->adsp->dramsize); 245 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) { 246 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n", 247 &priv->adsp->pa_dram, priv->adsp->dramsize); 248 ret = -EINVAL; 249 goto err_adsp_sram_power_off; 250 } 251 priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM]; 252 253 sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg; 254 255 sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM; 256 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM; 257 258 /* set default mailbox offset for FW ready message */ 259 sdev->dsp_box.offset = mt8195_get_mailbox_offset(sdev); 260 261 priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc", 262 PLATFORM_DEVID_NONE, 263 pdev, sizeof(*pdev)); 264 if (IS_ERR(priv->ipc_dev)) { 265 ret = PTR_ERR(priv->ipc_dev); 266 dev_err(sdev->dev, "failed to register mtk-adsp-ipc device\n"); 267 goto err_adsp_sram_power_off; 268 } 269 270 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev); 271 if (!priv->dsp_ipc) { 272 ret = -EPROBE_DEFER; 273 dev_err(sdev->dev, "failed to get drvdata\n"); 274 goto exit_pdev_unregister; 275 } 276 277 mtk_adsp_ipc_set_data(priv->dsp_ipc, priv); 278 priv->dsp_ipc->ops = &dsp_ops; 279 280 return 0; 281 282 exit_pdev_unregister: 283 platform_device_unregister(priv->ipc_dev); 284 err_adsp_sram_power_off: 285 adsp_sram_power_on(&pdev->dev, false); 286 exit_clk_disable: 287 adsp_clock_off(sdev); 288 289 return ret; 290 } 291 292 static int mt8195_dsp_shutdown(struct snd_sof_dev *sdev) 293 { 294 return snd_sof_suspend(sdev->dev); 295 } 296 297 static void mt8195_dsp_remove(struct snd_sof_dev *sdev) 298 { 299 struct platform_device *pdev = to_platform_device(sdev->dev); 300 struct adsp_priv *priv = sdev->pdata->hw_pdata; 301 302 platform_device_unregister(priv->ipc_dev); 303 adsp_sram_power_on(&pdev->dev, false); 304 adsp_clock_off(sdev); 305 } 306 307 static int mt8195_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state) 308 { 309 struct platform_device *pdev = to_platform_device(sdev->dev); 310 int ret; 311 u32 reset_sw, dbg_pc; 312 313 /* wait dsp enter idle, timeout is 1 second */ 314 ret = snd_sof_dsp_read_poll_timeout(sdev, DSP_REG_BAR, 315 DSP_RESET_SW, reset_sw, 316 ((reset_sw & ADSP_PWAIT) == ADSP_PWAIT), 317 SUSPEND_DSP_IDLE_POLL_INTERVAL_US, 318 SUSPEND_DSP_IDLE_TIMEOUT_US); 319 if (ret < 0) { 320 dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC); 321 dev_warn(sdev->dev, "dsp not idle, powering off anyway : swrest %#x, pc %#x, ret %d\n", 322 reset_sw, dbg_pc, ret); 323 } 324 325 /* stall and reset dsp */ 326 sof_hifixdsp_shutdown(sdev); 327 328 /* power down adsp sram */ 329 ret = adsp_sram_power_on(&pdev->dev, false); 330 if (ret) { 331 dev_err(sdev->dev, "adsp_sram_power_off fail!\n"); 332 return ret; 333 } 334 335 /* turn off adsp clock */ 336 return adsp_clock_off(sdev); 337 } 338 339 static int mt8195_dsp_resume(struct snd_sof_dev *sdev) 340 { 341 int ret; 342 343 /* turn on adsp clock */ 344 ret = adsp_clock_on(sdev); 345 if (ret) { 346 dev_err(sdev->dev, "adsp_clock_on fail!\n"); 347 return ret; 348 } 349 350 /* power on adsp sram */ 351 ret = adsp_sram_power_on(sdev->dev, true); 352 if (ret) 353 dev_err(sdev->dev, "adsp_sram_power_on fail!\n"); 354 355 return ret; 356 } 357 358 static void mt8195_adsp_dump(struct snd_sof_dev *sdev, u32 flags) 359 { 360 u32 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, dbg_inst; 361 u32 dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo, swrest; 362 363 /* dump debug registers */ 364 dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC); 365 dbg_data = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGDATA); 366 dbg_bus0 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS0); 367 dbg_bus1 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS1); 368 dbg_inst = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGINST); 369 dbg_ls0stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS0STAT); 370 dbg_ls1stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS1STAT); 371 faultbus = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTBUS); 372 faultinfo = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTINFO); 373 swrest = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_RESET_SW); 374 375 dev_info(sdev->dev, "adsp dump : pc %#x, data %#x, bus0 %#x, bus1 %#x, swrest %#x", 376 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, swrest); 377 dev_info(sdev->dev, "dbg_inst %#x, ls0stat %#x, ls1stat %#x, faultbus %#x, faultinfo %#x", 378 dbg_inst, dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo); 379 380 mtk_adsp_dump(sdev, flags); 381 } 382 383 static struct snd_soc_dai_driver mt8195_dai[] = { 384 { 385 .name = "SOF_DL2", 386 .playback = { 387 .channels_min = 1, 388 .channels_max = 2, 389 }, 390 }, 391 { 392 .name = "SOF_DL3", 393 .playback = { 394 .channels_min = 1, 395 .channels_max = 2, 396 }, 397 }, 398 { 399 .name = "SOF_UL4", 400 .capture = { 401 .channels_min = 1, 402 .channels_max = 2, 403 }, 404 }, 405 { 406 .name = "SOF_UL5", 407 .capture = { 408 .channels_min = 1, 409 .channels_max = 2, 410 }, 411 }, 412 }; 413 414 /* mt8195 ops */ 415 static const struct snd_sof_dsp_ops sof_mt8195_ops = { 416 /* probe and remove */ 417 .probe = mt8195_dsp_probe, 418 .remove = mt8195_dsp_remove, 419 .shutdown = mt8195_dsp_shutdown, 420 421 /* DSP core boot */ 422 .run = mt8195_run, 423 424 /* Block IO */ 425 .block_read = sof_block_read, 426 .block_write = sof_block_write, 427 428 /* Mailbox IO */ 429 .mailbox_read = sof_mailbox_read, 430 .mailbox_write = sof_mailbox_write, 431 432 /* Register IO */ 433 .write = sof_io_write, 434 .read = sof_io_read, 435 .write64 = sof_io_write64, 436 .read64 = sof_io_read64, 437 438 /* ipc */ 439 .send_msg = mtk_adsp_send_msg, 440 .get_mailbox_offset = mt8195_get_mailbox_offset, 441 .get_window_offset = mt8195_get_window_offset, 442 .ipc_msg_data = sof_ipc_msg_data, 443 .set_stream_data_offset = sof_set_stream_data_offset, 444 445 /* misc */ 446 .get_bar_index = mtk_adsp_get_bar_index, 447 448 /* stream callbacks */ 449 .pcm_open = sof_stream_pcm_open, 450 .pcm_hw_params = mtk_adsp_stream_pcm_hw_params, 451 .pcm_pointer = mtk_adsp_stream_pcm_pointer, 452 .pcm_close = sof_stream_pcm_close, 453 454 /* firmware loading */ 455 .load_firmware = snd_sof_load_firmware_memcpy, 456 457 /* Firmware ops */ 458 .dsp_arch_ops = &sof_xtensa_arch_ops, 459 460 /* Debug information */ 461 .dbg_dump = mt8195_adsp_dump, 462 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 463 464 /* DAI drivers */ 465 .drv = mt8195_dai, 466 .num_drv = ARRAY_SIZE(mt8195_dai), 467 468 /* PM */ 469 .suspend = mt8195_dsp_suspend, 470 .resume = mt8195_dsp_resume, 471 472 /* ALSA HW info flags */ 473 .hw_info = SNDRV_PCM_INFO_MMAP | 474 SNDRV_PCM_INFO_MMAP_VALID | 475 SNDRV_PCM_INFO_INTERLEAVED | 476 SNDRV_PCM_INFO_PAUSE | 477 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 478 }; 479 480 static struct snd_sof_of_mach sof_mt8195_machs[] = { 481 { 482 .compatible = "google,tomato", 483 .sof_tplg_filename = "sof-mt8195-mt6359-rt1019-rt5682.tplg" 484 }, { 485 .compatible = "google,dojo", 486 .sof_tplg_filename = "sof-mt8195-mt6359-max98390-rt5682.tplg" 487 }, { 488 .compatible = "mediatek,mt8195", 489 .sof_tplg_filename = "sof-mt8195.tplg" 490 }, { 491 /* sentinel */ 492 } 493 }; 494 495 static const struct sof_dev_desc sof_of_mt8195_desc = { 496 .of_machines = sof_mt8195_machs, 497 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3), 498 .ipc_default = SOF_IPC_TYPE_3, 499 .default_fw_path = { 500 [SOF_IPC_TYPE_3] = "mediatek/sof", 501 }, 502 .default_tplg_path = { 503 [SOF_IPC_TYPE_3] = "mediatek/sof-tplg", 504 }, 505 .default_fw_filename = { 506 [SOF_IPC_TYPE_3] = "sof-mt8195.ri", 507 }, 508 .nocodec_tplg_filename = "sof-mt8195-nocodec.tplg", 509 .ops = &sof_mt8195_ops, 510 .ipc_timeout = 1000, 511 }; 512 513 static const struct of_device_id sof_of_mt8195_ids[] = { 514 { .compatible = "mediatek,mt8195-dsp", .data = &sof_of_mt8195_desc}, 515 { } 516 }; 517 MODULE_DEVICE_TABLE(of, sof_of_mt8195_ids); 518 519 /* DT driver definition */ 520 static struct platform_driver snd_sof_of_mt8195_driver = { 521 .probe = sof_of_probe, 522 .remove = sof_of_remove, 523 .shutdown = sof_of_shutdown, 524 .driver = { 525 .name = "sof-audio-of-mt8195", 526 .pm = pm_ptr(&sof_of_pm), 527 .of_match_table = sof_of_mt8195_ids, 528 }, 529 }; 530 module_platform_driver(snd_sof_of_mt8195_driver); 531 532 MODULE_LICENSE("Dual BSD/GPL"); 533 MODULE_DESCRIPTION("SOF support for MTL 8195 platforms"); 534 MODULE_IMPORT_NS("SND_SOC_SOF_XTENSA"); 535 MODULE_IMPORT_NS("SND_SOC_SOF_MTK_COMMON"); 536