1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2024-2025 Intel Corporation 4 * 5 * Authors: Cezary Rojewski <cezary.rojewski@intel.com> 6 * Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com> 7 */ 8 9 #include <sound/hdaudio_ext.h> 10 #include "avs.h" 11 #include "registers.h" 12 #include "trace.h" 13 14 #define MTL_HfDSSGBL_BASE 0x1000 15 #define MTL_REG_HfDSSCS (MTL_HfDSSGBL_BASE + 0x0) 16 #define MTL_HfDSSCS_SPA BIT(16) 17 #define MTL_HfDSSCS_CPA BIT(24) 18 19 #define MTL_DSPCS_BASE 0x178D00 20 #define MTL_REG_DSPCCTL (MTL_DSPCS_BASE + 0x4) 21 #define MTL_DSPCCTL_OSEL GENMASK(25, 24) 22 #define MTL_DSPCCTL_OSEL_HOST BIT(25) 23 24 static int avs_ptl_core_power_on(struct avs_dev *adev) 25 { 26 u32 reg; 27 int ret; 28 29 /* Power up DSP domain. */ 30 snd_hdac_adsp_updatel(adev, MTL_REG_HfDSSCS, MTL_HfDSSCS_SPA, MTL_HfDSSCS_SPA); 31 trace_avs_dsp_core_op(1, AVS_MAIN_CORE_MASK, "power dsp", true); 32 33 ret = snd_hdac_adsp_readl_poll(adev, MTL_REG_HfDSSCS, reg, 34 (reg & MTL_HfDSSCS_CPA) == MTL_HfDSSCS_CPA, 35 AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US); 36 if (ret) { 37 dev_err(adev->dev, "power on domain dsp failed: %d\n", ret); 38 return ret; 39 } 40 41 /* Prevent power gating of DSP domain. */ 42 snd_hdac_adsp_updatel(adev, MTL_REG_HfPWRCTL2, MTL_HfPWRCTL2_WPDSPHPxPG, 43 MTL_HfPWRCTL2_WPDSPHPxPG); 44 trace_avs_dsp_core_op(1, AVS_MAIN_CORE_MASK, "prevent dsp PG", true); 45 46 ret = snd_hdac_adsp_readl_poll(adev, MTL_REG_HfPWRSTS2, reg, 47 (reg & MTL_HfPWRSTS2_DSPHPxPGS) == MTL_HfPWRSTS2_DSPHPxPGS, 48 AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US); 49 50 /* Set ownership to HOST. */ 51 snd_hdac_adsp_updatel(adev, MTL_REG_DSPCCTL, MTL_DSPCCTL_OSEL, MTL_DSPCCTL_OSEL_HOST); 52 return ret; 53 } 54 55 static int avs_ptl_core_power_off(struct avs_dev *adev) 56 { 57 u32 reg; 58 59 /* Allow power gating of DSP domain. No STS polling as HOST is only one of its users. */ 60 snd_hdac_adsp_updatel(adev, MTL_REG_HfPWRCTL2, MTL_HfPWRCTL2_WPDSPHPxPG, 0); 61 trace_avs_dsp_core_op(0, AVS_MAIN_CORE_MASK, "allow dsp pg", false); 62 63 /* Power down DSP domain. */ 64 snd_hdac_adsp_updatel(adev, MTL_REG_HfDSSCS, MTL_HfDSSCS_SPA, 0); 65 trace_avs_dsp_core_op(0, AVS_MAIN_CORE_MASK, "power dsp", false); 66 67 return snd_hdac_adsp_readl_poll(adev, MTL_REG_HfDSSCS, reg, 68 (reg & MTL_HfDSSCS_CPA) == 0, 69 AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US); 70 } 71 72 static int avs_ptl_core_power(struct avs_dev *adev, u32 core_mask, bool power) 73 { 74 core_mask &= AVS_MAIN_CORE_MASK; 75 if (!core_mask) 76 return 0; 77 78 if (power) 79 return avs_ptl_core_power_on(adev); 80 return avs_ptl_core_power_off(adev); 81 } 82 83 const struct avs_dsp_ops avs_ptl_dsp_ops = { 84 .power = avs_ptl_core_power, 85 .reset = avs_mtl_core_reset, 86 .stall = avs_lnl_core_stall, 87 .dsp_interrupt = avs_mtl_dsp_interrupt, 88 .int_control = avs_mtl_interrupt_control, 89 .load_basefw = avs_hda_load_basefw, 90 .load_lib = avs_hda_load_library, 91 .transfer_mods = avs_hda_transfer_modules, 92 .log_buffer_offset = avs_icl_log_buffer_offset, 93 .log_buffer_status = avs_apl_log_buffer_status, 94 .coredump = avs_apl_coredump, 95 .d0ix_toggle = avs_icl_d0ix_toggle, 96 .set_d0ix = avs_icl_set_d0ix, 97 AVS_SET_ENABLE_LOGS_OP(icl) 98 }; 99