1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2023, Linaro Limited 6 */ 7 8 #include <linux/module.h> 9 #include <linux/slab.h> 10 #include <linux/platform_device.h> 11 #include <linux/device.h> 12 #include <linux/delay.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/kernel.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/component.h> 17 #include <sound/tlv.h> 18 #include <linux/of_graph.h> 19 #include <linux/of.h> 20 #include <sound/jack.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 #include <linux/regmap.h> 24 #include <sound/soc.h> 25 #include <sound/soc-dapm.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/usb/typec_mux.h> 28 #include <linux/usb/typec_altmode.h> 29 30 #include "wcd-clsh-v2.h" 31 #include "wcd-mbhc-v2.h" 32 #include "wcd939x.h" 33 34 #define WCD939X_MAX_MICBIAS (4) 35 #define WCD939X_MAX_SUPPLY (4) 36 #define WCD939X_MBHC_MAX_BUTTONS (8) 37 #define TX_ADC_MAX (4) 38 #define WCD_MBHC_HS_V_MAX 1600 39 40 enum { 41 WCD939X_VERSION_1_0 = 0, 42 WCD939X_VERSION_1_1, 43 WCD939X_VERSION_2_0, 44 }; 45 46 #define WCD939X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 47 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 48 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ 49 SNDRV_PCM_RATE_384000) 50 /* Fractional Rates */ 51 #define WCD939X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 52 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) 53 #define WCD939X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 54 SNDRV_PCM_FMTBIT_S24_LE |\ 55 SNDRV_PCM_FMTBIT_S24_3LE |\ 56 SNDRV_PCM_FMTBIT_S32_LE) 57 58 /* Convert from vout ctl to micbias voltage in mV */ 59 #define WCD_VOUT_CTL_TO_MICB(v) (1000 + (v) * 50) 60 #define SWR_CLK_RATE_0P6MHZ (600000) 61 #define SWR_CLK_RATE_1P2MHZ (1200000) 62 #define SWR_CLK_RATE_2P4MHZ (2400000) 63 #define SWR_CLK_RATE_4P8MHZ (4800000) 64 #define SWR_CLK_RATE_9P6MHZ (9600000) 65 #define SWR_CLK_RATE_11P2896MHZ (1128960) 66 67 #define ADC_MODE_VAL_HIFI 0x01 68 #define ADC_MODE_VAL_LO_HIF 0x02 69 #define ADC_MODE_VAL_NORMAL 0x03 70 #define ADC_MODE_VAL_LP 0x05 71 #define ADC_MODE_VAL_ULP1 0x09 72 #define ADC_MODE_VAL_ULP2 0x0B 73 74 /* Z value defined in milliohm */ 75 #define WCD939X_ZDET_VAL_32 (32000) 76 #define WCD939X_ZDET_VAL_400 (400000) 77 #define WCD939X_ZDET_VAL_1200 (1200000) 78 #define WCD939X_ZDET_VAL_100K (100000000) 79 80 /* Z floating defined in ohms */ 81 #define WCD939X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 82 #define WCD939X_ZDET_NUM_MEASUREMENTS (900) 83 #define WCD939X_MBHC_GET_C1(c) (((c) & 0xC000) >> 14) 84 #define WCD939X_MBHC_GET_X1(x) ((x) & 0x3FFF) 85 86 /* Z value compared in milliOhm */ 87 #define WCD939X_ANA_MBHC_ZDET_CONST (1018 * 1024) 88 89 enum { 90 WCD9390 = 0, 91 WCD9395 = 5, 92 }; 93 94 enum { 95 /* INTR_CTRL_INT_MASK_0 */ 96 WCD939X_IRQ_MBHC_BUTTON_PRESS_DET = 0, 97 WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET, 98 WCD939X_IRQ_MBHC_ELECT_INS_REM_DET, 99 WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 100 WCD939X_IRQ_MBHC_SW_DET, 101 WCD939X_IRQ_HPHR_OCP_INT, 102 WCD939X_IRQ_HPHR_CNP_INT, 103 WCD939X_IRQ_HPHL_OCP_INT, 104 105 /* INTR_CTRL_INT_MASK_1 */ 106 WCD939X_IRQ_HPHL_CNP_INT, 107 WCD939X_IRQ_EAR_CNP_INT, 108 WCD939X_IRQ_EAR_SCD_INT, 109 WCD939X_IRQ_HPHL_PDM_WD_INT, 110 WCD939X_IRQ_HPHR_PDM_WD_INT, 111 WCD939X_IRQ_EAR_PDM_WD_INT, 112 113 /* INTR_CTRL_INT_MASK_2 */ 114 WCD939X_IRQ_MBHC_MOISTURE_INT, 115 WCD939X_IRQ_HPHL_SURGE_DET_INT, 116 WCD939X_IRQ_HPHR_SURGE_DET_INT, 117 WCD939X_NUM_IRQS, 118 }; 119 120 enum { 121 MICB_BIAS_DISABLE = 0, 122 MICB_BIAS_ENABLE, 123 MICB_BIAS_PULL_UP, 124 MICB_BIAS_PULL_DOWN, 125 }; 126 127 enum { 128 WCD_ADC1 = 0, 129 WCD_ADC2, 130 WCD_ADC3, 131 WCD_ADC4, 132 HPH_PA_DELAY, 133 }; 134 135 enum { 136 ADC_MODE_INVALID = 0, 137 ADC_MODE_HIFI, 138 ADC_MODE_LO_HIF, 139 ADC_MODE_NORMAL, 140 ADC_MODE_LP, 141 ADC_MODE_ULP1, 142 ADC_MODE_ULP2, 143 }; 144 145 enum { 146 AIF1_PB = 0, 147 AIF1_CAP, 148 NUM_CODEC_DAIS, 149 }; 150 151 static u8 tx_mode_bit[] = { 152 [ADC_MODE_INVALID] = 0x00, 153 [ADC_MODE_HIFI] = 0x01, 154 [ADC_MODE_LO_HIF] = 0x02, 155 [ADC_MODE_NORMAL] = 0x04, 156 [ADC_MODE_LP] = 0x08, 157 [ADC_MODE_ULP1] = 0x10, 158 [ADC_MODE_ULP2] = 0x20, 159 }; 160 161 struct zdet_param { 162 u16 ldo_ctl; 163 u16 noff; 164 u16 nshift; 165 u16 btn5; 166 u16 btn6; 167 u16 btn7; 168 }; 169 170 struct wcd939x_priv { 171 struct sdw_slave *tx_sdw_dev; 172 struct wcd939x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 173 struct device *txdev; 174 struct device *rxdev; 175 struct device_node *rxnode, *txnode; 176 struct regmap *regmap; 177 struct snd_soc_component *component; 178 /* micb setup lock */ 179 struct mutex micb_lock; 180 /* typec handling */ 181 bool typec_analog_mux; 182 #if IS_ENABLED(CONFIG_TYPEC) 183 enum typec_orientation typec_orientation; 184 unsigned long typec_mode; 185 struct typec_switch *typec_switch; 186 #endif /* CONFIG_TYPEC */ 187 /* mbhc module */ 188 struct wcd_mbhc *wcd_mbhc; 189 struct wcd_mbhc_config mbhc_cfg; 190 struct wcd_mbhc_intr intr_ids; 191 struct wcd_clsh_ctrl *clsh_info; 192 struct irq_domain *virq; 193 struct regmap_irq_chip *wcd_regmap_irq_chip; 194 struct regmap_irq_chip_data *irq_chip; 195 struct regulator_bulk_data supplies[WCD939X_MAX_SUPPLY]; 196 struct snd_soc_jack *jack; 197 unsigned long status_mask; 198 s32 micb_ref[WCD939X_MAX_MICBIAS]; 199 s32 pullup_ref[WCD939X_MAX_MICBIAS]; 200 u32 hph_mode; 201 u32 tx_mode[TX_ADC_MAX]; 202 int variant; 203 struct gpio_desc *reset_gpio; 204 u32 micb1_mv; 205 u32 micb2_mv; 206 u32 micb3_mv; 207 u32 micb4_mv; 208 int hphr_pdm_wd_int; 209 int hphl_pdm_wd_int; 210 int ear_pdm_wd_int; 211 bool comp1_enable; 212 bool comp2_enable; 213 bool ldoh; 214 }; 215 216 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 217 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 218 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 219 220 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 221 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD939X_ANA_MBHC_MECH, 0x80), 222 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD939X_ANA_MBHC_MECH, 0x40), 223 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD939X_ANA_MBHC_MECH, 0x20), 224 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD939X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 225 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD939X_ANA_MBHC_ELECT, 0x08), 226 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD939X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 227 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD939X_ANA_MBHC_MECH, 0x04), 228 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD939X_ANA_MBHC_MECH, 0x10), 229 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD939X_ANA_MBHC_MECH, 0x08), 230 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD939X_ANA_MBHC_MECH, 0x01), 231 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD939X_ANA_MBHC_ELECT, 0x06), 232 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD939X_ANA_MBHC_ELECT, 0x80), 233 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD939X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 234 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD939X_MBHC_NEW_CTL_1, 0x03), 235 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD939X_MBHC_NEW_CTL_2, 0x03), 236 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x08), 237 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD939X_ANA_MBHC_RESULT_3, 0x10), 238 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x20), 239 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x80), 240 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x40), 241 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD939X_HPH_OCP_CTL, 0x10), 242 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x07), 243 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD939X_ANA_MBHC_ELECT, 0x70), 244 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0xFF), 245 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD939X_ANA_MICB2, 0xC0), 246 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD939X_HPH_CNP_WG_TIME, 0xFF), 247 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD939X_ANA_HPH, 0x40), 248 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD939X_ANA_HPH, 0x80), 249 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD939X_ANA_HPH, 0xC0), 250 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD939X_ANA_MBHC_RESULT_3, 0x10), 251 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD939X_MBHC_CTL_BCS, 0x02), 252 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD939X_MBHC_NEW_FSM_STATUS, 0x01), 253 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD939X_MBHC_NEW_CTL_2, 0x70), 254 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD939X_MBHC_NEW_FSM_STATUS, 0x20), 255 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD939X_HPH_PA_CTL2, 0x40), 256 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD939X_HPH_PA_CTL2, 0x10), 257 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD939X_HPH_L_TEST, 0x01), 258 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD939X_HPH_R_TEST, 0x01), 259 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD939X_DIGITAL_INTR_STATUS_0, 0x80), 260 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD939X_DIGITAL_INTR_STATUS_0, 0x20), 261 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD939X_MBHC_NEW_CTL_1, 0x08), 262 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD939X_MBHC_NEW_FSM_STATUS, 0x40), 263 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD939X_MBHC_NEW_FSM_STATUS, 0x80), 264 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD939X_MBHC_NEW_ADC_RESULT, 0xFF), 265 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD939X_ANA_MICB2, 0x3F), 266 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD939X_MBHC_NEW_CTL_1, 0x10), 267 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD939X_MBHC_NEW_CTL_1, 0x04), 268 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD939X_ANA_MBHC_ZDET, 0x02), 269 }; 270 271 static const struct regmap_irq wcd939x_irqs[WCD939X_NUM_IRQS] = { 272 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01), 273 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02), 274 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04), 275 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08), 276 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_SW_DET, 0, 0x10), 277 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_OCP_INT, 0, 0x20), 278 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_CNP_INT, 0, 0x40), 279 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_OCP_INT, 0, 0x80), 280 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_CNP_INT, 1, 0x01), 281 REGMAP_IRQ_REG(WCD939X_IRQ_EAR_CNP_INT, 1, 0x02), 282 REGMAP_IRQ_REG(WCD939X_IRQ_EAR_SCD_INT, 1, 0x04), 283 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_PDM_WD_INT, 1, 0x20), 284 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_PDM_WD_INT, 1, 0x40), 285 REGMAP_IRQ_REG(WCD939X_IRQ_EAR_PDM_WD_INT, 1, 0x80), 286 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_MOISTURE_INT, 2, 0x02), 287 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04), 288 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08), 289 }; 290 291 static const struct regmap_irq_chip wcd939x_regmap_irq_chip = { 292 .name = "wcd939x", 293 .irqs = wcd939x_irqs, 294 .num_irqs = ARRAY_SIZE(wcd939x_irqs), 295 .num_regs = 3, 296 .status_base = WCD939X_DIGITAL_INTR_STATUS_0, 297 .mask_base = WCD939X_DIGITAL_INTR_MASK_0, 298 .ack_base = WCD939X_DIGITAL_INTR_CLEAR_0, 299 .use_ack = 1, 300 .runtime_pm = true, 301 .irq_drv_data = NULL, 302 }; 303 304 static int wcd939x_get_clk_rate(int mode) 305 { 306 int rate; 307 308 switch (mode) { 309 case ADC_MODE_ULP2: 310 rate = SWR_CLK_RATE_0P6MHZ; 311 break; 312 case ADC_MODE_ULP1: 313 rate = SWR_CLK_RATE_1P2MHZ; 314 break; 315 case ADC_MODE_LP: 316 rate = SWR_CLK_RATE_4P8MHZ; 317 break; 318 case ADC_MODE_NORMAL: 319 case ADC_MODE_LO_HIF: 320 case ADC_MODE_HIFI: 321 case ADC_MODE_INVALID: 322 default: 323 rate = SWR_CLK_RATE_9P6MHZ; 324 break; 325 } 326 327 return rate; 328 } 329 330 static int wcd939x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank) 331 { 332 u8 mask = (bank ? 0xF0 : 0x0F); 333 u8 val = 0; 334 335 switch (rate) { 336 case SWR_CLK_RATE_0P6MHZ: 337 val = 6; 338 break; 339 case SWR_CLK_RATE_1P2MHZ: 340 val = 5; 341 break; 342 case SWR_CLK_RATE_2P4MHZ: 343 val = 3; 344 break; 345 case SWR_CLK_RATE_4P8MHZ: 346 val = 1; 347 break; 348 case SWR_CLK_RATE_9P6MHZ: 349 default: 350 val = 0; 351 break; 352 } 353 354 snd_soc_component_write_field(component, WCD939X_DIGITAL_SWR_TX_CLK_RATE, mask, val); 355 356 return 0; 357 } 358 359 static int wcd939x_io_init(struct snd_soc_component *component) 360 { 361 snd_soc_component_write_field(component, WCD939X_ANA_BIAS, 362 WCD939X_BIAS_ANALOG_BIAS_EN, true); 363 snd_soc_component_write_field(component, WCD939X_ANA_BIAS, 364 WCD939X_BIAS_PRECHRG_EN, true); 365 366 /* 10 msec delay as per HW requirement */ 367 usleep_range(10000, 10010); 368 snd_soc_component_write_field(component, WCD939X_ANA_BIAS, 369 WCD939X_BIAS_PRECHRG_EN, false); 370 371 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L, 372 WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 0x15); 373 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R, 374 WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 0x15); 375 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL, 376 WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN, true); 377 378 snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_ULP, 379 WCD939X_FE_ICTRL_STG2CASC_ULP_ICTRL_SCBIAS_ULP0P6M, 1); 380 snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_ULP, 381 WCD939X_FE_ICTRL_STG2CASC_ULP_VALUE, 4); 382 383 snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2MAIN_ULP, 384 WCD939X_FE_ICTRL_STG2MAIN_ULP_VALUE, 8); 385 386 snd_soc_component_write_field(component, WCD939X_MICB1_TEST_CTL_1, 387 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7); 388 snd_soc_component_write_field(component, WCD939X_MICB2_TEST_CTL_1, 389 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7); 390 snd_soc_component_write_field(component, WCD939X_MICB3_TEST_CTL_1, 391 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7); 392 snd_soc_component_write_field(component, WCD939X_MICB4_TEST_CTL_1, 393 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7); 394 snd_soc_component_write_field(component, WCD939X_TX_3_4_TEST_BLK_EN2, 395 WCD939X_TEST_BLK_EN2_TXFE2_MBHC_CLKRST_EN, false); 396 397 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN, 398 WCD939X_EN_EN_SURGE_PROTECTION_HPHL, false); 399 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN, 400 WCD939X_EN_EN_SURGE_PROTECTION_HPHR, false); 401 402 snd_soc_component_write_field(component, WCD939X_HPH_OCP_CTL, 403 WCD939X_OCP_CTL_OCP_FSM_EN, true); 404 snd_soc_component_write_field(component, WCD939X_HPH_OCP_CTL, 405 WCD939X_OCP_CTL_SCD_OP_EN, true); 406 407 snd_soc_component_write(component, WCD939X_E_CFG0, 408 WCD939X_CFG0_IDLE_STEREO | 409 WCD939X_CFG0_AUTO_DISABLE_ANC); 410 411 return 0; 412 } 413 414 static int wcd939x_sdw_connect_port(const struct wcd939x_sdw_ch_info *ch_info, 415 struct sdw_port_config *port_config, 416 u8 enable) 417 { 418 u8 ch_mask, port_num; 419 420 port_num = ch_info->port_num; 421 ch_mask = ch_info->ch_mask; 422 423 port_config->num = port_num; 424 425 if (enable) 426 port_config->ch_mask |= ch_mask; 427 else 428 port_config->ch_mask &= ~ch_mask; 429 430 return 0; 431 } 432 433 static int wcd939x_connect_port(struct wcd939x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable) 434 { 435 return wcd939x_sdw_connect_port(&wcd->ch_info[ch_id], 436 &wcd->port_config[port_num - 1], 437 enable); 438 } 439 440 static int wcd939x_codec_enable_rxclk(struct snd_soc_dapm_widget *w, 441 struct snd_kcontrol *kcontrol, 442 int event) 443 { 444 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 445 446 switch (event) { 447 case SND_SOC_DAPM_PRE_PMU: 448 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES, 449 WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE, true); 450 451 /* Analog path clock controls */ 452 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 453 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN, true); 454 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 455 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN, 456 true); 457 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 458 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN, 459 true); 460 461 /* Digital path clock controls */ 462 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 463 WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN, true); 464 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 465 WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN, true); 466 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 467 WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN, true); 468 break; 469 case SND_SOC_DAPM_POST_PMD: 470 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES, 471 WCD939X_RX_SUPPLIES_VNEG_EN, false); 472 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES, 473 WCD939X_RX_SUPPLIES_VPOS_EN, false); 474 475 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 476 WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN, false); 477 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 478 WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN, false); 479 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 480 WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN, false); 481 482 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 483 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN, 484 false); 485 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 486 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN, 487 false); 488 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 489 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN, false); 490 491 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES, 492 WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE, false); 493 494 break; 495 } 496 497 return 0; 498 } 499 500 static int wcd939x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 501 struct snd_kcontrol *kcontrol, 502 int event) 503 { 504 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 505 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 506 507 switch (event) { 508 case SND_SOC_DAPM_PRE_PMU: 509 snd_soc_component_write_field(component, WCD939X_HPH_RDAC_CLK_CTL1, 510 WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN, 511 false); 512 513 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL, 514 WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN, true); 515 break; 516 case SND_SOC_DAPM_POST_PMU: 517 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L, 518 WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 0x1d); 519 if (wcd939x->comp1_enable) { 520 snd_soc_component_write_field(component, 521 WCD939X_DIGITAL_CDC_COMP_CTL_0, 522 WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN, 523 true); 524 /* 5msec compander delay as per HW requirement */ 525 if (!wcd939x->comp2_enable || 526 snd_soc_component_read_field(component, 527 WCD939X_DIGITAL_CDC_COMP_CTL_0, 528 WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN)) 529 usleep_range(5000, 5010); 530 531 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1, 532 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, 533 false); 534 } else { 535 snd_soc_component_write_field(component, 536 WCD939X_DIGITAL_CDC_COMP_CTL_0, 537 WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN, 538 false); 539 snd_soc_component_write_field(component, WCD939X_HPH_L_EN, 540 WCD939X_L_EN_GAIN_SOURCE_SEL, true); 541 } 542 break; 543 case SND_SOC_DAPM_POST_PMD: 544 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L, 545 WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 1); 546 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL, 547 WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN, false); 548 break; 549 } 550 551 return 0; 552 } 553 554 static int wcd939x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 555 struct snd_kcontrol *kcontrol, 556 int event) 557 { 558 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 559 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 560 561 dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__, 562 w->name, event); 563 564 switch (event) { 565 case SND_SOC_DAPM_PRE_PMU: 566 snd_soc_component_write_field(component, WCD939X_HPH_RDAC_CLK_CTL1, 567 WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN, 568 false); 569 570 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL, 571 WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN, true); 572 break; 573 case SND_SOC_DAPM_POST_PMU: 574 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R, 575 WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 0x1d); 576 if (wcd939x->comp2_enable) { 577 snd_soc_component_write_field(component, 578 WCD939X_DIGITAL_CDC_COMP_CTL_0, 579 WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN, 580 true); 581 /* 5msec compander delay as per HW requirement */ 582 if (!wcd939x->comp1_enable || 583 snd_soc_component_read_field(component, 584 WCD939X_DIGITAL_CDC_COMP_CTL_0, 585 WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN)) 586 usleep_range(5000, 5010); 587 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1, 588 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, 589 false); 590 } else { 591 snd_soc_component_write_field(component, 592 WCD939X_DIGITAL_CDC_COMP_CTL_0, 593 WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN, 594 false); 595 snd_soc_component_write_field(component, WCD939X_HPH_R_EN, 596 WCD939X_R_EN_GAIN_SOURCE_SEL, true); 597 } 598 break; 599 case SND_SOC_DAPM_POST_PMD: 600 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R, 601 WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 1); 602 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL, 603 WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN, false); 604 break; 605 } 606 607 return 0; 608 } 609 610 static int wcd939x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 611 struct snd_kcontrol *kcontrol, 612 int event) 613 { 614 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 615 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 616 617 switch (event) { 618 case SND_SOC_DAPM_PRE_PMU: 619 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_EAR_GAIN_CTL, 620 WCD939X_CDC_EAR_GAIN_CTL_EAR_EN, true); 621 622 snd_soc_component_write_field(component, WCD939X_EAR_DAC_CON, 623 WCD939X_DAC_CON_DAC_SAMPLE_EDGE_SEL, false); 624 625 /* 5 msec delay as per HW requirement */ 626 usleep_range(5000, 5010); 627 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 628 WCD_CLSH_STATE_EAR, CLS_AB_HIFI); 629 630 snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4, 631 WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd); 632 break; 633 case SND_SOC_DAPM_POST_PMD: 634 snd_soc_component_write_field(component, WCD939X_EAR_DAC_CON, 635 WCD939X_DAC_CON_DAC_SAMPLE_EDGE_SEL, true); 636 break; 637 } 638 639 return 0; 640 } 641 642 static int wcd939x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 643 struct snd_kcontrol *kcontrol, 644 int event) 645 { 646 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 647 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 648 int hph_mode = wcd939x->hph_mode; 649 650 switch (event) { 651 case SND_SOC_DAPM_PRE_PMU: 652 if (wcd939x->ldoh) 653 snd_soc_component_write_field(component, WCD939X_LDOH_MODE, 654 WCD939X_MODE_LDOH_EN, true); 655 656 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 657 WCD_CLSH_STATE_HPHR, hph_mode); 658 wcd_clsh_set_hph_mode(wcd939x->clsh_info, CLS_H_HIFI); 659 660 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || hph_mode == CLS_H_ULP) 661 snd_soc_component_write_field(component, 662 WCD939X_HPH_REFBUFF_LP_CTL, 663 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS, true); 664 if (hph_mode == CLS_H_LOHIFI) 665 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 666 WCD939X_HPH_PWR_LEVEL, 0); 667 668 snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4, 669 WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd); 670 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 671 WCD939X_HPH_HPHR_REF_ENABLE, true); 672 673 if (snd_soc_component_read_field(component, WCD939X_ANA_HPH, 674 WCD939X_HPH_HPHL_REF_ENABLE)) 675 usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */ 676 677 set_bit(HPH_PA_DELAY, &wcd939x->status_mask); 678 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL1, 679 WCD939X_PDM_WD_CTL1_PDM_WD_EN, 3); 680 break; 681 case SND_SOC_DAPM_POST_PMU: 682 /* 683 * 7ms sleep is required if compander is enabled as per 684 * HW requirement. If compander is disabled, then 685 * 20ms delay is required. 686 */ 687 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) { 688 if (!wcd939x->comp2_enable) 689 usleep_range(20000, 20100); 690 else 691 usleep_range(7000, 7100); 692 693 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 694 hph_mode == CLS_H_ULP) 695 snd_soc_component_write_field(component, 696 WCD939X_HPH_REFBUFF_LP_CTL, 697 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS, 698 false); 699 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask); 700 } 701 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1, 702 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, true); 703 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 704 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 705 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES, 706 WCD939X_RX_SUPPLIES_REGULATOR_MODE, 707 true); 708 709 enable_irq(wcd939x->hphr_pdm_wd_int); 710 break; 711 case SND_SOC_DAPM_PRE_PMD: 712 disable_irq_nosync(wcd939x->hphr_pdm_wd_int); 713 /* 714 * 7ms sleep is required if compander is enabled as per 715 * HW requirement. If compander is disabled, then 716 * 20ms delay is required. 717 */ 718 if (!wcd939x->comp2_enable) 719 usleep_range(20000, 20100); 720 else 721 usleep_range(7000, 7100); 722 723 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 724 WCD939X_HPH_HPHR_ENABLE, false); 725 726 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 727 WCD_EVENT_PRE_HPHR_PA_OFF); 728 set_bit(HPH_PA_DELAY, &wcd939x->status_mask); 729 break; 730 case SND_SOC_DAPM_POST_PMD: 731 /* 732 * 7ms sleep is required if compander is enabled as per 733 * HW requirement. If compander is disabled, then 734 * 20ms delay is required. 735 */ 736 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) { 737 if (!wcd939x->comp2_enable) 738 usleep_range(20000, 20100); 739 else 740 usleep_range(7000, 7100); 741 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask); 742 } 743 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 744 WCD_EVENT_POST_HPHR_PA_OFF); 745 746 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 747 WCD939X_HPH_HPHR_REF_ENABLE, false); 748 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL1, 749 WCD939X_PDM_WD_CTL1_PDM_WD_EN, 0); 750 751 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA, 752 WCD_CLSH_STATE_HPHR, hph_mode); 753 if (wcd939x->ldoh) 754 snd_soc_component_write_field(component, WCD939X_LDOH_MODE, 755 WCD939X_MODE_LDOH_EN, false); 756 break; 757 } 758 759 return 0; 760 } 761 762 static int wcd939x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 763 struct snd_kcontrol *kcontrol, 764 int event) 765 { 766 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 767 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 768 int hph_mode = wcd939x->hph_mode; 769 770 dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__, 771 w->name, event); 772 773 switch (event) { 774 case SND_SOC_DAPM_PRE_PMU: 775 if (wcd939x->ldoh) 776 snd_soc_component_write_field(component, WCD939X_LDOH_MODE, 777 WCD939X_MODE_LDOH_EN, true); 778 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 779 WCD_CLSH_STATE_HPHL, hph_mode); 780 wcd_clsh_set_hph_mode(wcd939x->clsh_info, CLS_H_HIFI); 781 782 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || hph_mode == CLS_H_ULP) 783 snd_soc_component_write_field(component, 784 WCD939X_HPH_REFBUFF_LP_CTL, 785 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS, 786 true); 787 if (hph_mode == CLS_H_LOHIFI) 788 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 789 WCD939X_HPH_PWR_LEVEL, 0); 790 791 snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4, 792 WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd); 793 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 794 WCD939X_HPH_HPHL_REF_ENABLE, true); 795 796 if (snd_soc_component_read_field(component, WCD939X_ANA_HPH, 797 WCD939X_HPH_HPHR_REF_ENABLE)) 798 usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */ 799 800 set_bit(HPH_PA_DELAY, &wcd939x->status_mask); 801 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0, 802 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 3); 803 break; 804 case SND_SOC_DAPM_POST_PMU: 805 /* 806 * 7ms sleep is required if compander is enabled as per 807 * HW requirement. If compander is disabled, then 808 * 20ms delay is required. 809 */ 810 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) { 811 if (!wcd939x->comp1_enable) 812 usleep_range(20000, 20100); 813 else 814 usleep_range(7000, 7100); 815 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 816 hph_mode == CLS_H_ULP) 817 snd_soc_component_write_field(component, 818 WCD939X_HPH_REFBUFF_LP_CTL, 819 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS, 820 false); 821 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask); 822 } 823 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1, 824 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, true); 825 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 826 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 827 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES, 828 WCD939X_RX_SUPPLIES_REGULATOR_MODE, 829 true); 830 enable_irq(wcd939x->hphl_pdm_wd_int); 831 break; 832 case SND_SOC_DAPM_PRE_PMD: 833 disable_irq_nosync(wcd939x->hphl_pdm_wd_int); 834 /* 835 * 7ms sleep is required if compander is enabled as per 836 * HW requirement. If compander is disabled, then 837 * 20ms delay is required. 838 */ 839 if (!wcd939x->comp1_enable) 840 usleep_range(20000, 20100); 841 else 842 usleep_range(7000, 7100); 843 844 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 845 WCD939X_HPH_HPHL_ENABLE, false); 846 847 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 848 set_bit(HPH_PA_DELAY, &wcd939x->status_mask); 849 break; 850 case SND_SOC_DAPM_POST_PMD: 851 /* 852 * 7ms sleep is required if compander is enabled as per 853 * HW requirement. If compander is disabled, then 854 * 20ms delay is required. 855 */ 856 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) { 857 if (!wcd939x->comp1_enable) 858 usleep_range(21000, 21100); 859 else 860 usleep_range(7000, 7100); 861 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask); 862 } 863 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 864 WCD_EVENT_POST_HPHL_PA_OFF); 865 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 866 WCD939X_HPH_HPHL_REF_ENABLE, false); 867 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0, 868 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 0); 869 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA, 870 WCD_CLSH_STATE_HPHL, hph_mode); 871 if (wcd939x->ldoh) 872 snd_soc_component_write_field(component, WCD939X_LDOH_MODE, 873 WCD939X_MODE_LDOH_EN, false); 874 break; 875 } 876 877 return 0; 878 } 879 880 static int wcd939x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 881 struct snd_kcontrol *kcontrol, int event) 882 { 883 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 884 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 885 886 switch (event) { 887 case SND_SOC_DAPM_PRE_PMU: 888 /* Enable watchdog interrupt for HPHL */ 889 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0, 890 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 3); 891 /* For EAR, use CLASS_AB regulator mode */ 892 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES, 893 WCD939X_RX_SUPPLIES_REGULATOR_MODE, true); 894 snd_soc_component_write_field(component, WCD939X_ANA_EAR_COMPANDER_CTL, 895 WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG, true); 896 break; 897 case SND_SOC_DAPM_POST_PMU: 898 /* 6 msec delay as per HW requirement */ 899 usleep_range(6000, 6010); 900 enable_irq(wcd939x->ear_pdm_wd_int); 901 break; 902 case SND_SOC_DAPM_PRE_PMD: 903 disable_irq_nosync(wcd939x->ear_pdm_wd_int); 904 break; 905 case SND_SOC_DAPM_POST_PMD: 906 snd_soc_component_write_field(component, WCD939X_ANA_EAR_COMPANDER_CTL, 907 WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG, 908 false); 909 /* 7 msec delay as per HW requirement */ 910 usleep_range(7000, 7010); 911 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0, 912 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 0); 913 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA, 914 WCD_CLSH_STATE_EAR, CLS_AB_HIFI); 915 break; 916 } 917 918 return 0; 919 } 920 921 /* TX Controls */ 922 923 static int wcd939x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 924 struct snd_kcontrol *kcontrol, 925 int event) 926 { 927 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 928 u16 dmic_clk_reg, dmic_clk_en_reg; 929 u8 dmic_clk_en_mask; 930 u8 dmic_ctl_mask; 931 u8 dmic_clk_mask; 932 933 switch (w->shift) { 934 case 0: 935 case 1: 936 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_1_2; 937 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC1_CTL; 938 dmic_clk_en_mask = WCD939X_CDC_DMIC1_CTL_DMIC_CLK_EN; 939 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_1_2_DMIC1_RATE; 940 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC1_IN_SEL; 941 break; 942 case 2: 943 case 3: 944 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_1_2; 945 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC2_CTL; 946 dmic_clk_en_mask = WCD939X_CDC_DMIC2_CTL_DMIC_CLK_EN; 947 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_1_2_DMIC2_RATE; 948 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC3_IN_SEL; 949 break; 950 case 4: 951 case 5: 952 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_3_4; 953 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC3_CTL; 954 dmic_clk_en_mask = WCD939X_CDC_DMIC3_CTL_DMIC_CLK_EN; 955 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_3_4_DMIC3_RATE; 956 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC4_IN_SEL; 957 break; 958 case 6: 959 case 7: 960 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_3_4; 961 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC4_CTL; 962 dmic_clk_en_mask = WCD939X_CDC_DMIC4_CTL_DMIC_CLK_EN; 963 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_3_4_DMIC4_RATE; 964 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC5_IN_SEL; 965 break; 966 default: 967 dev_err(component->dev, "%s: Invalid DMIC Selection\n", __func__); 968 return -EINVAL; 969 } 970 971 switch (event) { 972 case SND_SOC_DAPM_PRE_PMU: 973 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_AMIC_CTL, 974 dmic_ctl_mask, false); 975 /* 250us sleep as per HW requirement */ 976 usleep_range(250, 260); 977 if (w->shift == 2) 978 snd_soc_component_write_field(component, 979 WCD939X_DIGITAL_CDC_DMIC2_CTL, 980 WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN, 981 true); 982 /* Setting DMIC clock rate to 2.4MHz */ 983 snd_soc_component_write_field(component, dmic_clk_reg, 984 dmic_clk_mask, 3); 985 snd_soc_component_write_field(component, dmic_clk_en_reg, 986 dmic_clk_en_mask, true); 987 /* enable clock scaling */ 988 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL, 989 WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN, true); 990 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL, 991 WCD939X_CDC_DMIC_CTL_DMIC_DIV_BAK_EN, true); 992 break; 993 case SND_SOC_DAPM_POST_PMD: 994 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_AMIC_CTL, 995 dmic_ctl_mask, 1); 996 if (w->shift == 2) 997 snd_soc_component_write_field(component, 998 WCD939X_DIGITAL_CDC_DMIC2_CTL, 999 WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN, 1000 false); 1001 snd_soc_component_write_field(component, dmic_clk_en_reg, 1002 dmic_clk_en_mask, 0); 1003 break; 1004 } 1005 return 0; 1006 } 1007 1008 static int wcd939x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 1009 struct snd_kcontrol *kcontrol, int event) 1010 { 1011 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1012 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1013 int bank; 1014 int rate; 1015 1016 bank = wcd939x_swr_get_current_bank(wcd939x->sdw_priv[AIF1_CAP]->sdev); 1017 1018 switch (event) { 1019 case SND_SOC_DAPM_PRE_PMU: 1020 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 1021 int mode = 0; 1022 1023 if (test_bit(WCD_ADC1, &wcd939x->status_mask)) 1024 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]]; 1025 if (test_bit(WCD_ADC2, &wcd939x->status_mask)) 1026 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]]; 1027 if (test_bit(WCD_ADC3, &wcd939x->status_mask)) 1028 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]]; 1029 if (test_bit(WCD_ADC4, &wcd939x->status_mask)) 1030 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]]; 1031 1032 if (mode) 1033 rate = wcd939x_get_clk_rate(ffs(mode) - 1); 1034 else 1035 rate = wcd939x_get_clk_rate(ADC_MODE_INVALID); 1036 wcd939x_set_swr_clk_rate(component, rate, bank); 1037 wcd939x_set_swr_clk_rate(component, rate, !bank); 1038 } 1039 break; 1040 case SND_SOC_DAPM_POST_PMD: 1041 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 1042 rate = wcd939x_get_clk_rate(ADC_MODE_INVALID); 1043 wcd939x_set_swr_clk_rate(component, rate, !bank); 1044 wcd939x_set_swr_clk_rate(component, rate, bank); 1045 } 1046 break; 1047 } 1048 1049 return 0; 1050 } 1051 1052 static int wcd939x_get_adc_mode(int val) 1053 { 1054 int ret = 0; 1055 1056 switch (val) { 1057 case ADC_MODE_INVALID: 1058 ret = ADC_MODE_VAL_NORMAL; 1059 break; 1060 case ADC_MODE_HIFI: 1061 ret = ADC_MODE_VAL_HIFI; 1062 break; 1063 case ADC_MODE_LO_HIF: 1064 ret = ADC_MODE_VAL_LO_HIF; 1065 break; 1066 case ADC_MODE_NORMAL: 1067 ret = ADC_MODE_VAL_NORMAL; 1068 break; 1069 case ADC_MODE_LP: 1070 ret = ADC_MODE_VAL_LP; 1071 break; 1072 case ADC_MODE_ULP1: 1073 ret = ADC_MODE_VAL_ULP1; 1074 break; 1075 case ADC_MODE_ULP2: 1076 ret = ADC_MODE_VAL_ULP2; 1077 break; 1078 default: 1079 ret = -EINVAL; 1080 break; 1081 } 1082 return ret; 1083 } 1084 1085 static int wcd939x_codec_enable_adc(struct snd_soc_dapm_widget *w, 1086 struct snd_kcontrol *kcontrol, int event) 1087 { 1088 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1089 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1090 1091 switch (event) { 1092 case SND_SOC_DAPM_PRE_PMU: 1093 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 1094 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN, true); 1095 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 1096 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN, 1097 true); 1098 set_bit(w->shift, &wcd939x->status_mask); 1099 break; 1100 case SND_SOC_DAPM_POST_PMD: 1101 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 1102 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN, 1103 false); 1104 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 1105 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN, 1106 false); 1107 clear_bit(w->shift, &wcd939x->status_mask); 1108 break; 1109 } 1110 1111 return 0; 1112 } 1113 1114 static void wcd939x_tx_channel_config(struct snd_soc_component *component, 1115 int channel, bool init) 1116 { 1117 int reg, mask; 1118 1119 switch (channel) { 1120 case 0: 1121 reg = WCD939X_ANA_TX_CH2; 1122 mask = WCD939X_TX_CH2_HPF1_INIT; 1123 break; 1124 case 1: 1125 reg = WCD939X_ANA_TX_CH2; 1126 mask = WCD939X_TX_CH2_HPF2_INIT; 1127 break; 1128 case 2: 1129 reg = WCD939X_ANA_TX_CH4; 1130 mask = WCD939X_TX_CH4_HPF3_INIT; 1131 break; 1132 case 3: 1133 reg = WCD939X_ANA_TX_CH4; 1134 mask = WCD939X_TX_CH4_HPF4_INIT; 1135 break; 1136 default: 1137 return; 1138 } 1139 1140 snd_soc_component_write_field(component, reg, mask, init); 1141 } 1142 1143 static int wcd939x_adc_enable_req(struct snd_soc_dapm_widget *w, 1144 struct snd_kcontrol *kcontrol, int event) 1145 { 1146 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1147 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1148 int mode; 1149 1150 switch (event) { 1151 case SND_SOC_DAPM_PRE_PMU: 1152 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_REQ_CTL, 1153 WCD939X_CDC_REQ_CTL_FS_RATE_4P8, true); 1154 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_REQ_CTL, 1155 WCD939X_CDC_REQ_CTL_NO_NOTCH, false); 1156 1157 wcd939x_tx_channel_config(component, w->shift, true); 1158 mode = wcd939x_get_adc_mode(wcd939x->tx_mode[w->shift]); 1159 if (mode < 0) { 1160 dev_info(component->dev, "Invalid ADC mode\n"); 1161 return -EINVAL; 1162 } 1163 1164 switch (w->shift) { 1165 case 0: 1166 snd_soc_component_write_field(component, 1167 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1168 WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE, 1169 mode); 1170 snd_soc_component_write_field(component, 1171 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1172 WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN, 1173 true); 1174 break; 1175 case 1: 1176 snd_soc_component_write_field(component, 1177 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1178 WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE, 1179 mode); 1180 snd_soc_component_write_field(component, 1181 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1182 WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN, 1183 true); 1184 break; 1185 case 2: 1186 snd_soc_component_write_field(component, 1187 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1188 WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE, 1189 mode); 1190 snd_soc_component_write_field(component, 1191 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1192 WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN, 1193 true); 1194 break; 1195 case 3: 1196 snd_soc_component_write_field(component, 1197 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1198 WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE, 1199 mode); 1200 snd_soc_component_write_field(component, 1201 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1202 WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN, 1203 true); 1204 break; 1205 default: 1206 break; 1207 } 1208 1209 wcd939x_tx_channel_config(component, w->shift, false); 1210 break; 1211 case SND_SOC_DAPM_POST_PMD: 1212 switch (w->shift) { 1213 case 0: 1214 snd_soc_component_write_field(component, 1215 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1216 WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE, 1217 false); 1218 snd_soc_component_write_field(component, 1219 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1220 WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN, 1221 false); 1222 break; 1223 case 1: 1224 snd_soc_component_write_field(component, 1225 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1226 WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE, 1227 false); 1228 snd_soc_component_write_field(component, 1229 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1230 WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN, 1231 false); 1232 break; 1233 case 2: 1234 snd_soc_component_write_field(component, 1235 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1236 WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE, 1237 false); 1238 snd_soc_component_write_field(component, 1239 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1240 WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN, 1241 false); 1242 break; 1243 case 3: 1244 snd_soc_component_write_field(component, 1245 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1246 WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE, 1247 false); 1248 snd_soc_component_write_field(component, 1249 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1250 WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN, 1251 false); 1252 break; 1253 default: 1254 break; 1255 } 1256 break; 1257 } 1258 1259 return 0; 1260 } 1261 1262 static int wcd939x_micbias_control(struct snd_soc_component *component, 1263 int micb_num, int req, bool is_dapm) 1264 { 1265 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1266 int micb_index = micb_num - 1; 1267 u16 micb_reg; 1268 1269 switch (micb_num) { 1270 case MIC_BIAS_1: 1271 micb_reg = WCD939X_ANA_MICB1; 1272 break; 1273 case MIC_BIAS_2: 1274 micb_reg = WCD939X_ANA_MICB2; 1275 break; 1276 case MIC_BIAS_3: 1277 micb_reg = WCD939X_ANA_MICB3; 1278 break; 1279 case MIC_BIAS_4: 1280 micb_reg = WCD939X_ANA_MICB4; 1281 break; 1282 default: 1283 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 1284 __func__, micb_num); 1285 return -EINVAL; 1286 } 1287 1288 switch (req) { 1289 case MICB_PULLUP_ENABLE: 1290 wcd939x->pullup_ref[micb_index]++; 1291 if (wcd939x->pullup_ref[micb_index] == 1 && 1292 wcd939x->micb_ref[micb_index] == 0) 1293 snd_soc_component_write_field(component, micb_reg, 1294 WCD939X_MICB_ENABLE, 1295 MICB_BIAS_PULL_UP); 1296 break; 1297 case MICB_PULLUP_DISABLE: 1298 if (wcd939x->pullup_ref[micb_index] > 0) 1299 wcd939x->pullup_ref[micb_index]--; 1300 if (wcd939x->pullup_ref[micb_index] == 0 && 1301 wcd939x->micb_ref[micb_index] == 0) 1302 snd_soc_component_write_field(component, micb_reg, 1303 WCD939X_MICB_ENABLE, 1304 MICB_BIAS_DISABLE); 1305 break; 1306 case MICB_ENABLE: 1307 wcd939x->micb_ref[micb_index]++; 1308 if (wcd939x->micb_ref[micb_index] == 1) { 1309 snd_soc_component_write_field(component, 1310 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1311 WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN, true); 1312 snd_soc_component_write_field(component, 1313 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1314 WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN, true); 1315 snd_soc_component_write_field(component, 1316 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1317 WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN, true); 1318 snd_soc_component_write_field(component, 1319 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1320 WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN, true); 1321 snd_soc_component_write_field(component, 1322 WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 1323 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN, 1324 true); 1325 snd_soc_component_write_field(component, 1326 WCD939X_DIGITAL_CDC_ANA_TX_CLK_CTL, 1327 WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN, 1328 true); 1329 snd_soc_component_write_field(component, 1330 WCD939X_MICB1_TEST_CTL_2, 1331 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true); 1332 snd_soc_component_write_field(component, 1333 WCD939X_MICB2_TEST_CTL_2, 1334 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true); 1335 snd_soc_component_write_field(component, 1336 WCD939X_MICB3_TEST_CTL_2, 1337 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true); 1338 snd_soc_component_write_field(component, 1339 WCD939X_MICB4_TEST_CTL_2, 1340 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true); 1341 snd_soc_component_write_field(component, micb_reg, 1342 WCD939X_MICB_ENABLE, 1343 MICB_BIAS_ENABLE); 1344 if (micb_num == MIC_BIAS_2) 1345 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 1346 WCD_EVENT_POST_MICBIAS_2_ON); 1347 } 1348 if (micb_num == MIC_BIAS_2 && is_dapm) 1349 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 1350 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 1351 break; 1352 case MICB_DISABLE: 1353 if (wcd939x->micb_ref[micb_index] > 0) 1354 wcd939x->micb_ref[micb_index]--; 1355 1356 if (wcd939x->micb_ref[micb_index] == 0 && 1357 wcd939x->pullup_ref[micb_index] > 0) 1358 snd_soc_component_write_field(component, micb_reg, 1359 WCD939X_MICB_ENABLE, 1360 MICB_BIAS_PULL_UP); 1361 else if (wcd939x->micb_ref[micb_index] == 0 && 1362 wcd939x->pullup_ref[micb_index] == 0) { 1363 if (micb_num == MIC_BIAS_2) 1364 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 1365 WCD_EVENT_PRE_MICBIAS_2_OFF); 1366 1367 snd_soc_component_write_field(component, micb_reg, 1368 WCD939X_MICB_ENABLE, 1369 MICB_BIAS_DISABLE); 1370 if (micb_num == MIC_BIAS_2) 1371 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 1372 WCD_EVENT_POST_MICBIAS_2_OFF); 1373 } 1374 if (is_dapm && micb_num == MIC_BIAS_2) 1375 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 1376 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 1377 break; 1378 } 1379 1380 return 0; 1381 } 1382 1383 static int wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1384 struct snd_kcontrol *kcontrol, 1385 int event) 1386 { 1387 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1388 int micb_num = w->shift; 1389 1390 switch (event) { 1391 case SND_SOC_DAPM_PRE_PMU: 1392 wcd939x_micbias_control(component, micb_num, MICB_ENABLE, true); 1393 break; 1394 case SND_SOC_DAPM_POST_PMU: 1395 /* 1 msec delay as per HW requirement */ 1396 usleep_range(1000, 1100); 1397 break; 1398 case SND_SOC_DAPM_POST_PMD: 1399 wcd939x_micbias_control(component, micb_num, MICB_DISABLE, true); 1400 break; 1401 } 1402 1403 return 0; 1404 } 1405 1406 static int wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1407 struct snd_kcontrol *kcontrol, 1408 int event) 1409 { 1410 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1411 int micb_num = w->shift; 1412 1413 switch (event) { 1414 case SND_SOC_DAPM_PRE_PMU: 1415 wcd939x_micbias_control(component, micb_num, 1416 MICB_PULLUP_ENABLE, true); 1417 break; 1418 case SND_SOC_DAPM_POST_PMU: 1419 /* 1 msec delay as per HW requirement */ 1420 usleep_range(1000, 1100); 1421 break; 1422 case SND_SOC_DAPM_POST_PMD: 1423 wcd939x_micbias_control(component, micb_num, 1424 MICB_PULLUP_DISABLE, true); 1425 break; 1426 } 1427 1428 return 0; 1429 } 1430 1431 static int wcd939x_tx_mode_get(struct snd_kcontrol *kcontrol, 1432 struct snd_ctl_elem_value *ucontrol) 1433 { 1434 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1435 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1436 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1437 int path = e->shift_l; 1438 1439 ucontrol->value.enumerated.item[0] = wcd939x->tx_mode[path]; 1440 1441 return 0; 1442 } 1443 1444 static int wcd939x_tx_mode_put(struct snd_kcontrol *kcontrol, 1445 struct snd_ctl_elem_value *ucontrol) 1446 { 1447 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1448 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1449 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1450 int path = e->shift_l; 1451 1452 if (wcd939x->tx_mode[path] == ucontrol->value.enumerated.item[0]) 1453 return 0; 1454 1455 wcd939x->tx_mode[path] = ucontrol->value.enumerated.item[0]; 1456 1457 return 1; 1458 } 1459 1460 /* RX Controls */ 1461 1462 static int wcd939x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 1463 struct snd_ctl_elem_value *ucontrol) 1464 { 1465 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1466 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1467 1468 ucontrol->value.integer.value[0] = wcd939x->hph_mode; 1469 1470 return 0; 1471 } 1472 1473 static int wcd939x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 1474 struct snd_ctl_elem_value *ucontrol) 1475 { 1476 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1477 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1478 u32 mode_val; 1479 1480 mode_val = ucontrol->value.enumerated.item[0]; 1481 1482 if (mode_val == wcd939x->hph_mode) 1483 return 0; 1484 1485 if (wcd939x->variant == WCD9390) { 1486 switch (mode_val) { 1487 case CLS_H_NORMAL: 1488 case CLS_H_LP: 1489 case CLS_AB: 1490 case CLS_H_LOHIFI: 1491 case CLS_H_ULP: 1492 case CLS_AB_LP: 1493 case CLS_AB_LOHIFI: 1494 wcd939x->hph_mode = mode_val; 1495 return 1; 1496 } 1497 } else { 1498 switch (mode_val) { 1499 case CLS_H_NORMAL: 1500 case CLS_H_HIFI: 1501 case CLS_H_LP: 1502 case CLS_AB: 1503 case CLS_H_LOHIFI: 1504 case CLS_H_ULP: 1505 case CLS_AB_HIFI: 1506 case CLS_AB_LP: 1507 case CLS_AB_LOHIFI: 1508 wcd939x->hph_mode = mode_val; 1509 return 1; 1510 } 1511 } 1512 1513 dev_dbg(component->dev, "%s: Invalid HPH Mode\n", __func__); 1514 return -EINVAL; 1515 } 1516 1517 static int wcd939x_get_compander(struct snd_kcontrol *kcontrol, 1518 struct snd_ctl_elem_value *ucontrol) 1519 { 1520 struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value); 1521 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1522 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1523 1524 if (mc->shift) 1525 ucontrol->value.integer.value[0] = wcd939x->comp2_enable ? 1 : 0; 1526 else 1527 ucontrol->value.integer.value[0] = wcd939x->comp1_enable ? 1 : 0; 1528 1529 return 0; 1530 } 1531 1532 static int wcd939x_set_compander(struct snd_kcontrol *kcontrol, 1533 struct snd_ctl_elem_value *ucontrol) 1534 { 1535 struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value); 1536 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1537 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1538 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[AIF1_PB]; 1539 bool value = !!ucontrol->value.integer.value[0]; 1540 int portidx = wcd->ch_info[mc->reg].port_num; 1541 1542 if (mc->shift) 1543 wcd939x->comp2_enable = value; 1544 else 1545 wcd939x->comp1_enable = value; 1546 1547 if (value) 1548 wcd939x_connect_port(wcd, portidx, mc->reg, true); 1549 else 1550 wcd939x_connect_port(wcd, portidx, mc->reg, false); 1551 1552 return 1; 1553 } 1554 1555 static int wcd939x_ldoh_get(struct snd_kcontrol *kcontrol, 1556 struct snd_ctl_elem_value *ucontrol) 1557 { 1558 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1559 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1560 1561 ucontrol->value.integer.value[0] = wcd939x->ldoh ? 1 : 0; 1562 1563 return 0; 1564 } 1565 1566 static int wcd939x_ldoh_put(struct snd_kcontrol *kcontrol, 1567 struct snd_ctl_elem_value *ucontrol) 1568 { 1569 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1570 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1571 1572 if (wcd939x->ldoh == !!ucontrol->value.integer.value[0]) 1573 return 0; 1574 1575 wcd939x->ldoh = !!ucontrol->value.integer.value[0]; 1576 1577 return 1; 1578 } 1579 1580 static const char * const tx_mode_mux_text_wcd9390[] = { 1581 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 1582 }; 1583 1584 static const struct soc_enum tx0_mode_mux_enum_wcd9390 = 1585 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9390), 1586 tx_mode_mux_text_wcd9390); 1587 1588 static const struct soc_enum tx1_mode_mux_enum_wcd9390 = 1589 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9390), 1590 tx_mode_mux_text_wcd9390); 1591 1592 static const struct soc_enum tx2_mode_mux_enum_wcd9390 = 1593 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9390), 1594 tx_mode_mux_text_wcd9390); 1595 1596 static const struct soc_enum tx3_mode_mux_enum_wcd9390 = 1597 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9390), 1598 tx_mode_mux_text_wcd9390); 1599 1600 static const char * const tx_mode_mux_text[] = { 1601 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 1602 "ADC_ULP1", "ADC_ULP2", 1603 }; 1604 1605 static const struct soc_enum tx0_mode_mux_enum = 1606 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text), 1607 tx_mode_mux_text); 1608 1609 static const struct soc_enum tx1_mode_mux_enum = 1610 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text), 1611 tx_mode_mux_text); 1612 1613 static const struct soc_enum tx2_mode_mux_enum = 1614 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text), 1615 tx_mode_mux_text); 1616 1617 static const struct soc_enum tx3_mode_mux_enum = 1618 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text), 1619 tx_mode_mux_text); 1620 1621 static const char * const rx_hph_mode_mux_text_wcd9390[] = { 1622 "CLS_H_NORMAL", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB", 1623 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP", 1624 "CLS_AB_LOHIFI", 1625 }; 1626 1627 static const struct soc_enum rx_hph_mode_mux_enum_wcd9390 = 1628 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9390), 1629 rx_hph_mode_mux_text_wcd9390); 1630 1631 static const char * const rx_hph_mode_mux_text[] = { 1632 "CLS_H_NORMAL", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI", 1633 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI", 1634 }; 1635 1636 static const struct soc_enum rx_hph_mode_mux_enum = 1637 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 1638 rx_hph_mode_mux_text); 1639 1640 static const struct snd_kcontrol_new wcd9390_snd_controls[] = { 1641 SOC_SINGLE_TLV("EAR_PA Volume", WCD939X_ANA_EAR_COMPANDER_CTL, 1642 2, 0x10, 0, ear_pa_gain), 1643 1644 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9390, 1645 wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put), 1646 1647 SOC_ENUM_EXT("TX0 MODE", tx0_mode_mux_enum_wcd9390, 1648 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1649 SOC_ENUM_EXT("TX1 MODE", tx1_mode_mux_enum_wcd9390, 1650 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1651 SOC_ENUM_EXT("TX2 MODE", tx2_mode_mux_enum_wcd9390, 1652 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1653 SOC_ENUM_EXT("TX3 MODE", tx3_mode_mux_enum_wcd9390, 1654 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1655 }; 1656 1657 static const struct snd_kcontrol_new wcd9395_snd_controls[] = { 1658 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 1659 wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put), 1660 1661 SOC_ENUM_EXT("TX0 MODE", tx0_mode_mux_enum, 1662 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1663 SOC_ENUM_EXT("TX1 MODE", tx1_mode_mux_enum, 1664 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1665 SOC_ENUM_EXT("TX2 MODE", tx2_mode_mux_enum, 1666 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1667 SOC_ENUM_EXT("TX3 MODE", tx3_mode_mux_enum, 1668 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1669 }; 1670 1671 static const struct snd_kcontrol_new adc1_switch[] = { 1672 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1673 }; 1674 1675 static const struct snd_kcontrol_new adc2_switch[] = { 1676 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1677 }; 1678 1679 static const struct snd_kcontrol_new adc3_switch[] = { 1680 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1681 }; 1682 1683 static const struct snd_kcontrol_new adc4_switch[] = { 1684 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1685 }; 1686 1687 static const struct snd_kcontrol_new dmic1_switch[] = { 1688 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1689 }; 1690 1691 static const struct snd_kcontrol_new dmic2_switch[] = { 1692 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1693 }; 1694 1695 static const struct snd_kcontrol_new dmic3_switch[] = { 1696 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1697 }; 1698 1699 static const struct snd_kcontrol_new dmic4_switch[] = { 1700 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1701 }; 1702 1703 static const struct snd_kcontrol_new dmic5_switch[] = { 1704 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1705 }; 1706 1707 static const struct snd_kcontrol_new dmic6_switch[] = { 1708 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1709 }; 1710 1711 static const struct snd_kcontrol_new dmic7_switch[] = { 1712 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1713 }; 1714 1715 static const struct snd_kcontrol_new dmic8_switch[] = { 1716 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1717 }; 1718 1719 static const struct snd_kcontrol_new ear_rdac_switch[] = { 1720 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1721 }; 1722 1723 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 1724 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1725 }; 1726 1727 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 1728 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1729 }; 1730 1731 static const char * const adc1_mux_text[] = { 1732 "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4", "CH1_AMIC5" 1733 }; 1734 1735 static const struct soc_enum adc1_enum = 1736 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH12_MUX, 0, 1737 ARRAY_SIZE(adc1_mux_text), adc1_mux_text); 1738 1739 static const struct snd_kcontrol_new tx_adc1_mux = 1740 SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum); 1741 1742 static const char * const adc2_mux_text[] = { 1743 "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4", "CH2_AMIC5" 1744 }; 1745 1746 static const struct soc_enum adc2_enum = 1747 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH12_MUX, 3, 1748 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 1749 1750 static const struct snd_kcontrol_new tx_adc2_mux = 1751 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 1752 1753 static const char * const adc3_mux_text[] = { 1754 "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC3", "CH3_AMIC4", "CH3_AMIC5" 1755 }; 1756 1757 static const struct soc_enum adc3_enum = 1758 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH34_MUX, 0, 1759 ARRAY_SIZE(adc3_mux_text), adc3_mux_text); 1760 1761 static const struct snd_kcontrol_new tx_adc3_mux = 1762 SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum); 1763 1764 static const char * const adc4_mux_text[] = { 1765 "CH4_AMIC_DISABLE", "CH4_AMIC1", "CH4_AMIC3", "CH4_AMIC4", "CH4_AMIC5" 1766 }; 1767 1768 static const struct soc_enum adc4_enum = 1769 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH34_MUX, 3, 1770 ARRAY_SIZE(adc4_mux_text), adc4_mux_text); 1771 1772 static const struct snd_kcontrol_new tx_adc4_mux = 1773 SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum); 1774 1775 static const char * const rdac3_mux_text[] = { 1776 "RX3", "RX1" 1777 }; 1778 1779 static const struct soc_enum rdac3_enum = 1780 SOC_ENUM_SINGLE(WCD939X_DIGITAL_CDC_EAR_PATH_CTL, 0, 1781 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 1782 1783 static const struct snd_kcontrol_new rx_rdac3_mux = 1784 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 1785 1786 static int wcd939x_get_swr_port(struct snd_kcontrol *kcontrol, 1787 struct snd_ctl_elem_value *ucontrol) 1788 { 1789 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1790 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1791 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(comp); 1792 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[mixer->shift]; 1793 unsigned int portidx = wcd->ch_info[mixer->reg].port_num; 1794 1795 ucontrol->value.integer.value[0] = wcd->port_enable[portidx] ? 1 : 0; 1796 1797 return 0; 1798 } 1799 1800 static const char *version_to_str(u32 version) 1801 { 1802 switch (version) { 1803 case WCD939X_VERSION_1_0: 1804 return __stringify(WCD939X_1_0); 1805 case WCD939X_VERSION_1_1: 1806 return __stringify(WCD939X_1_1); 1807 case WCD939X_VERSION_2_0: 1808 return __stringify(WCD939X_2_0); 1809 } 1810 return NULL; 1811 } 1812 1813 static int wcd939x_set_swr_port(struct snd_kcontrol *kcontrol, 1814 struct snd_ctl_elem_value *ucontrol) 1815 { 1816 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1817 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1818 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(comp); 1819 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[mixer->shift]; 1820 unsigned int portidx = wcd->ch_info[mixer->reg].port_num; 1821 1822 wcd->port_enable[portidx] = !!ucontrol->value.integer.value[0]; 1823 1824 wcd939x_connect_port(wcd, portidx, mixer->reg, wcd->port_enable[portidx]); 1825 1826 return 1; 1827 } 1828 1829 /* MBHC Related */ 1830 1831 static void wcd939x_mbhc_clk_setup(struct snd_soc_component *component, 1832 bool enable) 1833 { 1834 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_1, 1835 WCD939X_CTL_1_RCO_EN, enable); 1836 } 1837 1838 static void wcd939x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 1839 bool enable) 1840 { 1841 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT, 1842 WCD939X_MBHC_ELECT_BIAS_EN, enable); 1843 } 1844 1845 static void wcd939x_mbhc_program_btn_thr(struct snd_soc_component *component, 1846 int *btn_low, int *btn_high, 1847 int num_btn, bool is_micbias) 1848 { 1849 int i, vth; 1850 1851 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 1852 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 1853 __func__, num_btn); 1854 return; 1855 } 1856 1857 for (i = 0; i < num_btn; i++) { 1858 vth = (btn_high[i] * 2) / 25; 1859 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_BTN0 + i, 1860 WCD939X_MBHC_BTN0_VTH, vth); 1861 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n", 1862 __func__, i, btn_high[i], vth); 1863 } 1864 } 1865 1866 static bool wcd939x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 1867 { 1868 if (micb_num == MIC_BIAS_2) { 1869 u8 val; 1870 1871 val = FIELD_GET(WCD939X_MICB_ENABLE, 1872 snd_soc_component_read(component, WCD939X_ANA_MICB2)); 1873 if (val == MICB_BIAS_ENABLE) 1874 return true; 1875 } 1876 1877 return false; 1878 } 1879 1880 static void wcd939x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 1881 int pull_up_cur) 1882 { 1883 /* Default pull up current to 2uA */ 1884 if (pull_up_cur > HS_PULLUP_I_OFF || 1885 pull_up_cur < HS_PULLUP_I_3P0_UA || 1886 pull_up_cur == HS_PULLUP_I_DEFAULT) 1887 pull_up_cur = HS_PULLUP_I_2P0_UA; 1888 1889 dev_dbg(component->dev, "%s: HS pull up current:%d\n", 1890 __func__, pull_up_cur); 1891 1892 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_INT_MECH_DET_CURRENT, 1893 WCD939X_MECH_DET_CURRENT_HSDET_PULLUP_CTL, pull_up_cur); 1894 } 1895 1896 static int wcd939x_mbhc_request_micbias(struct snd_soc_component *component, 1897 int micb_num, int req) 1898 { 1899 return wcd939x_micbias_control(component, micb_num, req, false); 1900 } 1901 1902 static void wcd939x_mbhc_micb_ramp_control(struct snd_soc_component *component, 1903 bool enable) 1904 { 1905 if (enable) { 1906 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP, 1907 WCD939X_MICB2_RAMP_SHIFT_CTL, 3); 1908 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP, 1909 WCD939X_MICB2_RAMP_RAMP_ENABLE, true); 1910 } else { 1911 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP, 1912 WCD939X_MICB2_RAMP_RAMP_ENABLE, false); 1913 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP, 1914 WCD939X_MICB2_RAMP_SHIFT_CTL, 0); 1915 } 1916 } 1917 1918 static int wcd939x_get_micb_vout_ctl_val(u32 micb_mv) 1919 { 1920 /* min micbias voltage is 1V and maximum is 2.85V */ 1921 if (micb_mv < 1000 || micb_mv > 2850) { 1922 pr_err("%s: unsupported micbias voltage\n", __func__); 1923 return -EINVAL; 1924 } 1925 1926 return (micb_mv - 1000) / 50; 1927 } 1928 1929 static int wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 1930 int req_volt, int micb_num) 1931 { 1932 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1933 unsigned int micb_reg, cur_vout_ctl, micb_en; 1934 int req_vout_ctl; 1935 int ret = 0; 1936 1937 switch (micb_num) { 1938 case MIC_BIAS_1: 1939 micb_reg = WCD939X_ANA_MICB1; 1940 break; 1941 case MIC_BIAS_2: 1942 micb_reg = WCD939X_ANA_MICB2; 1943 break; 1944 case MIC_BIAS_3: 1945 micb_reg = WCD939X_ANA_MICB3; 1946 break; 1947 case MIC_BIAS_4: 1948 micb_reg = WCD939X_ANA_MICB4; 1949 break; 1950 default: 1951 return -EINVAL; 1952 } 1953 mutex_lock(&wcd939x->micb_lock); 1954 1955 /* 1956 * If requested micbias voltage is same as current micbias 1957 * voltage, then just return. Otherwise, adjust voltage as 1958 * per requested value. If micbias is already enabled, then 1959 * to avoid slow micbias ramp-up or down enable pull-up 1960 * momentarily, change the micbias value and then re-enable 1961 * micbias. 1962 */ 1963 micb_en = snd_soc_component_read_field(component, micb_reg, 1964 WCD939X_MICB_ENABLE); 1965 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 1966 WCD939X_MICB_VOUT_CTL); 1967 1968 req_vout_ctl = wcd939x_get_micb_vout_ctl_val(req_volt); 1969 if (req_vout_ctl < 0) { 1970 ret = req_vout_ctl; 1971 goto exit; 1972 } 1973 1974 if (cur_vout_ctl == req_vout_ctl) { 1975 ret = 0; 1976 goto exit; 1977 } 1978 1979 dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n", 1980 __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl), 1981 req_volt, micb_en); 1982 1983 if (micb_en == MICB_BIAS_ENABLE) 1984 snd_soc_component_write_field(component, micb_reg, 1985 WCD939X_MICB_ENABLE, 1986 MICB_BIAS_PULL_DOWN); 1987 1988 snd_soc_component_write_field(component, micb_reg, 1989 WCD939X_MICB_VOUT_CTL, req_vout_ctl); 1990 1991 if (micb_en == MICB_BIAS_ENABLE) { 1992 snd_soc_component_write_field(component, micb_reg, 1993 WCD939X_MICB_ENABLE, 1994 MICB_BIAS_ENABLE); 1995 /* 1996 * Add 2ms delay as per HW requirement after enabling 1997 * micbias 1998 */ 1999 usleep_range(2000, 2100); 2000 } 2001 2002 exit: 2003 mutex_unlock(&wcd939x->micb_lock); 2004 return ret; 2005 } 2006 2007 static int wcd939x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 2008 int micb_num, bool req_en) 2009 { 2010 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2011 int micb_mv; 2012 2013 if (micb_num != MIC_BIAS_2) 2014 return -EINVAL; 2015 /* 2016 * If device tree micbias level is already above the minimum 2017 * voltage needed to detect threshold microphone, then do 2018 * not change the micbias, just return. 2019 */ 2020 if (wcd939x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 2021 return 0; 2022 2023 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd939x->micb2_mv; 2024 2025 return wcd939x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 2026 } 2027 2028 /* Selected by WCD939X_MBHC_GET_C1() */ 2029 static const s16 wcd939x_wcd_mbhc_d1_a[4] = { 2030 0, 30, 30, 6 2031 }; 2032 2033 /* Selected by zdet_param.noff */ 2034 static const int wcd939x_mbhc_mincode_param[] = { 2035 3277, 1639, 820, 410, 205, 103, 52, 26 2036 }; 2037 2038 static const struct zdet_param wcd939x_mbhc_zdet_param = { 2039 .ldo_ctl = 4, 2040 .noff = 0, 2041 .nshift = 6, 2042 .btn5 = 0x18, 2043 .btn6 = 0x60, 2044 .btn7 = 0x78, 2045 }; 2046 2047 static void wcd939x_mbhc_get_result_params(struct snd_soc_component *component, 2048 int32_t *zdet) 2049 { 2050 const struct zdet_param *zdet_param = &wcd939x_mbhc_zdet_param; 2051 s32 x1, d1, denom; 2052 int val; 2053 s16 c1; 2054 int i; 2055 2056 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET, 2057 WCD939X_MBHC_ZDET_ZDET_CHG_EN, true); 2058 for (i = 0; i < WCD939X_ZDET_NUM_MEASUREMENTS; i++) { 2059 val = snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_2, 2060 WCD939X_MBHC_RESULT_2_Z_RESULT_MSB); 2061 if (val & BIT(7)) 2062 break; 2063 } 2064 val = val << 8; 2065 val |= snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_1, 2066 WCD939X_MBHC_RESULT_1_Z_RESULT_LSB); 2067 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET, 2068 WCD939X_MBHC_ZDET_ZDET_CHG_EN, false); 2069 x1 = WCD939X_MBHC_GET_X1(val); 2070 c1 = WCD939X_MBHC_GET_C1(val); 2071 2072 /* If ramp is not complete, give additional 5ms */ 2073 if (c1 < 2 && x1) 2074 mdelay(5); 2075 2076 if (!c1 || !x1) { 2077 dev_dbg(component->dev, 2078 "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n", 2079 __func__, c1, x1); 2080 goto ramp_down; 2081 } 2082 2083 d1 = wcd939x_wcd_mbhc_d1_a[c1]; 2084 denom = (x1 * d1) - (1 << (14 - zdet_param->noff)); 2085 if (denom > 0) 2086 *zdet = (WCD939X_ANA_MBHC_ZDET_CONST * 1000) / denom; 2087 else if (x1 < wcd939x_mbhc_mincode_param[zdet_param->noff]) 2088 *zdet = WCD939X_ZDET_FLOATING_IMPEDANCE; 2089 2090 dev_dbg(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n", 2091 __func__, d1, c1, x1, *zdet); 2092 ramp_down: 2093 i = 0; 2094 while (x1) { 2095 val = snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_1, 2096 WCD939X_MBHC_RESULT_1_Z_RESULT_LSB) << 8; 2097 val |= snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_2, 2098 WCD939X_MBHC_RESULT_2_Z_RESULT_MSB); 2099 x1 = WCD939X_MBHC_GET_X1(val); 2100 i++; 2101 if (i == WCD939X_ZDET_NUM_MEASUREMENTS) 2102 break; 2103 } 2104 } 2105 2106 static void wcd939x_mbhc_zdet_ramp(struct snd_soc_component *component, 2107 s32 *zl, int32_t *zr) 2108 { 2109 const struct zdet_param *zdet_param = &wcd939x_mbhc_zdet_param; 2110 s32 zdet = 0; 2111 2112 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL, 2113 WCD939X_ZDET_ANA_CTL_MAXV_CTL, zdet_param->ldo_ctl); 2114 snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN5, WCD939X_MBHC_BTN5_VTH, 2115 zdet_param->btn5); 2116 snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN6, WCD939X_MBHC_BTN6_VTH, 2117 zdet_param->btn6); 2118 snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN7, WCD939X_MBHC_BTN7_VTH, 2119 zdet_param->btn7); 2120 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL, 2121 WCD939X_ZDET_ANA_CTL_RANGE_CTL, zdet_param->noff); 2122 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_RAMP_CTL, 2123 WCD939X_ZDET_RAMP_CTL_TIME_CTL, zdet_param->nshift); 2124 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_RAMP_CTL, 2125 WCD939X_ZDET_RAMP_CTL_ACC1_MIN_CTL, 6); /*acc1_min_63 */ 2126 2127 if (!zl) 2128 goto z_right; 2129 2130 /* Start impedance measurement for HPH_L */ 2131 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET, 2132 WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN, true); 2133 dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n", 2134 __func__, zdet_param->noff); 2135 wcd939x_mbhc_get_result_params(component, &zdet); 2136 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET, 2137 WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN, false); 2138 2139 *zl = zdet; 2140 2141 z_right: 2142 if (!zr) 2143 return; 2144 2145 /* Start impedance measurement for HPH_R */ 2146 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET, 2147 WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN, true); 2148 dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n", 2149 __func__, zdet_param->noff); 2150 wcd939x_mbhc_get_result_params(component, &zdet); 2151 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET, 2152 WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN, false); 2153 2154 *zr = zdet; 2155 } 2156 2157 static void wcd939x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2158 s32 *z_val, int flag_l_r) 2159 { 2160 int q1_cal; 2161 s16 q1; 2162 2163 q1 = snd_soc_component_read(component, WCD939X_DIGITAL_EFUSE_REG_21 + flag_l_r); 2164 if (q1 & BIT(7)) 2165 q1_cal = (10000 - ((q1 & GENMASK(6, 0)) * 10)); 2166 else 2167 q1_cal = (10000 + (q1 * 10)); 2168 2169 if (q1_cal > 0) 2170 *z_val = ((*z_val) * 10000) / q1_cal; 2171 } 2172 2173 static void wcd939x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 2174 u32 *zl, uint32_t *zr) 2175 { 2176 struct wcd939x_priv *wcd939x = dev_get_drvdata(component->dev); 2177 unsigned int reg0, reg1, reg2, reg3, reg4; 2178 int z_mono, z_diff1, z_diff2; 2179 bool is_fsm_disable = false; 2180 s32 z1l, z1r, z1ls; 2181 2182 reg0 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN5); 2183 reg1 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN6); 2184 reg2 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN7); 2185 reg3 = snd_soc_component_read(component, WCD939X_MBHC_CTL_CLK); 2186 reg4 = snd_soc_component_read(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL); 2187 2188 if (snd_soc_component_read_field(component, WCD939X_ANA_MBHC_ELECT, 2189 WCD939X_MBHC_ELECT_FSM_EN)) { 2190 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT, 2191 WCD939X_MBHC_ELECT_FSM_EN, false); 2192 is_fsm_disable = true; 2193 } 2194 2195 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 2196 if (wcd939x->mbhc_cfg.hphl_swh) 2197 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2198 WCD939X_MBHC_MECH_L_DET_EN, false); 2199 2200 /* Turn off 100k pull down on HPHL */ 2201 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2202 WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND, 2203 false); 2204 2205 /* 2206 * Disable surge protection before impedance detection. 2207 * This is done to give correct value for high impedance. 2208 */ 2209 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN, 2210 WCD939X_EN_EN_SURGE_PROTECTION_HPHR, false); 2211 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN, 2212 WCD939X_EN_EN_SURGE_PROTECTION_HPHL, false); 2213 2214 /* 1ms delay needed after disable surge protection */ 2215 usleep_range(1000, 1010); 2216 2217 /* First get impedance on Left */ 2218 wcd939x_mbhc_zdet_ramp(component, &z1l, NULL); 2219 if (z1l == WCD939X_ZDET_FLOATING_IMPEDANCE || z1l > WCD939X_ZDET_VAL_100K) { 2220 *zl = WCD939X_ZDET_FLOATING_IMPEDANCE; 2221 } else { 2222 *zl = z1l / 1000; 2223 wcd939x_wcd_mbhc_qfuse_cal(component, zl, 0); 2224 } 2225 dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 2226 __func__, *zl); 2227 2228 /* Start of right impedance ramp and calculation */ 2229 wcd939x_mbhc_zdet_ramp(component, NULL, &z1r); 2230 if (z1r == WCD939X_ZDET_FLOATING_IMPEDANCE || z1r > WCD939X_ZDET_VAL_100K) { 2231 *zr = WCD939X_ZDET_FLOATING_IMPEDANCE; 2232 } else { 2233 *zr = z1r / 1000; 2234 wcd939x_wcd_mbhc_qfuse_cal(component, zr, 1); 2235 } 2236 dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 2237 __func__, *zr); 2238 2239 /* Mono/stereo detection */ 2240 if (*zl == WCD939X_ZDET_FLOATING_IMPEDANCE && 2241 *zr == WCD939X_ZDET_FLOATING_IMPEDANCE) { 2242 dev_dbg(component->dev, 2243 "%s: plug type is invalid or extension cable\n", 2244 __func__); 2245 goto zdet_complete; 2246 } 2247 2248 if (*zl == WCD939X_ZDET_FLOATING_IMPEDANCE || 2249 *zr == WCD939X_ZDET_FLOATING_IMPEDANCE || 2250 (*zl < WCD_MONO_HS_MIN_THR && *zr > WCD_MONO_HS_MIN_THR) || 2251 (*zl > WCD_MONO_HS_MIN_THR && *zr < WCD_MONO_HS_MIN_THR)) { 2252 dev_dbg(component->dev, 2253 "%s: Mono plug type with one ch floating or shorted to GND\n", 2254 __func__); 2255 wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_MONO); 2256 goto zdet_complete; 2257 } 2258 2259 snd_soc_component_write_field(component, WCD939X_HPH_R_ATEST, 2260 WCD939X_R_ATEST_HPH_GND_OVR, true); 2261 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2, 2262 WCD939X_PA_CTL2_HPHPA_GND_R, true); 2263 wcd939x_mbhc_zdet_ramp(component, &z1ls, NULL); 2264 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2, 2265 WCD939X_PA_CTL2_HPHPA_GND_R, false); 2266 snd_soc_component_write_field(component, WCD939X_HPH_R_ATEST, 2267 WCD939X_R_ATEST_HPH_GND_OVR, false); 2268 2269 z1ls /= 1000; 2270 wcd939x_wcd_mbhc_qfuse_cal(component, &z1ls, 0); 2271 2272 /* Parallel of left Z and 9 ohm pull down resistor */ 2273 z_mono = (*zl * 9) / (*zl + 9); 2274 z_diff1 = z1ls > z_mono ? z1ls - z_mono : z_mono - z1ls; 2275 z_diff2 = *zl > z1ls ? *zl - z1ls : z1ls - *zl; 2276 if ((z_diff1 * (*zl + z1ls)) > (z_diff2 * (z1ls + z_mono))) { 2277 dev_dbg(component->dev, "%s: stereo plug type detected\n", 2278 __func__); 2279 wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 2280 } else { 2281 dev_dbg(component->dev, "%s: MONO plug type detected\n", 2282 __func__); 2283 wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_MONO); 2284 } 2285 2286 /* Enable surge protection again after impedance detection */ 2287 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN, 2288 WCD939X_EN_EN_SURGE_PROTECTION_HPHR, true); 2289 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN, 2290 WCD939X_EN_EN_SURGE_PROTECTION_HPHL, true); 2291 2292 zdet_complete: 2293 snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN5, reg0); 2294 snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN6, reg1); 2295 snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN7, reg2); 2296 2297 /* Turn on 100k pull down on HPHL */ 2298 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2299 WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND, true); 2300 2301 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 2302 if (wcd939x->mbhc_cfg.hphl_swh) 2303 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2304 WCD939X_MBHC_MECH_L_DET_EN, true); 2305 2306 snd_soc_component_write(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL, reg4); 2307 snd_soc_component_write(component, WCD939X_MBHC_CTL_CLK, reg3); 2308 2309 if (is_fsm_disable) 2310 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT, 2311 WCD939X_MBHC_ELECT_FSM_EN, true); 2312 } 2313 2314 static void wcd939x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 2315 bool enable) 2316 { 2317 if (enable) { 2318 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2319 WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN, 2320 true); 2321 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2322 WCD939X_MBHC_MECH_GND_DET_EN, true); 2323 } else { 2324 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2325 WCD939X_MBHC_MECH_GND_DET_EN, false); 2326 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2327 WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN, 2328 false); 2329 } 2330 } 2331 2332 static void wcd939x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 2333 bool enable) 2334 { 2335 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2, 2336 WCD939X_PA_CTL2_HPHPA_GND_R, enable); 2337 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2, 2338 WCD939X_PA_CTL2_HPHPA_GND_L, enable); 2339 } 2340 2341 static void wcd939x_mbhc_moisture_config(struct snd_soc_component *component) 2342 { 2343 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2344 2345 if (wcd939x->mbhc_cfg.moist_rref == R_OFF || wcd939x->typec_analog_mux) { 2346 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2, 2347 WCD939X_CTL_2_M_RTH_CTL, R_OFF); 2348 return; 2349 } 2350 2351 /* Do not enable moisture detection if jack type is NC */ 2352 if (!wcd939x->mbhc_cfg.hphl_swh) { 2353 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 2354 __func__); 2355 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2, 2356 WCD939X_CTL_2_M_RTH_CTL, R_OFF); 2357 return; 2358 } 2359 2360 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2, 2361 WCD939X_CTL_2_M_RTH_CTL, wcd939x->mbhc_cfg.moist_rref); 2362 } 2363 2364 static void wcd939x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 2365 { 2366 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2367 2368 if (enable) 2369 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2, 2370 WCD939X_CTL_2_M_RTH_CTL, 2371 wcd939x->mbhc_cfg.moist_rref); 2372 else 2373 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2, 2374 WCD939X_CTL_2_M_RTH_CTL, R_OFF); 2375 } 2376 2377 static bool wcd939x_mbhc_get_moisture_status(struct snd_soc_component *component) 2378 { 2379 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2380 bool ret = false; 2381 2382 if (wcd939x->mbhc_cfg.moist_rref == R_OFF || wcd939x->typec_analog_mux) { 2383 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2, 2384 WCD939X_CTL_2_M_RTH_CTL, R_OFF); 2385 goto done; 2386 } 2387 2388 /* Do not enable moisture detection if jack type is NC */ 2389 if (!wcd939x->mbhc_cfg.hphl_swh) { 2390 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 2391 __func__); 2392 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2, 2393 WCD939X_CTL_2_M_RTH_CTL, R_OFF); 2394 goto done; 2395 } 2396 2397 /* 2398 * If moisture_en is already enabled, then skip to plug type 2399 * detection. 2400 */ 2401 if (snd_soc_component_read_field(component, WCD939X_MBHC_NEW_CTL_2, 2402 WCD939X_CTL_2_M_RTH_CTL)) 2403 goto done; 2404 2405 wcd939x_mbhc_moisture_detect_en(component, true); 2406 2407 /* Read moisture comparator status, invert of status bit */ 2408 ret = !snd_soc_component_read_field(component, WCD939X_MBHC_NEW_FSM_STATUS, 2409 WCD939X_FSM_STATUS_HS_M_COMP_STATUS); 2410 done: 2411 return ret; 2412 } 2413 2414 static void wcd939x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 2415 bool enable) 2416 { 2417 snd_soc_component_write_field(component, 2418 WCD939X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 2419 WCD939X_MOISTURE_DET_POLLING_CTRL_MOIST_EN_POLLING, 2420 enable); 2421 } 2422 2423 static const struct wcd_mbhc_cb mbhc_cb = { 2424 .clk_setup = wcd939x_mbhc_clk_setup, 2425 .mbhc_bias = wcd939x_mbhc_mbhc_bias_control, 2426 .set_btn_thr = wcd939x_mbhc_program_btn_thr, 2427 .micbias_enable_status = wcd939x_mbhc_micb_en_status, 2428 .hph_pull_up_control_v2 = wcd939x_mbhc_hph_l_pull_up_control, 2429 .mbhc_micbias_control = wcd939x_mbhc_request_micbias, 2430 .mbhc_micb_ramp_control = wcd939x_mbhc_micb_ramp_control, 2431 .mbhc_micb_ctrl_thr_mic = wcd939x_mbhc_micb_ctrl_threshold_mic, 2432 .compute_impedance = wcd939x_wcd_mbhc_calc_impedance, 2433 .mbhc_gnd_det_ctrl = wcd939x_mbhc_gnd_det_ctrl, 2434 .hph_pull_down_ctrl = wcd939x_mbhc_hph_pull_down_ctrl, 2435 .mbhc_moisture_config = wcd939x_mbhc_moisture_config, 2436 .mbhc_get_moisture_status = wcd939x_mbhc_get_moisture_status, 2437 .mbhc_moisture_polling_ctrl = wcd939x_mbhc_moisture_polling_ctrl, 2438 .mbhc_moisture_detect_en = wcd939x_mbhc_moisture_detect_en, 2439 }; 2440 2441 static int wcd939x_get_hph_type(struct snd_kcontrol *kcontrol, 2442 struct snd_ctl_elem_value *ucontrol) 2443 { 2444 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2445 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2446 2447 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd939x->wcd_mbhc); 2448 2449 return 0; 2450 } 2451 2452 static int wcd939x_hph_impedance_get(struct snd_kcontrol *kcontrol, 2453 struct snd_ctl_elem_value *ucontrol) 2454 { 2455 struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value); 2456 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2457 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2458 bool hphr = mc->shift; 2459 u32 zl, zr; 2460 2461 wcd_mbhc_get_impedance(wcd939x->wcd_mbhc, &zl, &zr); 2462 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 2463 ucontrol->value.integer.value[0] = hphr ? zr : zl; 2464 2465 return 0; 2466 } 2467 2468 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 2469 SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0, 2470 wcd939x_get_hph_type, NULL), 2471 }; 2472 2473 static const struct snd_kcontrol_new impedance_detect_controls[] = { 2474 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0, 2475 wcd939x_hph_impedance_get, NULL), 2476 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0, 2477 wcd939x_hph_impedance_get, NULL), 2478 }; 2479 2480 static int wcd939x_mbhc_init(struct snd_soc_component *component) 2481 { 2482 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2483 struct wcd_mbhc_intr *intr_ids = &wcd939x->intr_ids; 2484 2485 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd939x->irq_chip, 2486 WCD939X_IRQ_MBHC_SW_DET); 2487 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd939x->irq_chip, 2488 WCD939X_IRQ_MBHC_BUTTON_PRESS_DET); 2489 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd939x->irq_chip, 2490 WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET); 2491 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd939x->irq_chip, 2492 WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2493 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd939x->irq_chip, 2494 WCD939X_IRQ_MBHC_ELECT_INS_REM_DET); 2495 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd939x->irq_chip, 2496 WCD939X_IRQ_HPHL_OCP_INT); 2497 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd939x->irq_chip, 2498 WCD939X_IRQ_HPHR_OCP_INT); 2499 2500 wcd939x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2501 if (IS_ERR(wcd939x->wcd_mbhc)) 2502 return PTR_ERR(wcd939x->wcd_mbhc); 2503 2504 snd_soc_add_component_controls(component, impedance_detect_controls, 2505 ARRAY_SIZE(impedance_detect_controls)); 2506 snd_soc_add_component_controls(component, hph_type_detect_controls, 2507 ARRAY_SIZE(hph_type_detect_controls)); 2508 2509 return 0; 2510 } 2511 2512 static void wcd939x_mbhc_deinit(struct snd_soc_component *component) 2513 { 2514 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2515 2516 wcd_mbhc_deinit(wcd939x->wcd_mbhc); 2517 } 2518 2519 /* END MBHC */ 2520 2521 static const struct snd_kcontrol_new wcd939x_snd_controls[] = { 2522 /* RX Path */ 2523 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD939X_COMP_L, 0, 1, 0, 2524 wcd939x_get_compander, wcd939x_set_compander), 2525 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD939X_COMP_R, 1, 1, 0, 2526 wcd939x_get_compander, wcd939x_set_compander), 2527 SOC_SINGLE_EXT("HPHL Switch", WCD939X_HPH_L, 0, 1, 0, 2528 wcd939x_get_swr_port, wcd939x_set_swr_port), 2529 SOC_SINGLE_EXT("HPHR Switch", WCD939X_HPH_R, 0, 1, 0, 2530 wcd939x_get_swr_port, wcd939x_set_swr_port), 2531 SOC_SINGLE_EXT("CLSH Switch", WCD939X_CLSH, 0, 1, 0, 2532 wcd939x_get_swr_port, wcd939x_set_swr_port), 2533 SOC_SINGLE_EXT("LO Switch", WCD939X_LO, 0, 1, 0, 2534 wcd939x_get_swr_port, wcd939x_set_swr_port), 2535 SOC_SINGLE_EXT("DSD_L Switch", WCD939X_DSD_L, 0, 1, 0, 2536 wcd939x_get_swr_port, wcd939x_set_swr_port), 2537 SOC_SINGLE_EXT("DSD_R Switch", WCD939X_DSD_R, 0, 1, 0, 2538 wcd939x_get_swr_port, wcd939x_set_swr_port), 2539 SOC_SINGLE_TLV("HPHL Volume", WCD939X_HPH_L_EN, 0, 20, 1, line_gain), 2540 SOC_SINGLE_TLV("HPHR Volume", WCD939X_HPH_R_EN, 0, 20, 1, line_gain), 2541 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0, 2542 wcd939x_ldoh_get, wcd939x_ldoh_put), 2543 2544 /* TX Path */ 2545 SOC_SINGLE_EXT("ADC1 Switch", WCD939X_ADC1, 1, 1, 0, 2546 wcd939x_get_swr_port, wcd939x_set_swr_port), 2547 SOC_SINGLE_EXT("ADC2 Switch", WCD939X_ADC2, 1, 1, 0, 2548 wcd939x_get_swr_port, wcd939x_set_swr_port), 2549 SOC_SINGLE_EXT("ADC3 Switch", WCD939X_ADC3, 1, 1, 0, 2550 wcd939x_get_swr_port, wcd939x_set_swr_port), 2551 SOC_SINGLE_EXT("ADC4 Switch", WCD939X_ADC4, 1, 1, 0, 2552 wcd939x_get_swr_port, wcd939x_set_swr_port), 2553 SOC_SINGLE_EXT("DMIC0 Switch", WCD939X_DMIC0, 1, 1, 0, 2554 wcd939x_get_swr_port, wcd939x_set_swr_port), 2555 SOC_SINGLE_EXT("DMIC1 Switch", WCD939X_DMIC1, 1, 1, 0, 2556 wcd939x_get_swr_port, wcd939x_set_swr_port), 2557 SOC_SINGLE_EXT("MBHC Switch", WCD939X_MBHC, 1, 1, 0, 2558 wcd939x_get_swr_port, wcd939x_set_swr_port), 2559 SOC_SINGLE_EXT("DMIC2 Switch", WCD939X_DMIC2, 1, 1, 0, 2560 wcd939x_get_swr_port, wcd939x_set_swr_port), 2561 SOC_SINGLE_EXT("DMIC3 Switch", WCD939X_DMIC3, 1, 1, 0, 2562 wcd939x_get_swr_port, wcd939x_set_swr_port), 2563 SOC_SINGLE_EXT("DMIC4 Switch", WCD939X_DMIC4, 1, 1, 0, 2564 wcd939x_get_swr_port, wcd939x_set_swr_port), 2565 SOC_SINGLE_EXT("DMIC5 Switch", WCD939X_DMIC5, 1, 1, 0, 2566 wcd939x_get_swr_port, wcd939x_set_swr_port), 2567 SOC_SINGLE_EXT("DMIC6 Switch", WCD939X_DMIC6, 1, 1, 0, 2568 wcd939x_get_swr_port, wcd939x_set_swr_port), 2569 SOC_SINGLE_EXT("DMIC7 Switch", WCD939X_DMIC7, 1, 1, 0, 2570 wcd939x_get_swr_port, wcd939x_set_swr_port), 2571 SOC_SINGLE_TLV("ADC1 Volume", WCD939X_ANA_TX_CH1, 0, 20, 0, 2572 analog_gain), 2573 SOC_SINGLE_TLV("ADC2 Volume", WCD939X_ANA_TX_CH2, 0, 20, 0, 2574 analog_gain), 2575 SOC_SINGLE_TLV("ADC3 Volume", WCD939X_ANA_TX_CH3, 0, 20, 0, 2576 analog_gain), 2577 SOC_SINGLE_TLV("ADC4 Volume", WCD939X_ANA_TX_CH4, 0, 20, 0, 2578 analog_gain), 2579 }; 2580 2581 static const struct snd_soc_dapm_widget wcd939x_dapm_widgets[] = { 2582 /*input widgets*/ 2583 SND_SOC_DAPM_INPUT("AMIC1"), 2584 SND_SOC_DAPM_INPUT("AMIC2"), 2585 SND_SOC_DAPM_INPUT("AMIC3"), 2586 SND_SOC_DAPM_INPUT("AMIC4"), 2587 SND_SOC_DAPM_INPUT("AMIC5"), 2588 2589 SND_SOC_DAPM_MIC("Analog Mic1", NULL), 2590 SND_SOC_DAPM_MIC("Analog Mic2", NULL), 2591 SND_SOC_DAPM_MIC("Analog Mic3", NULL), 2592 SND_SOC_DAPM_MIC("Analog Mic4", NULL), 2593 SND_SOC_DAPM_MIC("Analog Mic5", NULL), 2594 2595 /* TX widgets */ 2596 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 2597 wcd939x_codec_enable_adc, 2598 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2599 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 2600 wcd939x_codec_enable_adc, 2601 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2602 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 2603 wcd939x_codec_enable_adc, 2604 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2605 SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0, 2606 wcd939x_codec_enable_adc, 2607 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2608 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 2609 wcd939x_codec_enable_dmic, 2610 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2611 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 2612 wcd939x_codec_enable_dmic, 2613 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2614 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 2615 wcd939x_codec_enable_dmic, 2616 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2617 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 2618 wcd939x_codec_enable_dmic, 2619 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2620 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 2621 wcd939x_codec_enable_dmic, 2622 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2623 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 2624 wcd939x_codec_enable_dmic, 2625 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2626 SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0, 2627 wcd939x_codec_enable_dmic, 2628 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2629 SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0, 2630 wcd939x_codec_enable_dmic, 2631 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2632 2633 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, NULL, 0, 2634 wcd939x_adc_enable_req, 2635 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2636 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0, NULL, 0, 2637 wcd939x_adc_enable_req, 2638 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2639 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0, NULL, 0, 2640 wcd939x_adc_enable_req, 2641 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2642 SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0, 2643 wcd939x_adc_enable_req, 2644 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2645 2646 SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0, &tx_adc1_mux), 2647 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 2648 SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux), 2649 SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux), 2650 2651 /* tx mixers */ 2652 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, 2653 adc1_switch, ARRAY_SIZE(adc1_switch), wcd939x_tx_swr_ctrl, 2654 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2655 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, 2656 adc2_switch, ARRAY_SIZE(adc2_switch), wcd939x_tx_swr_ctrl, 2657 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2658 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, 2659 adc3_switch, ARRAY_SIZE(adc3_switch), wcd939x_tx_swr_ctrl, 2660 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2661 SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, 2662 adc4_switch, ARRAY_SIZE(adc4_switch), wcd939x_tx_swr_ctrl, 2663 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2664 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, 2665 dmic1_switch, ARRAY_SIZE(dmic1_switch), wcd939x_tx_swr_ctrl, 2666 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2667 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, 2668 dmic2_switch, ARRAY_SIZE(dmic2_switch), wcd939x_tx_swr_ctrl, 2669 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2670 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, 2671 dmic3_switch, ARRAY_SIZE(dmic3_switch), wcd939x_tx_swr_ctrl, 2672 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2673 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, 2674 dmic4_switch, ARRAY_SIZE(dmic4_switch), wcd939x_tx_swr_ctrl, 2675 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2676 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, 2677 dmic5_switch, ARRAY_SIZE(dmic5_switch), wcd939x_tx_swr_ctrl, 2678 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2679 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, 2680 dmic6_switch, ARRAY_SIZE(dmic6_switch), wcd939x_tx_swr_ctrl, 2681 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2682 SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, 2683 dmic7_switch, ARRAY_SIZE(dmic7_switch), wcd939x_tx_swr_ctrl, 2684 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2685 SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, 2686 dmic8_switch, ARRAY_SIZE(dmic8_switch), wcd939x_tx_swr_ctrl, 2687 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2688 2689 /* micbias widgets */ 2690 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2691 wcd939x_codec_enable_micbias, 2692 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2693 SND_SOC_DAPM_POST_PMD), 2694 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2695 wcd939x_codec_enable_micbias, 2696 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2697 SND_SOC_DAPM_POST_PMD), 2698 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2699 wcd939x_codec_enable_micbias, 2700 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2701 SND_SOC_DAPM_POST_PMD), 2702 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 2703 wcd939x_codec_enable_micbias, 2704 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2705 SND_SOC_DAPM_POST_PMD), 2706 2707 /* micbias pull up widgets */ 2708 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2709 wcd939x_codec_enable_micbias_pullup, 2710 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2711 SND_SOC_DAPM_POST_PMD), 2712 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2713 wcd939x_codec_enable_micbias_pullup, 2714 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2715 SND_SOC_DAPM_POST_PMD), 2716 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2717 wcd939x_codec_enable_micbias_pullup, 2718 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2719 SND_SOC_DAPM_POST_PMD), 2720 SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 2721 wcd939x_codec_enable_micbias_pullup, 2722 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2723 SND_SOC_DAPM_POST_PMD), 2724 2725 /* output widgets tx */ 2726 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 2727 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 2728 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 2729 SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"), 2730 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 2731 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 2732 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 2733 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 2734 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 2735 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 2736 SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"), 2737 SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"), 2738 2739 SND_SOC_DAPM_INPUT("IN1_HPHL"), 2740 SND_SOC_DAPM_INPUT("IN2_HPHR"), 2741 SND_SOC_DAPM_INPUT("IN3_EAR"), 2742 2743 /* rx widgets */ 2744 SND_SOC_DAPM_PGA_E("EAR PGA", WCD939X_ANA_EAR, 7, 0, NULL, 0, 2745 wcd939x_codec_enable_ear_pa, 2746 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2747 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2748 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD939X_ANA_HPH, 7, 0, NULL, 0, 2749 wcd939x_codec_enable_hphl_pa, 2750 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2751 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2752 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD939X_ANA_HPH, 6, 0, NULL, 0, 2753 wcd939x_codec_enable_hphr_pa, 2754 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2755 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2756 2757 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 2758 wcd939x_codec_hphl_dac_event, 2759 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2760 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2761 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 2762 wcd939x_codec_hphr_dac_event, 2763 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2764 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2765 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 2766 wcd939x_codec_ear_dac_event, 2767 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2768 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2769 2770 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 2771 2772 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 2773 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0, 2774 wcd939x_codec_enable_rxclk, 2775 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2776 SND_SOC_DAPM_POST_PMD), 2777 2778 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 2779 2780 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2781 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2782 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2783 2784 /* rx mixer widgets */ 2785 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 2786 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 2787 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 2788 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 2789 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 2790 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 2791 2792 /* output widgets rx */ 2793 SND_SOC_DAPM_OUTPUT("EAR"), 2794 SND_SOC_DAPM_OUTPUT("HPHL"), 2795 SND_SOC_DAPM_OUTPUT("HPHR"), 2796 }; 2797 2798 static const struct snd_soc_dapm_route wcd939x_audio_map[] = { 2799 /* TX Path */ 2800 {"ADC1_OUTPUT", NULL, "ADC1_MIXER"}, 2801 {"ADC1_MIXER", "Switch", "ADC1 REQ"}, 2802 {"ADC1 REQ", NULL, "ADC1"}, 2803 {"ADC1", NULL, "ADC1 MUX"}, 2804 {"ADC1 MUX", "CH1_AMIC1", "AMIC1"}, 2805 {"ADC1 MUX", "CH1_AMIC2", "AMIC2"}, 2806 {"ADC1 MUX", "CH1_AMIC3", "AMIC3"}, 2807 {"ADC1 MUX", "CH1_AMIC4", "AMIC4"}, 2808 {"ADC1 MUX", "CH1_AMIC5", "AMIC5"}, 2809 2810 {"ADC2_OUTPUT", NULL, "ADC2_MIXER"}, 2811 {"ADC2_MIXER", "Switch", "ADC2 REQ"}, 2812 {"ADC2 REQ", NULL, "ADC2"}, 2813 {"ADC2", NULL, "ADC2 MUX"}, 2814 {"ADC2 MUX", "CH2_AMIC1", "AMIC1"}, 2815 {"ADC2 MUX", "CH2_AMIC2", "AMIC2"}, 2816 {"ADC2 MUX", "CH2_AMIC3", "AMIC3"}, 2817 {"ADC2 MUX", "CH2_AMIC4", "AMIC4"}, 2818 {"ADC2 MUX", "CH2_AMIC5", "AMIC5"}, 2819 2820 {"ADC3_OUTPUT", NULL, "ADC3_MIXER"}, 2821 {"ADC3_MIXER", "Switch", "ADC3 REQ"}, 2822 {"ADC3 REQ", NULL, "ADC3"}, 2823 {"ADC3", NULL, "ADC3 MUX"}, 2824 {"ADC3 MUX", "CH3_AMIC1", "AMIC1"}, 2825 {"ADC3 MUX", "CH3_AMIC3", "AMIC3"}, 2826 {"ADC3 MUX", "CH3_AMIC4", "AMIC4"}, 2827 {"ADC3 MUX", "CH3_AMIC5", "AMIC5"}, 2828 2829 {"ADC4_OUTPUT", NULL, "ADC4_MIXER"}, 2830 {"ADC4_MIXER", "Switch", "ADC4 REQ"}, 2831 {"ADC4 REQ", NULL, "ADC4"}, 2832 {"ADC4", NULL, "ADC4 MUX"}, 2833 {"ADC4 MUX", "CH4_AMIC1", "AMIC1"}, 2834 {"ADC4 MUX", "CH4_AMIC3", "AMIC3"}, 2835 {"ADC4 MUX", "CH4_AMIC4", "AMIC4"}, 2836 {"ADC4 MUX", "CH4_AMIC5", "AMIC5"}, 2837 2838 {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"}, 2839 {"DMIC1_MIXER", "Switch", "DMIC1"}, 2840 2841 {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"}, 2842 {"DMIC2_MIXER", "Switch", "DMIC2"}, 2843 2844 {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"}, 2845 {"DMIC3_MIXER", "Switch", "DMIC3"}, 2846 2847 {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"}, 2848 {"DMIC4_MIXER", "Switch", "DMIC4"}, 2849 2850 {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"}, 2851 {"DMIC5_MIXER", "Switch", "DMIC5"}, 2852 2853 {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"}, 2854 {"DMIC6_MIXER", "Switch", "DMIC6"}, 2855 2856 {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"}, 2857 {"DMIC7_MIXER", "Switch", "DMIC7"}, 2858 2859 {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"}, 2860 {"DMIC8_MIXER", "Switch", "DMIC8"}, 2861 2862 /* RX Path */ 2863 {"IN1_HPHL", NULL, "VDD_BUCK"}, 2864 {"IN1_HPHL", NULL, "CLS_H_PORT"}, 2865 2866 {"RX1", NULL, "IN1_HPHL"}, 2867 {"RX1", NULL, "RXCLK"}, 2868 {"RDAC1", NULL, "RX1"}, 2869 {"HPHL_RDAC", "Switch", "RDAC1"}, 2870 {"HPHL PGA", NULL, "HPHL_RDAC"}, 2871 {"HPHL", NULL, "HPHL PGA"}, 2872 2873 {"IN2_HPHR", NULL, "VDD_BUCK"}, 2874 {"IN2_HPHR", NULL, "CLS_H_PORT"}, 2875 {"RX2", NULL, "IN2_HPHR"}, 2876 {"RDAC2", NULL, "RX2"}, 2877 {"RX2", NULL, "RXCLK"}, 2878 {"HPHR_RDAC", "Switch", "RDAC2"}, 2879 {"HPHR PGA", NULL, "HPHR_RDAC"}, 2880 {"HPHR", NULL, "HPHR PGA"}, 2881 2882 {"IN3_EAR", NULL, "VDD_BUCK"}, 2883 {"RX3", NULL, "IN3_EAR"}, 2884 {"RX3", NULL, "RXCLK"}, 2885 2886 {"RDAC3_MUX", "RX3", "RX3"}, 2887 {"RDAC3_MUX", "RX1", "RX1"}, 2888 {"RDAC3", NULL, "RDAC3_MUX"}, 2889 {"EAR_RDAC", "Switch", "RDAC3"}, 2890 {"EAR PGA", NULL, "EAR_RDAC"}, 2891 {"EAR", NULL, "EAR PGA"}, 2892 }; 2893 2894 static int wcd939x_set_micbias_data(struct wcd939x_priv *wcd939x) 2895 { 2896 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4; 2897 2898 /* set micbias voltage */ 2899 vout_ctl_1 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb1_mv); 2900 vout_ctl_2 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb2_mv); 2901 vout_ctl_3 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb3_mv); 2902 vout_ctl_4 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb4_mv); 2903 if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0) 2904 return -EINVAL; 2905 2906 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB1, 2907 WCD939X_MICB_VOUT_CTL, vout_ctl_1); 2908 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB2, 2909 WCD939X_MICB_VOUT_CTL, vout_ctl_2); 2910 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB3, 2911 WCD939X_MICB_VOUT_CTL, vout_ctl_3); 2912 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB4, 2913 WCD939X_MICB_VOUT_CTL, vout_ctl_4); 2914 2915 return 0; 2916 } 2917 2918 static irqreturn_t wcd939x_wd_handle_irq(int irq, void *data) 2919 { 2920 /* 2921 * HPHR/HPHL/EAR Watchdog interrupt threaded handler 2922 * 2923 * Watchdog interrupts are expected to be enabled when switching 2924 * on the HPHL/R and EAR RX PGA in order to make sure the interrupts 2925 * are acked by the regmap_irq handler to allow PDM sync. 2926 * We could leave those interrupts masked but we would not have 2927 * any valid way to enable/disable them without violating irq layers. 2928 * 2929 * The HPHR/HPHL/EAR Watchdog interrupts are handled 2930 * by regmap_irq, so requesting a threaded handler is the 2931 * safest way to be able to ack those interrupts without 2932 * colliding with the regmap_irq setup. 2933 */ 2934 2935 return IRQ_HANDLED; 2936 } 2937 2938 /* 2939 * Setup a virtual interrupt domain to hook regmap_irq 2940 * The root domain will have a single interrupt which mapping 2941 * will trigger the regmap_irq handler. 2942 * 2943 * root: 2944 * wcd_irq_chip 2945 * [0] wcd939x_regmap_irq_chip 2946 * [0] MBHC_BUTTON_PRESS_DET 2947 * [1] MBHC_BUTTON_RELEASE_DET 2948 * ... 2949 * [16] HPHR_SURGE_DET_INT 2950 * 2951 * Interrupt trigger: 2952 * soundwire_interrupt_callback() 2953 * \-handle_nested_irq(0) 2954 * \- regmap_irq_thread() 2955 * \- handle_nested_irq(i) 2956 */ 2957 static const struct irq_chip wcd_irq_chip = { 2958 .name = "WCD939x", 2959 }; 2960 2961 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 2962 irq_hw_number_t hw) 2963 { 2964 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 2965 irq_set_nested_thread(virq, 1); 2966 irq_set_noprobe(virq); 2967 2968 return 0; 2969 } 2970 2971 static const struct irq_domain_ops wcd_domain_ops = { 2972 .map = wcd_irq_chip_map, 2973 }; 2974 2975 static int wcd939x_irq_init(struct wcd939x_priv *wcd, struct device *dev) 2976 { 2977 wcd->virq = irq_domain_create_linear(NULL, 1, &wcd_domain_ops, NULL); 2978 if (!(wcd->virq)) { 2979 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 2980 return -EINVAL; 2981 } 2982 2983 return devm_regmap_add_irq_chip(dev, wcd->regmap, 2984 irq_create_mapping(wcd->virq, 0), 2985 IRQF_ONESHOT, 0, &wcd939x_regmap_irq_chip, 2986 &wcd->irq_chip); 2987 } 2988 2989 static int wcd939x_soc_codec_probe(struct snd_soc_component *component) 2990 { 2991 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2992 struct sdw_slave *tx_sdw_dev = wcd939x->tx_sdw_dev; 2993 struct device *dev = component->dev; 2994 unsigned long time_left; 2995 int ret, i; 2996 2997 time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete, 2998 msecs_to_jiffies(2000)); 2999 if (!time_left) { 3000 dev_err(dev, "soundwire device init timeout\n"); 3001 return -ETIMEDOUT; 3002 } 3003 3004 snd_soc_component_init_regmap(component, wcd939x->regmap); 3005 3006 ret = pm_runtime_resume_and_get(dev); 3007 if (ret < 0) 3008 return ret; 3009 3010 wcd939x->variant = snd_soc_component_read_field(component, 3011 WCD939X_DIGITAL_EFUSE_REG_0, 3012 WCD939X_EFUSE_REG_0_WCD939X_ID); 3013 3014 wcd939x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD939X); 3015 if (IS_ERR(wcd939x->clsh_info)) { 3016 pm_runtime_put(dev); 3017 return PTR_ERR(wcd939x->clsh_info); 3018 } 3019 3020 wcd939x_io_init(component); 3021 3022 /* Set all interrupts as edge triggered */ 3023 for (i = 0; i < wcd939x_regmap_irq_chip.num_regs; i++) 3024 regmap_write(wcd939x->regmap, 3025 (WCD939X_DIGITAL_INTR_LEVEL_0 + i), 0); 3026 3027 pm_runtime_put(dev); 3028 3029 /* Request for watchdog interrupt */ 3030 wcd939x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip, 3031 WCD939X_IRQ_HPHR_PDM_WD_INT); 3032 wcd939x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip, 3033 WCD939X_IRQ_HPHL_PDM_WD_INT); 3034 wcd939x->ear_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip, 3035 WCD939X_IRQ_EAR_PDM_WD_INT); 3036 3037 ret = request_threaded_irq(wcd939x->hphr_pdm_wd_int, NULL, wcd939x_wd_handle_irq, 3038 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3039 "HPHR PDM WD INT", wcd939x); 3040 if (ret) { 3041 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret); 3042 goto err_free_clsh_ctrl; 3043 } 3044 3045 ret = request_threaded_irq(wcd939x->hphl_pdm_wd_int, NULL, wcd939x_wd_handle_irq, 3046 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3047 "HPHL PDM WD INT", wcd939x); 3048 if (ret) { 3049 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret); 3050 goto err_free_hphr_pdm_wd_int; 3051 } 3052 3053 ret = request_threaded_irq(wcd939x->ear_pdm_wd_int, NULL, wcd939x_wd_handle_irq, 3054 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3055 "AUX PDM WD INT", wcd939x); 3056 if (ret) { 3057 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret); 3058 goto err_free_hphl_pdm_wd_int; 3059 } 3060 3061 /* Disable watchdog interrupt for HPH and AUX */ 3062 disable_irq_nosync(wcd939x->hphr_pdm_wd_int); 3063 disable_irq_nosync(wcd939x->hphl_pdm_wd_int); 3064 disable_irq_nosync(wcd939x->ear_pdm_wd_int); 3065 3066 switch (wcd939x->variant) { 3067 case WCD9390: 3068 ret = snd_soc_add_component_controls(component, wcd9390_snd_controls, 3069 ARRAY_SIZE(wcd9390_snd_controls)); 3070 if (ret < 0) { 3071 dev_err(component->dev, 3072 "%s: Failed to add snd ctrls for variant: %d\n", 3073 __func__, wcd939x->variant); 3074 goto err_free_ear_pdm_wd_int; 3075 } 3076 break; 3077 case WCD9395: 3078 ret = snd_soc_add_component_controls(component, wcd9395_snd_controls, 3079 ARRAY_SIZE(wcd9395_snd_controls)); 3080 if (ret < 0) { 3081 dev_err(component->dev, 3082 "%s: Failed to add snd ctrls for variant: %d\n", 3083 __func__, wcd939x->variant); 3084 goto err_free_ear_pdm_wd_int; 3085 } 3086 break; 3087 default: 3088 break; 3089 } 3090 3091 ret = wcd939x_mbhc_init(component); 3092 if (ret) { 3093 dev_err(component->dev, "mbhc initialization failed\n"); 3094 goto err_free_ear_pdm_wd_int; 3095 } 3096 3097 return 0; 3098 3099 err_free_ear_pdm_wd_int: 3100 free_irq(wcd939x->ear_pdm_wd_int, wcd939x); 3101 err_free_hphl_pdm_wd_int: 3102 free_irq(wcd939x->hphl_pdm_wd_int, wcd939x); 3103 err_free_hphr_pdm_wd_int: 3104 free_irq(wcd939x->hphr_pdm_wd_int, wcd939x); 3105 err_free_clsh_ctrl: 3106 wcd_clsh_ctrl_free(wcd939x->clsh_info); 3107 3108 return ret; 3109 } 3110 3111 static void wcd939x_soc_codec_remove(struct snd_soc_component *component) 3112 { 3113 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 3114 3115 wcd939x_mbhc_deinit(component); 3116 3117 free_irq(wcd939x->ear_pdm_wd_int, wcd939x); 3118 free_irq(wcd939x->hphl_pdm_wd_int, wcd939x); 3119 free_irq(wcd939x->hphr_pdm_wd_int, wcd939x); 3120 3121 wcd_clsh_ctrl_free(wcd939x->clsh_info); 3122 } 3123 3124 static int wcd939x_codec_set_jack(struct snd_soc_component *comp, 3125 struct snd_soc_jack *jack, void *data) 3126 { 3127 struct wcd939x_priv *wcd = dev_get_drvdata(comp->dev); 3128 3129 if (jack) 3130 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 3131 3132 wcd_mbhc_stop(wcd->wcd_mbhc); 3133 3134 return 0; 3135 } 3136 3137 static const struct snd_soc_component_driver soc_codec_dev_wcd939x = { 3138 .name = "wcd939x_codec", 3139 .probe = wcd939x_soc_codec_probe, 3140 .remove = wcd939x_soc_codec_remove, 3141 .controls = wcd939x_snd_controls, 3142 .num_controls = ARRAY_SIZE(wcd939x_snd_controls), 3143 .dapm_widgets = wcd939x_dapm_widgets, 3144 .num_dapm_widgets = ARRAY_SIZE(wcd939x_dapm_widgets), 3145 .dapm_routes = wcd939x_audio_map, 3146 .num_dapm_routes = ARRAY_SIZE(wcd939x_audio_map), 3147 .set_jack = wcd939x_codec_set_jack, 3148 .endianness = 1, 3149 }; 3150 3151 #if IS_ENABLED(CONFIG_TYPEC) 3152 /* Get USB-C plug orientation to provide swap event for MBHC */ 3153 static int wcd939x_typec_switch_set(struct typec_switch_dev *sw, 3154 enum typec_orientation orientation) 3155 { 3156 struct wcd939x_priv *wcd939x = typec_switch_get_drvdata(sw); 3157 3158 wcd939x->typec_orientation = orientation; 3159 3160 return 0; 3161 } 3162 3163 static int wcd939x_typec_mux_set(struct typec_mux_dev *mux, 3164 struct typec_mux_state *state) 3165 { 3166 struct wcd939x_priv *wcd939x = typec_mux_get_drvdata(mux); 3167 unsigned int previous_mode = wcd939x->typec_mode; 3168 3169 if (!wcd939x->wcd_mbhc) 3170 return -EINVAL; 3171 3172 if (wcd939x->typec_mode != state->mode) { 3173 wcd939x->typec_mode = state->mode; 3174 3175 if (wcd939x->typec_mode == TYPEC_MODE_AUDIO) 3176 return wcd_mbhc_typec_report_plug(wcd939x->wcd_mbhc); 3177 else if (previous_mode == TYPEC_MODE_AUDIO) 3178 return wcd_mbhc_typec_report_unplug(wcd939x->wcd_mbhc); 3179 } 3180 3181 return 0; 3182 } 3183 #endif /* CONFIG_TYPEC */ 3184 3185 static void wcd939x_dt_parse_micbias_info(struct device *dev, struct wcd939x_priv *wcd) 3186 { 3187 struct device_node *np = dev->of_node; 3188 u32 prop_val = 0; 3189 int rc = 0; 3190 3191 rc = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val); 3192 if (!rc) 3193 wcd->micb1_mv = prop_val / 1000; 3194 else 3195 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__); 3196 3197 rc = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val); 3198 if (!rc) 3199 wcd->micb2_mv = prop_val / 1000; 3200 else 3201 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__); 3202 3203 rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val); 3204 if (!rc) 3205 wcd->micb3_mv = prop_val / 1000; 3206 else 3207 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__); 3208 3209 rc = of_property_read_u32(np, "qcom,micbias4-microvolt", &prop_val); 3210 if (!rc) 3211 wcd->micb4_mv = prop_val / 1000; 3212 else 3213 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__); 3214 } 3215 3216 #if IS_ENABLED(CONFIG_TYPEC) 3217 static bool wcd939x_swap_gnd_mic(struct snd_soc_component *component) 3218 { 3219 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 3220 3221 if (!wcd939x->typec_analog_mux || !wcd939x->typec_switch) 3222 return false; 3223 3224 /* Report inversion via Type Switch of USBSS */ 3225 typec_switch_set(wcd939x->typec_switch, 3226 wcd939x->typec_orientation == TYPEC_ORIENTATION_REVERSE ? 3227 TYPEC_ORIENTATION_NORMAL : TYPEC_ORIENTATION_REVERSE); 3228 3229 return true; 3230 } 3231 #endif /* CONFIG_TYPEC */ 3232 3233 static int wcd939x_populate_dt_data(struct wcd939x_priv *wcd939x, struct device *dev) 3234 { 3235 struct wcd_mbhc_config *cfg = &wcd939x->mbhc_cfg; 3236 #if IS_ENABLED(CONFIG_TYPEC) 3237 struct device_node *np; 3238 #endif /* CONFIG_TYPEC */ 3239 int ret; 3240 3241 wcd939x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 3242 if (IS_ERR(wcd939x->reset_gpio)) { 3243 ret = PTR_ERR(wcd939x->reset_gpio); 3244 return dev_err_probe(dev, ret, "Failed to get reset gpio\n"); 3245 } 3246 3247 wcd939x->supplies[0].supply = "vdd-rxtx"; 3248 wcd939x->supplies[1].supply = "vdd-io"; 3249 wcd939x->supplies[2].supply = "vdd-buck"; 3250 wcd939x->supplies[3].supply = "vdd-mic-bias"; 3251 3252 ret = regulator_bulk_get(dev, WCD939X_MAX_SUPPLY, wcd939x->supplies); 3253 if (ret) 3254 return dev_err_probe(dev, ret, "Failed to get supplies\n"); 3255 3256 ret = regulator_bulk_enable(WCD939X_MAX_SUPPLY, wcd939x->supplies); 3257 if (ret) { 3258 regulator_bulk_free(WCD939X_MAX_SUPPLY, wcd939x->supplies); 3259 return dev_err_probe(dev, ret, "Failed to enable supplies\n"); 3260 } 3261 3262 wcd939x_dt_parse_micbias_info(dev, wcd939x); 3263 3264 cfg->mbhc_micbias = MIC_BIAS_2; 3265 cfg->anc_micbias = MIC_BIAS_2; 3266 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 3267 cfg->num_btn = WCD939X_MBHC_MAX_BUTTONS; 3268 cfg->micb_mv = wcd939x->micb2_mv; 3269 cfg->linein_th = 5000; 3270 cfg->hs_thr = 1700; 3271 cfg->hph_thr = 50; 3272 3273 wcd_dt_parse_mbhc_data(dev, cfg); 3274 3275 #if IS_ENABLED(CONFIG_TYPEC) 3276 /* 3277 * Is node has a port and a valid remote endpoint 3278 * consider HP lines are connected to the USBSS part 3279 */ 3280 np = of_graph_get_remote_node(dev->of_node, 0, 0); 3281 if (np) { 3282 wcd939x->typec_analog_mux = true; 3283 cfg->typec_analog_mux = true; 3284 cfg->swap_gnd_mic = wcd939x_swap_gnd_mic; 3285 } 3286 #endif /* CONFIG_TYPEC */ 3287 3288 return 0; 3289 } 3290 3291 static int wcd939x_reset(struct wcd939x_priv *wcd939x) 3292 { 3293 gpiod_set_value(wcd939x->reset_gpio, 1); 3294 /* 20us sleep required after pulling the reset gpio to LOW */ 3295 usleep_range(20, 30); 3296 gpiod_set_value(wcd939x->reset_gpio, 0); 3297 /* 20us sleep required after pulling the reset gpio to HIGH */ 3298 usleep_range(20, 30); 3299 3300 return 0; 3301 } 3302 3303 static int wcd939x_codec_hw_params(struct snd_pcm_substream *substream, 3304 struct snd_pcm_hw_params *params, 3305 struct snd_soc_dai *dai) 3306 { 3307 struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev); 3308 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id]; 3309 3310 return wcd939x_sdw_hw_params(wcd, substream, params, dai); 3311 } 3312 3313 static int wcd939x_codec_free(struct snd_pcm_substream *substream, 3314 struct snd_soc_dai *dai) 3315 { 3316 struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev); 3317 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id]; 3318 3319 return wcd939x_sdw_free(wcd, substream, dai); 3320 } 3321 3322 static int wcd939x_codec_set_sdw_stream(struct snd_soc_dai *dai, 3323 void *stream, int direction) 3324 { 3325 struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev); 3326 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id]; 3327 3328 return wcd939x_sdw_set_sdw_stream(wcd, dai, stream, direction); 3329 } 3330 3331 static const struct snd_soc_dai_ops wcd939x_sdw_dai_ops = { 3332 .hw_params = wcd939x_codec_hw_params, 3333 .hw_free = wcd939x_codec_free, 3334 .set_stream = wcd939x_codec_set_sdw_stream, 3335 }; 3336 3337 static struct snd_soc_dai_driver wcd939x_dais[] = { 3338 [0] = { 3339 .name = "wcd939x-sdw-rx", 3340 .playback = { 3341 .stream_name = "WCD AIF1 Playback", 3342 .rates = WCD939X_RATES_MASK | WCD939X_FRAC_RATES_MASK, 3343 .formats = WCD939X_FORMATS, 3344 .rate_max = 384000, 3345 .rate_min = 8000, 3346 .channels_min = 1, 3347 .channels_max = 2, 3348 }, 3349 .ops = &wcd939x_sdw_dai_ops, 3350 }, 3351 [1] = { 3352 .name = "wcd939x-sdw-tx", 3353 .capture = { 3354 .stream_name = "WCD AIF1 Capture", 3355 .rates = WCD939X_RATES_MASK | WCD939X_FRAC_RATES_MASK, 3356 .formats = WCD939X_FORMATS, 3357 .rate_min = 8000, 3358 .rate_max = 384000, 3359 .channels_min = 1, 3360 .channels_max = 4, 3361 }, 3362 .ops = &wcd939x_sdw_dai_ops, 3363 }, 3364 }; 3365 3366 static int wcd939x_bind(struct device *dev) 3367 { 3368 struct wcd939x_priv *wcd939x = dev_get_drvdata(dev); 3369 unsigned int version, id1, status1; 3370 int ret; 3371 3372 #if IS_ENABLED(CONFIG_TYPEC) 3373 /* 3374 * Get USBSS type-c switch to send gnd/mic swap events 3375 * typec_switch is fetched now to avoid a probe deadlock since 3376 * the USBSS depends on the typec_mux register in wcd939x_probe() 3377 */ 3378 if (wcd939x->typec_analog_mux) { 3379 wcd939x->typec_switch = fwnode_typec_switch_get(dev->fwnode); 3380 if (IS_ERR(wcd939x->typec_switch)) 3381 return dev_err_probe(dev, PTR_ERR(wcd939x->typec_switch), 3382 "failed to acquire orientation-switch\n"); 3383 } 3384 #endif /* CONFIG_TYPEC */ 3385 3386 ret = component_bind_all(dev, wcd939x); 3387 if (ret) { 3388 dev_err(dev, "%s: Slave bind failed, ret = %d\n", 3389 __func__, ret); 3390 goto err_put_typec_switch; 3391 } 3392 3393 wcd939x->rxdev = wcd939x_sdw_device_get(wcd939x->rxnode); 3394 if (!wcd939x->rxdev) { 3395 dev_err(dev, "could not find slave with matching of node\n"); 3396 ret = -EINVAL; 3397 goto err_unbind; 3398 } 3399 wcd939x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd939x->rxdev); 3400 wcd939x->sdw_priv[AIF1_PB]->wcd939x = wcd939x; 3401 3402 wcd939x->txdev = wcd939x_sdw_device_get(wcd939x->txnode); 3403 if (!wcd939x->txdev) { 3404 dev_err(dev, "could not find txslave with matching of node\n"); 3405 ret = -EINVAL; 3406 goto err_put_rxdev; 3407 } 3408 wcd939x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd939x->txdev); 3409 wcd939x->sdw_priv[AIF1_CAP]->wcd939x = wcd939x; 3410 wcd939x->tx_sdw_dev = dev_to_sdw_dev(wcd939x->txdev); 3411 3412 /* 3413 * As TX is main CSR reg interface, which should not be suspended first. 3414 * explicitly add the dependency link 3415 */ 3416 if (!device_link_add(wcd939x->rxdev, wcd939x->txdev, DL_FLAG_STATELESS | 3417 DL_FLAG_PM_RUNTIME)) { 3418 dev_err(dev, "could not devlink tx and rx\n"); 3419 ret = -EINVAL; 3420 goto err_put_txdev; 3421 } 3422 3423 if (!device_link_add(dev, wcd939x->txdev, DL_FLAG_STATELESS | 3424 DL_FLAG_PM_RUNTIME)) { 3425 dev_err(dev, "could not devlink wcd and tx\n"); 3426 ret = -EINVAL; 3427 goto err_remove_rxtx_link; 3428 } 3429 3430 if (!device_link_add(dev, wcd939x->rxdev, DL_FLAG_STATELESS | 3431 DL_FLAG_PM_RUNTIME)) { 3432 dev_err(dev, "could not devlink wcd and rx\n"); 3433 ret = -EINVAL; 3434 goto err_remove_tx_link; 3435 } 3436 3437 /* Get regmap from TX SoundWire device */ 3438 wcd939x->regmap = wcd939x_swr_get_regmap(wcd939x->sdw_priv[AIF1_CAP]); 3439 if (IS_ERR(wcd939x->regmap)) { 3440 dev_err(dev, "could not get TX device regmap\n"); 3441 ret = PTR_ERR(wcd939x->regmap); 3442 goto err_remove_rx_link; 3443 } 3444 3445 ret = wcd939x_irq_init(wcd939x, dev); 3446 if (ret) { 3447 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret); 3448 goto err_remove_rx_link; 3449 } 3450 3451 wcd939x->sdw_priv[AIF1_PB]->slave_irq = wcd939x->virq; 3452 wcd939x->sdw_priv[AIF1_CAP]->slave_irq = wcd939x->virq; 3453 3454 ret = wcd939x_set_micbias_data(wcd939x); 3455 if (ret < 0) { 3456 dev_err(dev, "%s: bad micbias pdata\n", __func__); 3457 goto err_remove_rx_link; 3458 } 3459 3460 /* Check WCD9395 version */ 3461 regmap_read(wcd939x->regmap, WCD939X_DIGITAL_CHIP_ID1, &id1); 3462 regmap_read(wcd939x->regmap, WCD939X_EAR_STATUS_REG_1, &status1); 3463 3464 if (id1 == 0) 3465 version = ((status1 & 0x3) ? WCD939X_VERSION_1_1 : WCD939X_VERSION_1_0); 3466 else 3467 version = WCD939X_VERSION_2_0; 3468 3469 dev_dbg(dev, "wcd939x version: %s\n", version_to_str(version)); 3470 3471 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd939x, 3472 wcd939x_dais, ARRAY_SIZE(wcd939x_dais)); 3473 if (ret) { 3474 dev_err(dev, "%s: Codec registration failed\n", 3475 __func__); 3476 goto err_remove_rx_link; 3477 } 3478 3479 return 0; 3480 3481 err_remove_rx_link: 3482 device_link_remove(dev, wcd939x->rxdev); 3483 err_remove_tx_link: 3484 device_link_remove(dev, wcd939x->txdev); 3485 err_remove_rxtx_link: 3486 device_link_remove(wcd939x->rxdev, wcd939x->txdev); 3487 err_put_txdev: 3488 put_device(wcd939x->txdev); 3489 err_put_rxdev: 3490 put_device(wcd939x->rxdev); 3491 err_unbind: 3492 component_unbind_all(dev, wcd939x); 3493 err_put_typec_switch: 3494 #if IS_ENABLED(CONFIG_TYPEC) 3495 if (wcd939x->typec_analog_mux) 3496 typec_switch_put(wcd939x->typec_switch); 3497 #endif /* CONFIG_TYPEC */ 3498 3499 return ret; 3500 } 3501 3502 static void wcd939x_unbind(struct device *dev) 3503 { 3504 struct wcd939x_priv *wcd939x = dev_get_drvdata(dev); 3505 3506 snd_soc_unregister_component(dev); 3507 device_link_remove(dev, wcd939x->txdev); 3508 device_link_remove(dev, wcd939x->rxdev); 3509 device_link_remove(wcd939x->rxdev, wcd939x->txdev); 3510 put_device(wcd939x->txdev); 3511 put_device(wcd939x->rxdev); 3512 component_unbind_all(dev, wcd939x); 3513 } 3514 3515 static const struct component_master_ops wcd939x_comp_ops = { 3516 .bind = wcd939x_bind, 3517 .unbind = wcd939x_unbind, 3518 }; 3519 3520 static void __maybe_unused wcd939x_typec_mux_unregister(void *data) 3521 { 3522 struct typec_mux_dev *typec_mux = data; 3523 3524 typec_mux_unregister(typec_mux); 3525 } 3526 3527 static void __maybe_unused wcd939x_typec_switch_unregister(void *data) 3528 { 3529 struct typec_switch_dev *typec_sw = data; 3530 3531 typec_switch_unregister(typec_sw); 3532 } 3533 3534 static int wcd939x_add_typec(struct wcd939x_priv *wcd939x, struct device *dev) 3535 { 3536 #if IS_ENABLED(CONFIG_TYPEC) 3537 int ret; 3538 struct typec_mux_dev *typec_mux; 3539 struct typec_switch_dev *typec_sw; 3540 struct typec_mux_desc mux_desc = { 3541 .drvdata = wcd939x, 3542 .fwnode = dev_fwnode(dev), 3543 .set = wcd939x_typec_mux_set, 3544 }; 3545 struct typec_switch_desc sw_desc = { 3546 .drvdata = wcd939x, 3547 .fwnode = dev_fwnode(dev), 3548 .set = wcd939x_typec_switch_set, 3549 }; 3550 3551 /* 3552 * Is USBSS is used to mux analog lines, 3553 * register a typec mux/switch to get typec events 3554 */ 3555 if (!wcd939x->typec_analog_mux) 3556 return 0; 3557 3558 typec_mux = typec_mux_register(dev, &mux_desc); 3559 if (IS_ERR(typec_mux)) 3560 return dev_err_probe(dev, PTR_ERR(typec_mux), 3561 "failed to register typec mux\n"); 3562 3563 ret = devm_add_action_or_reset(dev, wcd939x_typec_mux_unregister, 3564 typec_mux); 3565 if (ret) 3566 return ret; 3567 3568 typec_sw = typec_switch_register(dev, &sw_desc); 3569 if (IS_ERR(typec_sw)) 3570 return dev_err_probe(dev, PTR_ERR(typec_sw), 3571 "failed to register typec switch\n"); 3572 3573 ret = devm_add_action_or_reset(dev, wcd939x_typec_switch_unregister, 3574 typec_sw); 3575 if (ret) 3576 return ret; 3577 #endif 3578 3579 return 0; 3580 } 3581 3582 static int wcd939x_add_slave_components(struct wcd939x_priv *wcd939x, 3583 struct device *dev, 3584 struct component_match **matchptr) 3585 { 3586 struct device_node *np = dev->of_node; 3587 3588 wcd939x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 3589 if (!wcd939x->rxnode) { 3590 dev_err(dev, "%s: Rx-device node not defined\n", __func__); 3591 return -ENODEV; 3592 } 3593 3594 of_node_get(wcd939x->rxnode); 3595 component_match_add_release(dev, matchptr, component_release_of, 3596 component_compare_of, wcd939x->rxnode); 3597 3598 wcd939x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 3599 if (!wcd939x->txnode) { 3600 dev_err(dev, "%s: Tx-device node not defined\n", __func__); 3601 return -ENODEV; 3602 } 3603 of_node_get(wcd939x->txnode); 3604 component_match_add_release(dev, matchptr, component_release_of, 3605 component_compare_of, wcd939x->txnode); 3606 return 0; 3607 } 3608 3609 static int wcd939x_probe(struct platform_device *pdev) 3610 { 3611 struct component_match *match = NULL; 3612 struct wcd939x_priv *wcd939x = NULL; 3613 struct device *dev = &pdev->dev; 3614 int ret; 3615 3616 wcd939x = devm_kzalloc(dev, sizeof(struct wcd939x_priv), 3617 GFP_KERNEL); 3618 if (!wcd939x) 3619 return -ENOMEM; 3620 3621 dev_set_drvdata(dev, wcd939x); 3622 mutex_init(&wcd939x->micb_lock); 3623 3624 ret = wcd939x_populate_dt_data(wcd939x, dev); 3625 if (ret) { 3626 dev_err(dev, "%s: Fail to obtain platform data\n", __func__); 3627 return -EINVAL; 3628 } 3629 3630 ret = wcd939x_add_typec(wcd939x, dev); 3631 if (ret) 3632 goto err_disable_regulators; 3633 3634 ret = wcd939x_add_slave_components(wcd939x, dev, &match); 3635 if (ret) 3636 goto err_disable_regulators; 3637 3638 wcd939x_reset(wcd939x); 3639 3640 ret = component_master_add_with_match(dev, &wcd939x_comp_ops, match); 3641 if (ret) 3642 goto err_disable_regulators; 3643 3644 pm_runtime_set_autosuspend_delay(dev, 1000); 3645 pm_runtime_use_autosuspend(dev); 3646 pm_runtime_mark_last_busy(dev); 3647 pm_runtime_set_active(dev); 3648 pm_runtime_enable(dev); 3649 pm_runtime_idle(dev); 3650 3651 return 0; 3652 3653 err_disable_regulators: 3654 regulator_bulk_disable(WCD939X_MAX_SUPPLY, wcd939x->supplies); 3655 regulator_bulk_free(WCD939X_MAX_SUPPLY, wcd939x->supplies); 3656 3657 return ret; 3658 } 3659 3660 static void wcd939x_remove(struct platform_device *pdev) 3661 { 3662 struct device *dev = &pdev->dev; 3663 struct wcd939x_priv *wcd939x = dev_get_drvdata(dev); 3664 3665 component_master_del(dev, &wcd939x_comp_ops); 3666 3667 pm_runtime_disable(dev); 3668 pm_runtime_set_suspended(dev); 3669 pm_runtime_dont_use_autosuspend(dev); 3670 3671 regulator_bulk_disable(WCD939X_MAX_SUPPLY, wcd939x->supplies); 3672 regulator_bulk_free(WCD939X_MAX_SUPPLY, wcd939x->supplies); 3673 } 3674 3675 #if defined(CONFIG_OF) 3676 static const struct of_device_id wcd939x_dt_match[] = { 3677 { .compatible = "qcom,wcd9390-codec" }, 3678 { .compatible = "qcom,wcd9395-codec" }, 3679 {} 3680 }; 3681 MODULE_DEVICE_TABLE(of, wcd939x_dt_match); 3682 #endif 3683 3684 static struct platform_driver wcd939x_codec_driver = { 3685 .probe = wcd939x_probe, 3686 .remove = wcd939x_remove, 3687 .driver = { 3688 .name = "wcd939x_codec", 3689 .of_match_table = of_match_ptr(wcd939x_dt_match), 3690 .suppress_bind_attrs = true, 3691 }, 3692 }; 3693 3694 module_platform_driver(wcd939x_codec_driver); 3695 MODULE_DESCRIPTION("WCD939X Codec driver"); 3696 MODULE_LICENSE("GPL"); 3697