1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 4 #include <linux/component.h> 5 #include <linux/delay.h> 6 #include <linux/device.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/slab.h> 16 #include <sound/jack.h> 17 #include <sound/pcm_params.h> 18 #include <sound/pcm.h> 19 #include <sound/soc-dapm.h> 20 #include <sound/soc.h> 21 #include <sound/tlv.h> 22 23 #include "wcd-clsh-v2.h" 24 #include "wcd-mbhc-v2.h" 25 #include "wcd937x.h" 26 27 enum { 28 CHIPID_WCD9370 = 0, 29 CHIPID_WCD9375 = 5, 30 }; 31 32 /* Z value defined in milliohm */ 33 #define WCD937X_ZDET_VAL_32 (32000) 34 #define WCD937X_ZDET_VAL_400 (400000) 35 #define WCD937X_ZDET_VAL_1200 (1200000) 36 #define WCD937X_ZDET_VAL_100K (100000000) 37 /* Z floating defined in ohms */ 38 #define WCD937X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 39 #define WCD937X_ZDET_NUM_MEASUREMENTS (900) 40 #define WCD937X_MBHC_GET_C1(c) (((c) & 0xC000) >> 14) 41 #define WCD937X_MBHC_GET_X1(x) ((x) & 0x3FFF) 42 /* Z value compared in milliOhm */ 43 #define WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z) (((z) > 400000) || ((z) < 32000)) 44 #define WCD937X_MBHC_ZDET_CONST (86 * 16384) 45 #define WCD937X_MBHC_MOISTURE_RREF R_24_KOHM 46 #define WCD_MBHC_HS_V_MAX 1600 47 #define EAR_RX_PATH_AUX 1 48 #define WCD937X_MBHC_MAX_BUTTONS 8 49 50 #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 51 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 52 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ 53 SNDRV_PCM_RATE_384000) 54 55 /* Fractional Rates */ 56 #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 57 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) 58 59 #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |\ 60 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 61 62 enum { 63 ALLOW_BUCK_DISABLE, 64 HPH_COMP_DELAY, 65 HPH_PA_DELAY, 66 AMIC2_BCS_ENABLE, 67 }; 68 69 enum { 70 AIF1_PB = 0, 71 AIF1_CAP, 72 NUM_CODEC_DAIS, 73 }; 74 75 struct wcd937x_priv { 76 struct sdw_slave *tx_sdw_dev; 77 struct wcd937x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 78 struct device *txdev; 79 struct device *rxdev; 80 struct device_node *rxnode; 81 struct device_node *txnode; 82 struct regmap *regmap; 83 /* micb setup lock */ 84 struct mutex micb_lock; 85 /* mbhc module */ 86 struct wcd_mbhc *wcd_mbhc; 87 struct wcd_mbhc_config mbhc_cfg; 88 struct wcd_mbhc_intr intr_ids; 89 struct wcd_clsh_ctrl *clsh_info; 90 struct irq_domain *virq; 91 struct regmap_irq_chip *wcd_regmap_irq_chip; 92 struct regmap_irq_chip_data *irq_chip; 93 struct regulator_bulk_data supplies[WCD937X_MAX_BULK_SUPPLY]; 94 struct snd_soc_jack *jack; 95 unsigned long status_mask; 96 s32 micb_ref[WCD937X_MAX_MICBIAS]; 97 s32 pullup_ref[WCD937X_MAX_MICBIAS]; 98 u32 hph_mode; 99 int ear_rx_path; 100 u32 micb1_mv; 101 u32 micb2_mv; 102 u32 micb3_mv; 103 int hphr_pdm_wd_int; 104 int hphl_pdm_wd_int; 105 int aux_pdm_wd_int; 106 bool comp1_enable; 107 bool comp2_enable; 108 109 struct gpio_desc *us_euro_gpio; 110 struct gpio_desc *reset_gpio; 111 112 atomic_t rx_clk_cnt; 113 atomic_t ana_clk_count; 114 }; 115 116 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 117 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 118 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 119 120 struct wcd937x_mbhc_zdet_param { 121 u16 ldo_ctl; 122 u16 noff; 123 u16 nshift; 124 u16 btn5; 125 u16 btn6; 126 u16 btn7; 127 }; 128 129 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 130 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD937X_ANA_MBHC_MECH, 0x80), 131 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD937X_ANA_MBHC_MECH, 0x40), 132 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD937X_ANA_MBHC_MECH, 0x20), 133 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 134 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD937X_ANA_MBHC_ELECT, 0x08), 135 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 136 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD937X_ANA_MBHC_MECH, 0x04), 137 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x10), 138 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x08), 139 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD937X_ANA_MBHC_MECH, 0x01), 140 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD937X_ANA_MBHC_ELECT, 0x06), 141 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD937X_ANA_MBHC_ELECT, 0x80), 142 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 143 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD937X_MBHC_NEW_CTL_1, 0x03), 144 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD937X_MBHC_NEW_CTL_2, 0x03), 145 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x08), 146 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD937X_ANA_MBHC_RESULT_3, 0x10), 147 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x20), 148 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x80), 149 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x40), 150 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD937X_HPH_OCP_CTL, 0x10), 151 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x07), 152 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD937X_ANA_MBHC_ELECT, 0x70), 153 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0xFF), 154 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD937X_ANA_MICB2, 0xC0), 155 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD937X_HPH_CNP_WG_TIME, 0xFF), 156 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD937X_ANA_HPH, 0x40), 157 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD937X_ANA_HPH, 0x80), 158 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD937X_ANA_HPH, 0xC0), 159 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD937X_ANA_MBHC_RESULT_3, 0x10), 160 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD937X_MBHC_CTL_BCS, 0x02), 161 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x01), 162 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD937X_MBHC_NEW_CTL_2, 0x70), 163 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x20), 164 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD937X_HPH_PA_CTL2, 0x40), 165 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD937X_HPH_PA_CTL2, 0x10), 166 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD937X_HPH_L_TEST, 0x01), 167 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD937X_HPH_R_TEST, 0x01), 168 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x80), 169 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x20), 170 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD937X_MBHC_NEW_CTL_1, 0x08), 171 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD937X_MBHC_NEW_FSM_STATUS, 0x40), 172 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD937X_MBHC_NEW_FSM_STATUS, 0x80), 173 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD937X_MBHC_NEW_ADC_RESULT, 0xFF), 174 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD937X_ANA_MICB2, 0x3F), 175 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD937X_MBHC_NEW_CTL_1, 0x10), 176 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD937X_MBHC_NEW_CTL_1, 0x04), 177 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD937X_ANA_MBHC_ZDET, 0x02), 178 }; 179 180 static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = { 181 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, BIT(0)), 182 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, BIT(1)), 183 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, BIT(2)), 184 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, BIT(3)), 185 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, BIT(4)), 186 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, BIT(5)), 187 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, BIT(6)), 188 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, BIT(7)), 189 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, BIT(0)), 190 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, BIT(1)), 191 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, BIT(2)), 192 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, BIT(3)), 193 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, BIT(4)), 194 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, BIT(5)), 195 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, BIT(6)), 196 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, BIT(7)), 197 REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, BIT(0)), 198 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, BIT(1)), 199 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, BIT(2)), 200 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, BIT(3)), 201 }; 202 203 static int wcd937x_handle_post_irq(void *data) 204 { 205 struct wcd937x_priv *wcd937x; 206 207 if (data) 208 wcd937x = (struct wcd937x_priv *)data; 209 else 210 return IRQ_HANDLED; 211 212 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_0, 0); 213 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_1, 0); 214 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_2, 0); 215 216 return IRQ_HANDLED; 217 } 218 219 static const u32 wcd937x_config_regs[] = { 220 WCD937X_DIGITAL_INTR_LEVEL_0, 221 }; 222 223 static const struct regmap_irq_chip wcd937x_regmap_irq_chip = { 224 .name = "wcd937x", 225 .irqs = wcd937x_irqs, 226 .num_irqs = ARRAY_SIZE(wcd937x_irqs), 227 .num_regs = 3, 228 .status_base = WCD937X_DIGITAL_INTR_STATUS_0, 229 .mask_base = WCD937X_DIGITAL_INTR_MASK_0, 230 .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0, 231 .use_ack = 1, 232 .clear_ack = 1, 233 .config_base = wcd937x_config_regs, 234 .num_config_bases = ARRAY_SIZE(wcd937x_config_regs), 235 .num_config_regs = 1, 236 .runtime_pm = true, 237 .handle_post_irq = wcd937x_handle_post_irq, 238 .irq_drv_data = NULL, 239 }; 240 241 static void wcd937x_reset(struct wcd937x_priv *wcd937x) 242 { 243 gpiod_set_value(wcd937x->reset_gpio, 1); 244 usleep_range(20, 30); 245 gpiod_set_value(wcd937x->reset_gpio, 0); 246 usleep_range(20, 30); 247 } 248 249 static void wcd937x_io_init(struct regmap *regmap) 250 { 251 u32 val = 0, temp = 0, temp1 = 0; 252 253 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_29, &val); 254 255 val = val & 0x0F; 256 257 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &temp); 258 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_17, &temp1); 259 260 if (temp == 0x02 || temp1 > 0x09) 261 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0E, val); 262 else 263 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0e, 0x0e); 264 265 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x80, 0x80); 266 usleep_range(1000, 1010); 267 268 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x40, 0x40); 269 usleep_range(1000, 1010); 270 271 regmap_update_bits(regmap, WCD937X_LDORXTX_CONFIG, BIT(4), 0x00); 272 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xf0, BIT(7)); 273 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(7), BIT(7)); 274 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), BIT(6)); 275 usleep_range(10000, 10010); 276 277 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), 0x00); 278 regmap_update_bits(regmap, WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xff, 0xd9); 279 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_1, 0xff, 0xfa); 280 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_1, 0xff, 0xfa); 281 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_1, 0xff, 0xfa); 282 283 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_2, 0x38, 0x00); 284 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_2, 0x38, 0x00); 285 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_2, 0x38, 0x00); 286 287 /* Set Bandgap Fine Adjustment to +5mV for Tanggu SMIC part */ 288 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &val); 289 if (val == 0x01) { 290 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); 291 } else if (val == 0x02) { 292 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x1F, 0x04); 293 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x1F, 0x04); 294 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); 295 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL, 0xF0, 0x50); 296 } 297 } 298 299 static int wcd937x_rx_clk_enable(struct snd_soc_component *component) 300 { 301 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 302 303 if (atomic_read(&wcd937x->rx_clk_cnt)) 304 return 0; 305 306 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(3), BIT(3)); 307 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), BIT(0)); 308 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), BIT(0)); 309 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX0_CTL, BIT(6), 0x00); 310 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX1_CTL, BIT(6), 0x00); 311 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX2_CTL, BIT(6), 0x00); 312 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), BIT(1)); 313 314 atomic_inc(&wcd937x->rx_clk_cnt); 315 316 return 0; 317 } 318 319 static int wcd937x_rx_clk_disable(struct snd_soc_component *component) 320 { 321 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 322 323 if (!atomic_read(&wcd937x->rx_clk_cnt)) { 324 dev_err(component->dev, "clk already disabled\n"); 325 return 0; 326 } 327 328 atomic_dec(&wcd937x->rx_clk_cnt); 329 330 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), 0x00); 331 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), 0x00); 332 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), 0x00); 333 334 return 0; 335 } 336 337 static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 338 struct snd_kcontrol *kcontrol, 339 int event) 340 { 341 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 342 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 343 int hph_mode = wcd937x->hph_mode; 344 345 switch (event) { 346 case SND_SOC_DAPM_PRE_PMU: 347 wcd937x_rx_clk_enable(component); 348 snd_soc_component_update_bits(component, 349 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 350 BIT(0), BIT(0)); 351 snd_soc_component_update_bits(component, 352 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 353 BIT(2), BIT(2)); 354 snd_soc_component_update_bits(component, 355 WCD937X_HPH_RDAC_CLK_CTL1, 356 BIT(7), 0x00); 357 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 358 break; 359 case SND_SOC_DAPM_POST_PMU: 360 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 361 snd_soc_component_update_bits(component, 362 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 363 0x0f, BIT(1)); 364 else if (hph_mode == CLS_H_LOHIFI) 365 snd_soc_component_update_bits(component, 366 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 367 0x0f, 0x06); 368 369 if (wcd937x->comp1_enable) { 370 snd_soc_component_update_bits(component, 371 WCD937X_DIGITAL_CDC_COMP_CTL_0, 372 BIT(1), BIT(1)); 373 snd_soc_component_update_bits(component, 374 WCD937X_HPH_L_EN, 375 BIT(5), 0x00); 376 377 if (wcd937x->comp2_enable) { 378 snd_soc_component_update_bits(component, 379 WCD937X_DIGITAL_CDC_COMP_CTL_0, 380 BIT(0), BIT(0)); 381 snd_soc_component_update_bits(component, 382 WCD937X_HPH_R_EN, BIT(5), 0x00); 383 } 384 385 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) { 386 usleep_range(5000, 5110); 387 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 388 } 389 } else { 390 snd_soc_component_update_bits(component, 391 WCD937X_DIGITAL_CDC_COMP_CTL_0, 392 BIT(1), 0x00); 393 snd_soc_component_update_bits(component, 394 WCD937X_HPH_L_EN, 395 BIT(5), BIT(5)); 396 } 397 398 snd_soc_component_update_bits(component, 399 WCD937X_HPH_NEW_INT_HPH_TIMER1, 400 BIT(1), 0x00); 401 break; 402 case SND_SOC_DAPM_POST_PMD: 403 snd_soc_component_update_bits(component, 404 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 405 0x0f, BIT(0)); 406 break; 407 } 408 409 return 0; 410 } 411 412 static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 413 struct snd_kcontrol *kcontrol, 414 int event) 415 { 416 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 417 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 418 int hph_mode = wcd937x->hph_mode; 419 420 switch (event) { 421 case SND_SOC_DAPM_PRE_PMU: 422 wcd937x_rx_clk_enable(component); 423 snd_soc_component_update_bits(component, 424 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(1), BIT(1)); 425 snd_soc_component_update_bits(component, 426 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, BIT(3), BIT(3)); 427 snd_soc_component_update_bits(component, 428 WCD937X_HPH_RDAC_CLK_CTL1, BIT(7), 0x00); 429 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 430 break; 431 case SND_SOC_DAPM_POST_PMU: 432 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 433 snd_soc_component_update_bits(component, 434 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 435 0x0f, BIT(1)); 436 else if (hph_mode == CLS_H_LOHIFI) 437 snd_soc_component_update_bits(component, 438 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 439 0x0f, 0x06); 440 if (wcd937x->comp2_enable) { 441 snd_soc_component_update_bits(component, 442 WCD937X_DIGITAL_CDC_COMP_CTL_0, 443 BIT(0), BIT(0)); 444 snd_soc_component_update_bits(component, 445 WCD937X_HPH_R_EN, BIT(5), 0x00); 446 if (wcd937x->comp1_enable) { 447 snd_soc_component_update_bits(component, 448 WCD937X_DIGITAL_CDC_COMP_CTL_0, 449 BIT(1), BIT(1)); 450 snd_soc_component_update_bits(component, 451 WCD937X_HPH_L_EN, 452 BIT(5), 0x00); 453 } 454 455 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) { 456 usleep_range(5000, 5110); 457 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 458 } 459 } else { 460 snd_soc_component_update_bits(component, 461 WCD937X_DIGITAL_CDC_COMP_CTL_0, 462 BIT(0), 0x00); 463 snd_soc_component_update_bits(component, 464 WCD937X_HPH_R_EN, 465 BIT(5), BIT(5)); 466 } 467 snd_soc_component_update_bits(component, 468 WCD937X_HPH_NEW_INT_HPH_TIMER1, 469 BIT(1), 0x00); 470 break; 471 case SND_SOC_DAPM_POST_PMD: 472 snd_soc_component_update_bits(component, 473 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 474 0x0f, BIT(0)); 475 break; 476 } 477 478 return 0; 479 } 480 481 static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 482 struct snd_kcontrol *kcontrol, 483 int event) 484 { 485 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 486 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 487 int hph_mode = wcd937x->hph_mode; 488 489 switch (event) { 490 case SND_SOC_DAPM_PRE_PMU: 491 wcd937x_rx_clk_enable(component); 492 snd_soc_component_update_bits(component, 493 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 494 BIT(2), BIT(2)); 495 snd_soc_component_update_bits(component, 496 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 497 BIT(0), BIT(0)); 498 499 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 500 snd_soc_component_update_bits(component, 501 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 502 0x0f, BIT(1)); 503 else if (hph_mode == CLS_H_LOHIFI) 504 snd_soc_component_update_bits(component, 505 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 506 0x0f, 0x06); 507 if (wcd937x->comp1_enable) 508 snd_soc_component_update_bits(component, 509 WCD937X_DIGITAL_CDC_COMP_CTL_0, 510 BIT(1), BIT(1)); 511 usleep_range(5000, 5010); 512 513 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, BIT(2), 0x00); 514 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 515 WCD_CLSH_EVENT_PRE_DAC, 516 WCD_CLSH_STATE_EAR, 517 hph_mode); 518 519 break; 520 case SND_SOC_DAPM_POST_PMD: 521 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI || 522 hph_mode == CLS_H_HIFI) 523 snd_soc_component_update_bits(component, 524 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 525 0x0f, BIT(0)); 526 if (wcd937x->comp1_enable) 527 snd_soc_component_update_bits(component, 528 WCD937X_DIGITAL_CDC_COMP_CTL_0, 529 BIT(1), 0x00); 530 break; 531 } 532 533 return 0; 534 } 535 536 static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, 537 struct snd_kcontrol *kcontrol, 538 int event) 539 { 540 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 541 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 542 int hph_mode = wcd937x->hph_mode; 543 544 switch (event) { 545 case SND_SOC_DAPM_PRE_PMU: 546 wcd937x_rx_clk_enable(component); 547 snd_soc_component_update_bits(component, 548 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 549 BIT(2), BIT(2)); 550 snd_soc_component_update_bits(component, 551 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 552 BIT(2), BIT(2)); 553 snd_soc_component_update_bits(component, 554 WCD937X_DIGITAL_CDC_AUX_GAIN_CTL, 555 BIT(0), BIT(0)); 556 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 557 WCD_CLSH_EVENT_PRE_DAC, 558 WCD_CLSH_STATE_AUX, 559 hph_mode); 560 561 break; 562 case SND_SOC_DAPM_POST_PMD: 563 snd_soc_component_update_bits(component, 564 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 565 BIT(2), 0x00); 566 break; 567 } 568 569 return 0; 570 } 571 572 static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 573 struct snd_kcontrol *kcontrol, 574 int event) 575 { 576 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 577 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 578 int hph_mode = wcd937x->hph_mode; 579 580 switch (event) { 581 case SND_SOC_DAPM_PRE_PMU: 582 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 583 WCD_CLSH_EVENT_PRE_DAC, 584 WCD_CLSH_STATE_HPHR, 585 hph_mode); 586 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 587 BIT(4), BIT(4)); 588 usleep_range(100, 110); 589 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 590 snd_soc_component_update_bits(component, 591 WCD937X_DIGITAL_PDM_WD_CTL1, 592 0x07, 0x03); 593 break; 594 case SND_SOC_DAPM_POST_PMU: 595 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 596 if (wcd937x->comp2_enable) 597 usleep_range(7000, 7100); 598 else 599 usleep_range(20000, 20100); 600 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 601 } 602 603 snd_soc_component_update_bits(component, 604 WCD937X_HPH_NEW_INT_HPH_TIMER1, 605 BIT(1), BIT(1)); 606 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 607 snd_soc_component_update_bits(component, 608 WCD937X_ANA_RX_SUPPLIES, 609 BIT(1), BIT(1)); 610 enable_irq(wcd937x->hphr_pdm_wd_int); 611 break; 612 case SND_SOC_DAPM_PRE_PMD: 613 disable_irq_nosync(wcd937x->hphr_pdm_wd_int); 614 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 615 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHR_PA_OFF); 616 break; 617 case SND_SOC_DAPM_POST_PMD: 618 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 619 if (wcd937x->comp2_enable) 620 usleep_range(7000, 7100); 621 else 622 usleep_range(20000, 20100); 623 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 624 } 625 626 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHR_PA_OFF); 627 snd_soc_component_update_bits(component, 628 WCD937X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00); 629 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 630 BIT(4), 0x00); 631 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 632 WCD_CLSH_EVENT_POST_PA, 633 WCD_CLSH_STATE_HPHR, 634 hph_mode); 635 break; 636 } 637 638 return 0; 639 } 640 641 static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 642 struct snd_kcontrol *kcontrol, 643 int event) 644 { 645 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 646 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 647 int hph_mode = wcd937x->hph_mode; 648 649 switch (event) { 650 case SND_SOC_DAPM_PRE_PMU: 651 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 652 WCD_CLSH_EVENT_PRE_DAC, 653 WCD_CLSH_STATE_HPHL, 654 hph_mode); 655 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 656 BIT(5), BIT(5)); 657 usleep_range(100, 110); 658 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 659 snd_soc_component_update_bits(component, 660 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03); 661 break; 662 case SND_SOC_DAPM_POST_PMU: 663 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 664 if (!wcd937x->comp1_enable) 665 usleep_range(20000, 20100); 666 else 667 usleep_range(7000, 7100); 668 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 669 } 670 671 snd_soc_component_update_bits(component, 672 WCD937X_HPH_NEW_INT_HPH_TIMER1, 673 BIT(1), BIT(1)); 674 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 675 snd_soc_component_update_bits(component, 676 WCD937X_ANA_RX_SUPPLIES, 677 BIT(1), BIT(1)); 678 enable_irq(wcd937x->hphl_pdm_wd_int); 679 break; 680 case SND_SOC_DAPM_PRE_PMD: 681 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 682 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 683 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 684 break; 685 case SND_SOC_DAPM_POST_PMD: 686 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 687 if (!wcd937x->comp1_enable) 688 usleep_range(20000, 20100); 689 else 690 usleep_range(7000, 7100); 691 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 692 } 693 694 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 695 snd_soc_component_update_bits(component, 696 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00); 697 snd_soc_component_update_bits(component, 698 WCD937X_ANA_HPH, BIT(5), 0x00); 699 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 700 WCD_CLSH_EVENT_POST_PA, 701 WCD_CLSH_STATE_HPHL, 702 hph_mode); 703 break; 704 } 705 706 return 0; 707 } 708 709 static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, 710 struct snd_kcontrol *kcontrol, 711 int event) 712 { 713 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 714 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 715 int hph_mode = wcd937x->hph_mode; 716 u8 val; 717 718 switch (event) { 719 case SND_SOC_DAPM_PRE_PMU: 720 val = WCD937X_DIGITAL_PDM_WD_CTL2_EN | 721 WCD937X_DIGITAL_PDM_WD_CTL2_TIMEOUT_SEL | 722 WCD937X_DIGITAL_PDM_WD_CTL2_HOLD_OFF; 723 snd_soc_component_update_bits(component, 724 WCD937X_DIGITAL_PDM_WD_CTL2, 725 WCD937X_DIGITAL_PDM_WD_CTL2_MASK, 726 val); 727 break; 728 case SND_SOC_DAPM_POST_PMU: 729 usleep_range(1000, 1010); 730 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 731 snd_soc_component_update_bits(component, 732 WCD937X_ANA_RX_SUPPLIES, 733 BIT(1), BIT(1)); 734 enable_irq(wcd937x->aux_pdm_wd_int); 735 break; 736 case SND_SOC_DAPM_PRE_PMD: 737 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 738 break; 739 case SND_SOC_DAPM_POST_PMD: 740 usleep_range(2000, 2010); 741 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 742 WCD_CLSH_EVENT_POST_PA, 743 WCD_CLSH_STATE_AUX, 744 hph_mode); 745 snd_soc_component_update_bits(component, 746 WCD937X_DIGITAL_PDM_WD_CTL2, 747 WCD937X_DIGITAL_PDM_WD_CTL2_MASK, 748 0x00); 749 break; 750 } 751 752 return 0; 753 } 754 755 static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 756 struct snd_kcontrol *kcontrol, 757 int event) 758 { 759 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 760 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 761 int hph_mode = wcd937x->hph_mode; 762 763 switch (event) { 764 case SND_SOC_DAPM_PRE_PMU: 765 /* Enable watchdog interrupt for HPHL or AUX depending on mux value */ 766 wcd937x->ear_rx_path = snd_soc_component_read(component, 767 WCD937X_DIGITAL_CDC_EAR_PATH_CTL); 768 769 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 770 snd_soc_component_update_bits(component, 771 WCD937X_DIGITAL_PDM_WD_CTL2, 772 BIT(0), BIT(0)); 773 else 774 snd_soc_component_update_bits(component, 775 WCD937X_DIGITAL_PDM_WD_CTL0, 776 0x07, 0x03); 777 if (!wcd937x->comp1_enable) 778 snd_soc_component_update_bits(component, 779 WCD937X_ANA_EAR_COMPANDER_CTL, 780 BIT(7), BIT(7)); 781 break; 782 case SND_SOC_DAPM_POST_PMU: 783 usleep_range(6000, 6010); 784 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 785 snd_soc_component_update_bits(component, 786 WCD937X_ANA_RX_SUPPLIES, 787 BIT(1), BIT(1)); 788 789 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 790 enable_irq(wcd937x->aux_pdm_wd_int); 791 else 792 enable_irq(wcd937x->hphl_pdm_wd_int); 793 break; 794 case SND_SOC_DAPM_PRE_PMD: 795 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 796 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 797 else 798 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 799 break; 800 case SND_SOC_DAPM_POST_PMD: 801 if (!wcd937x->comp1_enable) 802 snd_soc_component_update_bits(component, 803 WCD937X_ANA_EAR_COMPANDER_CTL, 804 BIT(7), 0x00); 805 usleep_range(7000, 7010); 806 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 807 WCD_CLSH_EVENT_POST_PA, 808 WCD_CLSH_STATE_EAR, 809 hph_mode); 810 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, 811 BIT(2), BIT(2)); 812 813 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 814 snd_soc_component_update_bits(component, 815 WCD937X_DIGITAL_PDM_WD_CTL2, 816 BIT(0), 0x00); 817 else 818 snd_soc_component_update_bits(component, 819 WCD937X_DIGITAL_PDM_WD_CTL0, 820 0x07, 0x00); 821 break; 822 } 823 824 return 0; 825 } 826 827 static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w, 828 struct snd_kcontrol *kcontrol, 829 int event) 830 { 831 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 832 833 if (event == SND_SOC_DAPM_POST_PMD) { 834 wcd937x_rx_clk_disable(component); 835 snd_soc_component_update_bits(component, 836 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 837 BIT(0), 0x00); 838 } 839 840 return 0; 841 } 842 843 static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w, 844 struct snd_kcontrol *kcontrol, int event) 845 { 846 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 847 848 if (event == SND_SOC_DAPM_POST_PMD) { 849 wcd937x_rx_clk_disable(component); 850 snd_soc_component_update_bits(component, 851 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 852 BIT(1), 0x00); 853 } 854 855 return 0; 856 } 857 858 static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w, 859 struct snd_kcontrol *kcontrol, 860 int event) 861 { 862 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 863 864 if (event == SND_SOC_DAPM_POST_PMD) { 865 usleep_range(6000, 6010); 866 wcd937x_rx_clk_disable(component); 867 snd_soc_component_update_bits(component, 868 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 869 BIT(2), 0x00); 870 } 871 872 return 0; 873 } 874 875 static int wcd937x_get_micb_vout_ctl_val(u32 micb_mv) 876 { 877 if (micb_mv < 1000 || micb_mv > 2850) { 878 pr_err("Unsupported micbias voltage (%u mV)\n", micb_mv); 879 return -EINVAL; 880 } 881 882 return (micb_mv - 1000) / 50; 883 } 884 885 static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 886 struct snd_kcontrol *kcontrol, int event) 887 { 888 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 889 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 890 bool use_amic3 = snd_soc_component_read(component, WCD937X_TX_NEW_TX_CH2_SEL) & BIT(7); 891 892 /* Enable BCS for Headset mic */ 893 if (event == SND_SOC_DAPM_PRE_PMU && strnstr(w->name, "ADC", sizeof("ADC"))) 894 if (w->shift == 1 && !use_amic3) 895 set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask); 896 897 return 0; 898 } 899 900 static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w, 901 struct snd_kcontrol *kcontrol, int event) 902 { 903 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 904 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 905 906 switch (event) { 907 case SND_SOC_DAPM_PRE_PMU: 908 atomic_inc(&wcd937x->ana_clk_count); 909 snd_soc_component_update_bits(component, 910 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(7), BIT(7)); 911 snd_soc_component_update_bits(component, 912 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), BIT(3)); 913 snd_soc_component_update_bits(component, 914 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(4), BIT(4)); 915 break; 916 case SND_SOC_DAPM_POST_PMD: 917 if (w->shift == 1 && test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) 918 clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask); 919 920 snd_soc_component_update_bits(component, 921 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), 0x00); 922 break; 923 } 924 925 return 0; 926 } 927 928 static int wcd937x_enable_req(struct snd_soc_dapm_widget *w, 929 struct snd_kcontrol *kcontrol, int event) 930 { 931 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 932 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 933 934 switch (event) { 935 case SND_SOC_DAPM_PRE_PMU: 936 snd_soc_component_update_bits(component, 937 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(1), BIT(1)); 938 snd_soc_component_update_bits(component, 939 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(0), 0x00); 940 snd_soc_component_update_bits(component, 941 WCD937X_ANA_TX_CH2, BIT(6), BIT(6)); 942 snd_soc_component_update_bits(component, 943 WCD937X_ANA_TX_CH3_HPF, BIT(6), BIT(6)); 944 snd_soc_component_update_bits(component, 945 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70); 946 snd_soc_component_update_bits(component, 947 WCD937X_ANA_TX_CH1, BIT(7), BIT(7)); 948 snd_soc_component_update_bits(component, 949 WCD937X_ANA_TX_CH2, BIT(6), 0x00); 950 snd_soc_component_update_bits(component, 951 WCD937X_ANA_TX_CH2, BIT(7), BIT(7)); 952 snd_soc_component_update_bits(component, 953 WCD937X_ANA_TX_CH3, BIT(7), BIT(7)); 954 break; 955 case SND_SOC_DAPM_POST_PMD: 956 snd_soc_component_update_bits(component, 957 WCD937X_ANA_TX_CH1, BIT(7), 0x00); 958 snd_soc_component_update_bits(component, 959 WCD937X_ANA_TX_CH2, BIT(7), 0x00); 960 snd_soc_component_update_bits(component, 961 WCD937X_ANA_TX_CH3, BIT(7), 0x00); 962 snd_soc_component_update_bits(component, 963 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(4), 0x00); 964 965 atomic_dec(&wcd937x->ana_clk_count); 966 if (atomic_read(&wcd937x->ana_clk_count) <= 0) { 967 snd_soc_component_update_bits(component, 968 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 969 BIT(4), 0x00); 970 atomic_set(&wcd937x->ana_clk_count, 0); 971 } 972 973 snd_soc_component_update_bits(component, 974 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 975 BIT(7), 0x00); 976 break; 977 } 978 979 return 0; 980 } 981 982 static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 983 struct snd_kcontrol *kcontrol, 984 int event) 985 { 986 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 987 u16 dmic_clk_reg; 988 989 switch (w->shift) { 990 case 0: 991 case 1: 992 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL; 993 break; 994 case 2: 995 case 3: 996 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL; 997 break; 998 case 4: 999 case 5: 1000 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL; 1001 break; 1002 default: 1003 dev_err(component->dev, "Invalid DMIC Selection\n"); 1004 return -EINVAL; 1005 } 1006 1007 switch (event) { 1008 case SND_SOC_DAPM_PRE_PMU: 1009 snd_soc_component_update_bits(component, 1010 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 1011 BIT(7), BIT(7)); 1012 snd_soc_component_update_bits(component, 1013 dmic_clk_reg, 0x07, BIT(1)); 1014 snd_soc_component_update_bits(component, 1015 dmic_clk_reg, BIT(3), BIT(3)); 1016 snd_soc_component_update_bits(component, 1017 dmic_clk_reg, 0x70, BIT(5)); 1018 break; 1019 } 1020 1021 return 0; 1022 } 1023 1024 static int wcd937x_micbias_control(struct snd_soc_component *component, 1025 int micb_num, int req, bool is_dapm) 1026 { 1027 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1028 int micb_index = micb_num - 1; 1029 u16 micb_reg; 1030 1031 if (micb_index < 0 || (micb_index > WCD937X_MAX_MICBIAS - 1)) { 1032 dev_err(component->dev, "Invalid micbias index, micb_ind:%d\n", micb_index); 1033 return -EINVAL; 1034 } 1035 switch (micb_num) { 1036 case MIC_BIAS_1: 1037 micb_reg = WCD937X_ANA_MICB1; 1038 break; 1039 case MIC_BIAS_2: 1040 micb_reg = WCD937X_ANA_MICB2; 1041 break; 1042 case MIC_BIAS_3: 1043 micb_reg = WCD937X_ANA_MICB3; 1044 break; 1045 default: 1046 dev_err(component->dev, "Invalid micbias number: %d\n", micb_num); 1047 return -EINVAL; 1048 } 1049 1050 mutex_lock(&wcd937x->micb_lock); 1051 switch (req) { 1052 case MICB_PULLUP_ENABLE: 1053 wcd937x->pullup_ref[micb_index]++; 1054 if (wcd937x->pullup_ref[micb_index] == 1 && 1055 wcd937x->micb_ref[micb_index] == 0) 1056 snd_soc_component_update_bits(component, micb_reg, 1057 0xc0, BIT(7)); 1058 break; 1059 case MICB_PULLUP_DISABLE: 1060 if (wcd937x->pullup_ref[micb_index] > 0) 1061 wcd937x->pullup_ref[micb_index]++; 1062 if (wcd937x->pullup_ref[micb_index] == 0 && 1063 wcd937x->micb_ref[micb_index] == 0) 1064 snd_soc_component_update_bits(component, micb_reg, 1065 0xc0, 0x00); 1066 break; 1067 case MICB_ENABLE: 1068 wcd937x->micb_ref[micb_index]++; 1069 atomic_inc(&wcd937x->ana_clk_count); 1070 if (wcd937x->micb_ref[micb_index] == 1) { 1071 snd_soc_component_update_bits(component, 1072 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 1073 0xf0, 0xf0); 1074 snd_soc_component_update_bits(component, 1075 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 1076 BIT(4), BIT(4)); 1077 snd_soc_component_update_bits(component, 1078 WCD937X_MICB1_TEST_CTL_2, 1079 BIT(0), BIT(0)); 1080 snd_soc_component_update_bits(component, 1081 WCD937X_MICB2_TEST_CTL_2, 1082 BIT(0), BIT(0)); 1083 snd_soc_component_update_bits(component, 1084 WCD937X_MICB3_TEST_CTL_2, 1085 BIT(0), BIT(0)); 1086 snd_soc_component_update_bits(component, 1087 micb_reg, 0xc0, BIT(6)); 1088 1089 if (micb_num == MIC_BIAS_2) 1090 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1091 WCD_EVENT_POST_MICBIAS_2_ON); 1092 1093 if (micb_num == MIC_BIAS_2 && is_dapm) 1094 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1095 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 1096 } 1097 break; 1098 case MICB_DISABLE: 1099 atomic_dec(&wcd937x->ana_clk_count); 1100 if (wcd937x->micb_ref[micb_index] > 0) 1101 wcd937x->micb_ref[micb_index]--; 1102 if (wcd937x->micb_ref[micb_index] == 0 && 1103 wcd937x->pullup_ref[micb_index] > 0) 1104 snd_soc_component_update_bits(component, micb_reg, 1105 0xc0, BIT(7)); 1106 else if (wcd937x->micb_ref[micb_index] == 0 && 1107 wcd937x->pullup_ref[micb_index] == 0) { 1108 if (micb_num == MIC_BIAS_2) 1109 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1110 WCD_EVENT_PRE_MICBIAS_2_OFF); 1111 1112 snd_soc_component_update_bits(component, micb_reg, 1113 0xc0, 0x00); 1114 if (micb_num == MIC_BIAS_2) 1115 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1116 WCD_EVENT_POST_MICBIAS_2_OFF); 1117 } 1118 1119 if (is_dapm && micb_num == MIC_BIAS_2) 1120 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1121 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 1122 if (atomic_read(&wcd937x->ana_clk_count) <= 0) { 1123 snd_soc_component_update_bits(component, 1124 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 1125 BIT(4), 0x00); 1126 atomic_set(&wcd937x->ana_clk_count, 0); 1127 } 1128 break; 1129 } 1130 mutex_unlock(&wcd937x->micb_lock); 1131 1132 return 0; 1133 } 1134 1135 static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1136 int event) 1137 { 1138 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1139 int micb_num = w->shift; 1140 1141 switch (event) { 1142 case SND_SOC_DAPM_PRE_PMU: 1143 wcd937x_micbias_control(component, micb_num, 1144 MICB_ENABLE, true); 1145 break; 1146 case SND_SOC_DAPM_POST_PMU: 1147 usleep_range(1000, 1100); 1148 break; 1149 case SND_SOC_DAPM_POST_PMD: 1150 wcd937x_micbias_control(component, micb_num, 1151 MICB_DISABLE, true); 1152 break; 1153 } 1154 1155 return 0; 1156 } 1157 1158 static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1159 struct snd_kcontrol *kcontrol, 1160 int event) 1161 { 1162 return __wcd937x_codec_enable_micbias(w, event); 1163 } 1164 1165 static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1166 int event) 1167 { 1168 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1169 int micb_num = w->shift; 1170 1171 switch (event) { 1172 case SND_SOC_DAPM_PRE_PMU: 1173 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_ENABLE, true); 1174 break; 1175 case SND_SOC_DAPM_POST_PMU: 1176 usleep_range(1000, 1100); 1177 break; 1178 case SND_SOC_DAPM_POST_PMD: 1179 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_DISABLE, true); 1180 break; 1181 } 1182 1183 return 0; 1184 } 1185 1186 static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1187 struct snd_kcontrol *kcontrol, 1188 int event) 1189 { 1190 return __wcd937x_codec_enable_micbias_pullup(w, event); 1191 } 1192 1193 static int wcd937x_connect_port(struct wcd937x_sdw_priv *wcd, u8 port_idx, u8 ch_id, bool enable) 1194 { 1195 struct sdw_port_config *port_config = &wcd->port_config[port_idx - 1]; 1196 const struct wcd937x_sdw_ch_info *ch_info = &wcd->ch_info[ch_id]; 1197 u8 port_num = ch_info->port_num; 1198 u8 ch_mask = ch_info->ch_mask; 1199 u8 mstr_port_num, mstr_ch_mask; 1200 struct sdw_slave *sdev = wcd->sdev; 1201 1202 port_config->num = port_num; 1203 1204 mstr_port_num = sdev->m_port_map[port_num]; 1205 mstr_ch_mask = ch_info->master_ch_mask; 1206 1207 if (enable) { 1208 port_config->ch_mask |= ch_mask; 1209 wcd->master_channel_map[mstr_port_num] |= mstr_ch_mask; 1210 } else { 1211 port_config->ch_mask &= ~ch_mask; 1212 wcd->master_channel_map[mstr_port_num] &= ~mstr_ch_mask; 1213 } 1214 1215 return 0; 1216 } 1217 1218 static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 1219 struct snd_ctl_elem_value *ucontrol) 1220 { 1221 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1222 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1223 1224 ucontrol->value.integer.value[0] = wcd937x->hph_mode; 1225 return 0; 1226 } 1227 1228 static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 1229 struct snd_ctl_elem_value *ucontrol) 1230 { 1231 struct snd_soc_component *component = 1232 snd_soc_kcontrol_component(kcontrol); 1233 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1234 u32 mode_val; 1235 1236 mode_val = ucontrol->value.enumerated.item[0]; 1237 1238 if (!mode_val) 1239 mode_val = CLS_AB; 1240 1241 if (mode_val == wcd937x->hph_mode) 1242 return 0; 1243 1244 switch (mode_val) { 1245 case CLS_H_NORMAL: 1246 case CLS_H_HIFI: 1247 case CLS_H_LP: 1248 case CLS_AB: 1249 case CLS_H_LOHIFI: 1250 case CLS_H_ULP: 1251 case CLS_AB_LP: 1252 case CLS_AB_HIFI: 1253 wcd937x->hph_mode = mode_val; 1254 return 1; 1255 } 1256 1257 dev_dbg(component->dev, "%s: Invalid HPH Mode\n", __func__); 1258 return -EINVAL; 1259 } 1260 1261 static int wcd937x_get_compander(struct snd_kcontrol *kcontrol, 1262 struct snd_ctl_elem_value *ucontrol) 1263 { 1264 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1265 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1266 struct soc_mixer_control *mc; 1267 bool hphr; 1268 1269 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1270 hphr = mc->shift; 1271 1272 ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable : 1273 wcd937x->comp1_enable; 1274 return 0; 1275 } 1276 1277 static int wcd937x_set_compander(struct snd_kcontrol *kcontrol, 1278 struct snd_ctl_elem_value *ucontrol) 1279 { 1280 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1281 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1282 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[AIF1_PB]; 1283 int value = ucontrol->value.integer.value[0]; 1284 struct soc_mixer_control *mc; 1285 int portidx; 1286 bool hphr; 1287 1288 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1289 hphr = mc->shift; 1290 1291 if (hphr) { 1292 if (value == wcd937x->comp2_enable) 1293 return 0; 1294 1295 wcd937x->comp2_enable = value; 1296 } else { 1297 if (value == wcd937x->comp1_enable) 1298 return 0; 1299 1300 wcd937x->comp1_enable = value; 1301 } 1302 1303 portidx = wcd->ch_info[mc->reg].port_num; 1304 1305 if (value) 1306 wcd937x_connect_port(wcd, portidx, mc->reg, true); 1307 else 1308 wcd937x_connect_port(wcd, portidx, mc->reg, false); 1309 1310 return 1; 1311 } 1312 1313 static int wcd937x_get_swr_port(struct snd_kcontrol *kcontrol, 1314 struct snd_ctl_elem_value *ucontrol) 1315 { 1316 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1317 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1318 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp); 1319 struct wcd937x_sdw_priv *wcd; 1320 int dai_id = mixer->shift; 1321 int ch_idx = mixer->reg; 1322 int portidx; 1323 1324 wcd = wcd937x->sdw_priv[dai_id]; 1325 portidx = wcd->ch_info[ch_idx].port_num; 1326 1327 ucontrol->value.integer.value[0] = wcd->port_enable[portidx]; 1328 1329 return 0; 1330 } 1331 1332 static int wcd937x_set_swr_port(struct snd_kcontrol *kcontrol, 1333 struct snd_ctl_elem_value *ucontrol) 1334 { 1335 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1336 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1337 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp); 1338 struct wcd937x_sdw_priv *wcd; 1339 int dai_id = mixer->shift; 1340 int ch_idx = mixer->reg; 1341 int portidx; 1342 bool enable; 1343 1344 wcd = wcd937x->sdw_priv[dai_id]; 1345 1346 portidx = wcd->ch_info[ch_idx].port_num; 1347 1348 enable = ucontrol->value.integer.value[0]; 1349 1350 if (enable == wcd->port_enable[portidx]) { 1351 wcd937x_connect_port(wcd, portidx, ch_idx, enable); 1352 return 0; 1353 } 1354 1355 wcd->port_enable[portidx] = enable; 1356 wcd937x_connect_port(wcd, portidx, ch_idx, enable); 1357 1358 return 1; 1359 } 1360 1361 static const char * const rx_hph_mode_mux_text[] = { 1362 "CLS_H_NORMAL", "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", 1363 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_AB_LP", "CLS_AB_HIFI", 1364 }; 1365 1366 static const struct soc_enum rx_hph_mode_mux_enum = 1367 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), rx_hph_mode_mux_text); 1368 1369 /* MBHC related */ 1370 static void wcd937x_mbhc_clk_setup(struct snd_soc_component *component, 1371 bool enable) 1372 { 1373 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_1, 1374 WCD937X_MBHC_CTL_RCO_EN_MASK, enable); 1375 } 1376 1377 static void wcd937x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 1378 bool enable) 1379 { 1380 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_ELECT, 1381 WCD937X_ANA_MBHC_BIAS_EN, enable); 1382 } 1383 1384 static void wcd937x_mbhc_program_btn_thr(struct snd_soc_component *component, 1385 int *btn_low, int *btn_high, 1386 int num_btn, bool is_micbias) 1387 { 1388 int i, vth; 1389 1390 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 1391 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 1392 __func__, num_btn); 1393 return; 1394 } 1395 1396 for (i = 0; i < num_btn; i++) { 1397 vth = ((btn_high[i] * 2) / 25) & 0x3F; 1398 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_BTN0 + i, 1399 WCD937X_MBHC_BTN_VTH_MASK, vth); 1400 } 1401 } 1402 1403 static bool wcd937x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 1404 { 1405 u8 val; 1406 1407 if (micb_num == MIC_BIAS_2) { 1408 val = snd_soc_component_read_field(component, 1409 WCD937X_ANA_MICB2, 1410 WCD937X_ANA_MICB2_ENABLE_MASK); 1411 if (val == WCD937X_MICB_ENABLE) 1412 return true; 1413 } 1414 return false; 1415 } 1416 1417 static void wcd937x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 1418 int pull_up_cur) 1419 { 1420 /* Default pull up current to 2uA */ 1421 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA) 1422 pull_up_cur = HS_PULLUP_I_2P0_UA; 1423 1424 snd_soc_component_write_field(component, 1425 WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 1426 WCD937X_HSDET_PULLUP_C_MASK, pull_up_cur); 1427 } 1428 1429 static int wcd937x_mbhc_request_micbias(struct snd_soc_component *component, 1430 int micb_num, int req) 1431 { 1432 return wcd937x_micbias_control(component, micb_num, req, false); 1433 } 1434 1435 static void wcd937x_mbhc_micb_ramp_control(struct snd_soc_component *component, 1436 bool enable) 1437 { 1438 if (enable) { 1439 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1440 WCD937X_RAMP_SHIFT_CTRL_MASK, 0x0C); 1441 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1442 WCD937X_RAMP_EN_MASK, 1); 1443 } else { 1444 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1445 WCD937X_RAMP_EN_MASK, 0); 1446 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1447 WCD937X_RAMP_SHIFT_CTRL_MASK, 0); 1448 } 1449 } 1450 1451 static int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 1452 int req_volt, int micb_num) 1453 { 1454 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1455 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 1456 1457 switch (micb_num) { 1458 case MIC_BIAS_1: 1459 micb_reg = WCD937X_ANA_MICB1; 1460 break; 1461 case MIC_BIAS_2: 1462 micb_reg = WCD937X_ANA_MICB2; 1463 break; 1464 case MIC_BIAS_3: 1465 micb_reg = WCD937X_ANA_MICB3; 1466 break; 1467 default: 1468 return -EINVAL; 1469 } 1470 mutex_lock(&wcd937x->micb_lock); 1471 /* 1472 * If requested micbias voltage is same as current micbias 1473 * voltage, then just return. Otherwise, adjust voltage as 1474 * per requested value. If micbias is already enabled, then 1475 * to avoid slow micbias ramp-up or down enable pull-up 1476 * momentarily, change the micbias value and then re-enable 1477 * micbias. 1478 */ 1479 micb_en = snd_soc_component_read_field(component, micb_reg, 1480 WCD937X_MICB_EN_MASK); 1481 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 1482 WCD937X_MICB_VOUT_MASK); 1483 1484 req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt); 1485 if (req_vout_ctl < 0) { 1486 ret = -EINVAL; 1487 goto exit; 1488 } 1489 1490 if (cur_vout_ctl == req_vout_ctl) { 1491 ret = 0; 1492 goto exit; 1493 } 1494 1495 if (micb_en == WCD937X_MICB_ENABLE) 1496 snd_soc_component_write_field(component, micb_reg, 1497 WCD937X_MICB_EN_MASK, 1498 WCD937X_MICB_PULL_UP); 1499 1500 snd_soc_component_write_field(component, micb_reg, 1501 WCD937X_MICB_VOUT_MASK, 1502 req_vout_ctl); 1503 1504 if (micb_en == WCD937X_MICB_ENABLE) { 1505 snd_soc_component_write_field(component, micb_reg, 1506 WCD937X_MICB_EN_MASK, 1507 WCD937X_MICB_ENABLE); 1508 /* 1509 * Add 2ms delay as per HW requirement after enabling 1510 * micbias 1511 */ 1512 usleep_range(2000, 2100); 1513 } 1514 exit: 1515 mutex_unlock(&wcd937x->micb_lock); 1516 return ret; 1517 } 1518 1519 static int wcd937x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 1520 int micb_num, bool req_en) 1521 { 1522 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1523 int micb_mv; 1524 1525 if (micb_num != MIC_BIAS_2) 1526 return -EINVAL; 1527 /* 1528 * If device tree micbias level is already above the minimum 1529 * voltage needed to detect threshold microphone, then do 1530 * not change the micbias, just return. 1531 */ 1532 if (wcd937x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 1533 return 0; 1534 1535 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd937x->micb2_mv; 1536 1537 return wcd937x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 1538 } 1539 1540 static void wcd937x_mbhc_get_result_params(struct snd_soc_component *component, 1541 s16 *d1_a, u16 noff, 1542 int32_t *zdet) 1543 { 1544 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1545 int i; 1546 int val, val1; 1547 s16 c1; 1548 s32 x1, d1; 1549 s32 denom; 1550 static const int minCode_param[] = { 1551 3277, 1639, 820, 410, 205, 103, 52, 26 1552 }; 1553 1554 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x20); 1555 for (i = 0; i < WCD937X_ZDET_NUM_MEASUREMENTS; i++) { 1556 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_2, &val); 1557 if (val & 0x80) 1558 break; 1559 } 1560 val = val << 0x8; 1561 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_1, &val1); 1562 val |= val1; 1563 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x00); 1564 x1 = WCD937X_MBHC_GET_X1(val); 1565 c1 = WCD937X_MBHC_GET_C1(val); 1566 /* If ramp is not complete, give additional 5ms */ 1567 if (c1 < 2 && x1) 1568 usleep_range(5000, 5050); 1569 1570 if (!c1 || !x1) { 1571 dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n", 1572 c1, x1); 1573 goto ramp_down; 1574 } 1575 d1 = d1_a[c1]; 1576 denom = (x1 * d1) - (1 << (14 - noff)); 1577 if (denom > 0) 1578 *zdet = (WCD937X_MBHC_ZDET_CONST * 1000) / denom; 1579 else if (x1 < minCode_param[noff]) 1580 *zdet = WCD937X_ZDET_FLOATING_IMPEDANCE; 1581 1582 dev_err(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n", 1583 __func__, d1, c1, x1, *zdet); 1584 ramp_down: 1585 i = 0; 1586 while (x1) { 1587 regmap_read(wcd937x->regmap, 1588 WCD937X_ANA_MBHC_RESULT_1, &val); 1589 regmap_read(wcd937x->regmap, 1590 WCD937X_ANA_MBHC_RESULT_2, &val1); 1591 val = val << 0x08; 1592 val |= val1; 1593 x1 = WCD937X_MBHC_GET_X1(val); 1594 i++; 1595 if (i == WCD937X_ZDET_NUM_MEASUREMENTS) 1596 break; 1597 } 1598 } 1599 1600 static void wcd937x_mbhc_zdet_ramp(struct snd_soc_component *component, 1601 struct wcd937x_mbhc_zdet_param *zdet_param, 1602 s32 *zl, s32 *zr, s16 *d1_a) 1603 { 1604 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1605 s32 zdet = 0; 1606 1607 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, 1608 WCD937X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 1609 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN5, 1610 WCD937X_VTH_MASK, zdet_param->btn5); 1611 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN6, 1612 WCD937X_VTH_MASK, zdet_param->btn6); 1613 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN7, 1614 WCD937X_VTH_MASK, zdet_param->btn7); 1615 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, 1616 WCD937X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 1617 snd_soc_component_update_bits(component, WCD937X_MBHC_NEW_ZDET_RAMP_CTL, 1618 0x0F, zdet_param->nshift); 1619 1620 if (!zl) 1621 goto z_right; 1622 /* Start impedance measurement for HPH_L */ 1623 regmap_update_bits(wcd937x->regmap, 1624 WCD937X_ANA_MBHC_ZDET, 0x80, 0x80); 1625 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 1626 regmap_update_bits(wcd937x->regmap, 1627 WCD937X_ANA_MBHC_ZDET, 0x80, 0x00); 1628 1629 *zl = zdet; 1630 1631 z_right: 1632 if (!zr) 1633 return; 1634 /* Start impedance measurement for HPH_R */ 1635 regmap_update_bits(wcd937x->regmap, 1636 WCD937X_ANA_MBHC_ZDET, 0x40, 0x40); 1637 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 1638 regmap_update_bits(wcd937x->regmap, 1639 WCD937X_ANA_MBHC_ZDET, 0x40, 0x00); 1640 1641 *zr = zdet; 1642 } 1643 1644 static void wcd937x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 1645 s32 *z_val, int flag_l_r) 1646 { 1647 s16 q1; 1648 int q1_cal; 1649 1650 if (*z_val < (WCD937X_ZDET_VAL_400 / 1000)) 1651 q1 = snd_soc_component_read(component, 1652 WCD937X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r)); 1653 else 1654 q1 = snd_soc_component_read(component, 1655 WCD937X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r)); 1656 if (q1 & 0x80) 1657 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 1658 else 1659 q1_cal = (10000 + (q1 * 25)); 1660 if (q1_cal > 0) 1661 *z_val = ((*z_val) * 10000) / q1_cal; 1662 } 1663 1664 static void wcd937x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 1665 u32 *zl, u32 *zr) 1666 { 1667 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1668 s16 reg0, reg1, reg2, reg3, reg4; 1669 s32 z1l, z1r, z1ls; 1670 int zMono, z_diff1, z_diff2; 1671 bool is_fsm_disable = false; 1672 struct wcd937x_mbhc_zdet_param zdet_param[] = { 1673 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 1674 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 1675 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 1676 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 1677 }; 1678 struct wcd937x_mbhc_zdet_param *zdet_param_ptr = NULL; 1679 s16 d1_a[][4] = { 1680 {0, 30, 90, 30}, 1681 {0, 30, 30, 5}, 1682 {0, 30, 30, 5}, 1683 {0, 30, 30, 5}, 1684 }; 1685 s16 *d1 = NULL; 1686 1687 reg0 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN5); 1688 reg1 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN6); 1689 reg2 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN7); 1690 reg3 = snd_soc_component_read(component, WCD937X_MBHC_CTL_CLK); 1691 reg4 = snd_soc_component_read(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL); 1692 1693 if (snd_soc_component_read(component, WCD937X_ANA_MBHC_ELECT) & 0x80) { 1694 is_fsm_disable = true; 1695 regmap_update_bits(wcd937x->regmap, 1696 WCD937X_ANA_MBHC_ELECT, 0x80, 0x00); 1697 } 1698 1699 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 1700 if (wcd937x->mbhc_cfg.hphl_swh) 1701 regmap_update_bits(wcd937x->regmap, 1702 WCD937X_ANA_MBHC_MECH, 0x80, 0x00); 1703 1704 /* Turn off 100k pull down on HPHL */ 1705 regmap_update_bits(wcd937x->regmap, 1706 WCD937X_ANA_MBHC_MECH, 0x01, 0x00); 1707 1708 /* Disable surge protection before impedance detection. 1709 * This is done to give correct value for high impedance. 1710 */ 1711 regmap_update_bits(wcd937x->regmap, 1712 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00); 1713 /* 1ms delay needed after disable surge protection */ 1714 usleep_range(1000, 1010); 1715 1716 /* First get impedance on Left */ 1717 d1 = d1_a[1]; 1718 zdet_param_ptr = &zdet_param[1]; 1719 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1); 1720 1721 if (!WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1l)) 1722 goto left_ch_impedance; 1723 1724 /* Second ramp for left ch */ 1725 if (z1l < WCD937X_ZDET_VAL_32) { 1726 zdet_param_ptr = &zdet_param[0]; 1727 d1 = d1_a[0]; 1728 } else if ((z1l > WCD937X_ZDET_VAL_400) && 1729 (z1l <= WCD937X_ZDET_VAL_1200)) { 1730 zdet_param_ptr = &zdet_param[2]; 1731 d1 = d1_a[2]; 1732 } else if (z1l > WCD937X_ZDET_VAL_1200) { 1733 zdet_param_ptr = &zdet_param[3]; 1734 d1 = d1_a[3]; 1735 } 1736 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1); 1737 1738 left_ch_impedance: 1739 if (z1l == WCD937X_ZDET_FLOATING_IMPEDANCE || 1740 z1l > WCD937X_ZDET_VAL_100K) { 1741 *zl = WCD937X_ZDET_FLOATING_IMPEDANCE; 1742 zdet_param_ptr = &zdet_param[1]; 1743 d1 = d1_a[1]; 1744 } else { 1745 *zl = z1l / 1000; 1746 wcd937x_wcd_mbhc_qfuse_cal(component, zl, 0); 1747 } 1748 1749 /* Start of right impedance ramp and calculation */ 1750 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1); 1751 if (WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1r)) { 1752 if ((z1r > WCD937X_ZDET_VAL_1200 && 1753 zdet_param_ptr->noff == 0x6) || 1754 ((*zl) != WCD937X_ZDET_FLOATING_IMPEDANCE)) 1755 goto right_ch_impedance; 1756 /* Second ramp for right ch */ 1757 if (z1r < WCD937X_ZDET_VAL_32) { 1758 zdet_param_ptr = &zdet_param[0]; 1759 d1 = d1_a[0]; 1760 } else if ((z1r > WCD937X_ZDET_VAL_400) && 1761 (z1r <= WCD937X_ZDET_VAL_1200)) { 1762 zdet_param_ptr = &zdet_param[2]; 1763 d1 = d1_a[2]; 1764 } else if (z1r > WCD937X_ZDET_VAL_1200) { 1765 zdet_param_ptr = &zdet_param[3]; 1766 d1 = d1_a[3]; 1767 } 1768 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1); 1769 } 1770 right_ch_impedance: 1771 if (z1r == WCD937X_ZDET_FLOATING_IMPEDANCE || 1772 z1r > WCD937X_ZDET_VAL_100K) { 1773 *zr = WCD937X_ZDET_FLOATING_IMPEDANCE; 1774 } else { 1775 *zr = z1r / 1000; 1776 wcd937x_wcd_mbhc_qfuse_cal(component, zr, 1); 1777 } 1778 1779 /* Mono/stereo detection */ 1780 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) && 1781 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE)) { 1782 dev_err(component->dev, 1783 "%s: plug type is invalid or extension cable\n", 1784 __func__); 1785 goto zdet_complete; 1786 } 1787 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) || 1788 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE) || 1789 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 1790 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 1791 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO); 1792 goto zdet_complete; 1793 } 1794 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST, 1795 WCD937X_HPHPA_GND_OVR_MASK, 1); 1796 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1797 WCD937X_HPHPA_GND_R_MASK, 1); 1798 if (*zl < (WCD937X_ZDET_VAL_32 / 1000)) 1799 wcd937x_mbhc_zdet_ramp(component, &zdet_param[0], &z1ls, NULL, d1); 1800 else 1801 wcd937x_mbhc_zdet_ramp(component, &zdet_param[1], &z1ls, NULL, d1); 1802 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1803 WCD937X_HPHPA_GND_R_MASK, 0); 1804 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST, 1805 WCD937X_HPHPA_GND_OVR_MASK, 0); 1806 z1ls /= 1000; 1807 wcd937x_wcd_mbhc_qfuse_cal(component, &z1ls, 0); 1808 /* Parallel of left Z and 9 ohm pull down resistor */ 1809 zMono = ((*zl) * 9) / ((*zl) + 9); 1810 z_diff1 = (z1ls > zMono) ? (z1ls - zMono) : (zMono - z1ls); 1811 z_diff2 = ((*zl) > z1ls) ? ((*zl) - z1ls) : (z1ls - (*zl)); 1812 if ((z_diff1 * (*zl + z1ls)) > (z_diff2 * (z1ls + zMono))) 1813 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 1814 else 1815 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO); 1816 1817 /* Enable surge protection again after impedance detection */ 1818 regmap_update_bits(wcd937x->regmap, 1819 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 1820 zdet_complete: 1821 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN5, reg0); 1822 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN6, reg1); 1823 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN7, reg2); 1824 /* Turn on 100k pull down on HPHL */ 1825 regmap_update_bits(wcd937x->regmap, 1826 WCD937X_ANA_MBHC_MECH, 0x01, 0x01); 1827 1828 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 1829 if (wcd937x->mbhc_cfg.hphl_swh) 1830 regmap_update_bits(wcd937x->regmap, 1831 WCD937X_ANA_MBHC_MECH, 0x80, 0x80); 1832 1833 snd_soc_component_write(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, reg4); 1834 snd_soc_component_write(component, WCD937X_MBHC_CTL_CLK, reg3); 1835 if (is_fsm_disable) 1836 regmap_update_bits(wcd937x->regmap, 1837 WCD937X_ANA_MBHC_ELECT, 0x80, 0x80); 1838 } 1839 1840 static void wcd937x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 1841 bool enable) 1842 { 1843 if (enable) { 1844 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1845 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 1); 1846 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1847 WCD937X_MBHC_GND_DET_EN_MASK, 1); 1848 } else { 1849 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1850 WCD937X_MBHC_GND_DET_EN_MASK, 0); 1851 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1852 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 0); 1853 } 1854 } 1855 1856 static void wcd937x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 1857 bool enable) 1858 { 1859 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1860 WCD937X_HPHPA_GND_R_MASK, enable); 1861 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1862 WCD937X_HPHPA_GND_L_MASK, enable); 1863 } 1864 1865 static void wcd937x_mbhc_moisture_config(struct snd_soc_component *component) 1866 { 1867 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1868 1869 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) { 1870 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1871 WCD937X_M_RTH_CTL_MASK, R_OFF); 1872 return; 1873 } 1874 1875 /* Do not enable moisture detection if jack type is NC */ 1876 if (!wcd937x->mbhc_cfg.hphl_swh) { 1877 dev_err(component->dev, "%s: disable moisture detection for NC\n", 1878 __func__); 1879 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1880 WCD937X_M_RTH_CTL_MASK, R_OFF); 1881 return; 1882 } 1883 1884 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1885 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref); 1886 } 1887 1888 static void wcd937x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 1889 { 1890 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1891 1892 if (enable) 1893 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1894 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref); 1895 else 1896 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1897 WCD937X_M_RTH_CTL_MASK, R_OFF); 1898 } 1899 1900 static bool wcd937x_mbhc_get_moisture_status(struct snd_soc_component *component) 1901 { 1902 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1903 bool ret = false; 1904 1905 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) { 1906 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1907 WCD937X_M_RTH_CTL_MASK, R_OFF); 1908 goto done; 1909 } 1910 1911 /* Do not enable moisture detection if jack type is NC */ 1912 if (!wcd937x->mbhc_cfg.hphl_swh) { 1913 dev_err(component->dev, "%s: disable moisture detection for NC\n", 1914 __func__); 1915 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1916 WCD937X_M_RTH_CTL_MASK, R_OFF); 1917 goto done; 1918 } 1919 1920 /* 1921 * If moisture_en is already enabled, then skip to plug type 1922 * detection. 1923 */ 1924 if (snd_soc_component_read_field(component, WCD937X_MBHC_NEW_CTL_2, WCD937X_M_RTH_CTL_MASK)) 1925 goto done; 1926 1927 wcd937x_mbhc_moisture_detect_en(component, true); 1928 /* Read moisture comparator status */ 1929 ret = ((snd_soc_component_read(component, WCD937X_MBHC_NEW_FSM_STATUS) 1930 & 0x20) ? 0 : 1); 1931 done: 1932 return ret; 1933 } 1934 1935 static void wcd937x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 1936 bool enable) 1937 { 1938 snd_soc_component_write_field(component, 1939 WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 1940 WCD937X_MOISTURE_EN_POLLING_MASK, enable); 1941 } 1942 1943 static const struct wcd_mbhc_cb mbhc_cb = { 1944 .clk_setup = wcd937x_mbhc_clk_setup, 1945 .mbhc_bias = wcd937x_mbhc_mbhc_bias_control, 1946 .set_btn_thr = wcd937x_mbhc_program_btn_thr, 1947 .micbias_enable_status = wcd937x_mbhc_micb_en_status, 1948 .hph_pull_up_control_v2 = wcd937x_mbhc_hph_l_pull_up_control, 1949 .mbhc_micbias_control = wcd937x_mbhc_request_micbias, 1950 .mbhc_micb_ramp_control = wcd937x_mbhc_micb_ramp_control, 1951 .mbhc_micb_ctrl_thr_mic = wcd937x_mbhc_micb_ctrl_threshold_mic, 1952 .compute_impedance = wcd937x_wcd_mbhc_calc_impedance, 1953 .mbhc_gnd_det_ctrl = wcd937x_mbhc_gnd_det_ctrl, 1954 .hph_pull_down_ctrl = wcd937x_mbhc_hph_pull_down_ctrl, 1955 .mbhc_moisture_config = wcd937x_mbhc_moisture_config, 1956 .mbhc_get_moisture_status = wcd937x_mbhc_get_moisture_status, 1957 .mbhc_moisture_polling_ctrl = wcd937x_mbhc_moisture_polling_ctrl, 1958 .mbhc_moisture_detect_en = wcd937x_mbhc_moisture_detect_en, 1959 }; 1960 1961 static int wcd937x_get_hph_type(struct snd_kcontrol *kcontrol, 1962 struct snd_ctl_elem_value *ucontrol) 1963 { 1964 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1965 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1966 1967 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd937x->wcd_mbhc); 1968 1969 return 0; 1970 } 1971 1972 static int wcd937x_hph_impedance_get(struct snd_kcontrol *kcontrol, 1973 struct snd_ctl_elem_value *ucontrol) 1974 { 1975 u32 zl, zr; 1976 bool hphr; 1977 struct soc_mixer_control *mc; 1978 struct snd_soc_component *component = 1979 snd_soc_kcontrol_component(kcontrol); 1980 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1981 1982 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1983 hphr = mc->shift; 1984 wcd_mbhc_get_impedance(wcd937x->wcd_mbhc, &zl, &zr); 1985 ucontrol->value.integer.value[0] = hphr ? zr : zl; 1986 1987 return 0; 1988 } 1989 1990 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 1991 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 1992 wcd937x_get_hph_type, NULL), 1993 }; 1994 1995 static const struct snd_kcontrol_new impedance_detect_controls[] = { 1996 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 1997 wcd937x_hph_impedance_get, NULL), 1998 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 1999 wcd937x_hph_impedance_get, NULL), 2000 }; 2001 2002 static int wcd937x_mbhc_init(struct snd_soc_component *component) 2003 { 2004 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2005 struct wcd_mbhc_intr *intr_ids = &wcd937x->intr_ids; 2006 2007 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2008 WCD937X_IRQ_MBHC_SW_DET); 2009 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2010 WCD937X_IRQ_MBHC_BUTTON_PRESS_DET); 2011 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2012 WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET); 2013 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2014 WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2015 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2016 WCD937X_IRQ_MBHC_ELECT_INS_REM_DET); 2017 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd937x->irq_chip, 2018 WCD937X_IRQ_HPHL_OCP_INT); 2019 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd937x->irq_chip, 2020 WCD937X_IRQ_HPHR_OCP_INT); 2021 2022 wcd937x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2023 if (IS_ERR(wcd937x->wcd_mbhc)) 2024 return PTR_ERR(wcd937x->wcd_mbhc); 2025 2026 snd_soc_add_component_controls(component, impedance_detect_controls, 2027 ARRAY_SIZE(impedance_detect_controls)); 2028 snd_soc_add_component_controls(component, hph_type_detect_controls, 2029 ARRAY_SIZE(hph_type_detect_controls)); 2030 2031 return 0; 2032 } 2033 2034 static void wcd937x_mbhc_deinit(struct snd_soc_component *component) 2035 { 2036 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2037 2038 wcd_mbhc_deinit(wcd937x->wcd_mbhc); 2039 } 2040 2041 /* END MBHC */ 2042 2043 static const struct snd_kcontrol_new wcd937x_snd_controls[] = { 2044 SOC_SINGLE_TLV("EAR_PA Volume", WCD937X_ANA_EAR_COMPANDER_CTL, 2045 2, 0x10, 0, ear_pa_gain), 2046 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2047 wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put), 2048 2049 SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0, 2050 wcd937x_get_compander, wcd937x_set_compander), 2051 SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0, 2052 wcd937x_get_compander, wcd937x_set_compander), 2053 2054 SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain), 2055 SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain), 2056 SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0, analog_gain), 2057 SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0, analog_gain), 2058 SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0, analog_gain), 2059 2060 SOC_SINGLE_EXT("HPHL Switch", WCD937X_HPH_L, 0, 1, 0, 2061 wcd937x_get_swr_port, wcd937x_set_swr_port), 2062 SOC_SINGLE_EXT("HPHR Switch", WCD937X_HPH_R, 0, 1, 0, 2063 wcd937x_get_swr_port, wcd937x_set_swr_port), 2064 SOC_SINGLE_EXT("LO Switch", WCD937X_LO, 0, 1, 0, 2065 wcd937x_get_swr_port, wcd937x_set_swr_port), 2066 2067 SOC_SINGLE_EXT("ADC1 Switch", WCD937X_ADC1, 1, 1, 0, 2068 wcd937x_get_swr_port, wcd937x_set_swr_port), 2069 SOC_SINGLE_EXT("ADC2 Switch", WCD937X_ADC2, 1, 1, 0, 2070 wcd937x_get_swr_port, wcd937x_set_swr_port), 2071 SOC_SINGLE_EXT("ADC3 Switch", WCD937X_ADC3, 1, 1, 0, 2072 wcd937x_get_swr_port, wcd937x_set_swr_port), 2073 SOC_SINGLE_EXT("DMIC0 Switch", WCD937X_DMIC0, 1, 1, 0, 2074 wcd937x_get_swr_port, wcd937x_set_swr_port), 2075 SOC_SINGLE_EXT("DMIC1 Switch", WCD937X_DMIC1, 1, 1, 0, 2076 wcd937x_get_swr_port, wcd937x_set_swr_port), 2077 SOC_SINGLE_EXT("MBHC Switch", WCD937X_MBHC, 1, 1, 0, 2078 wcd937x_get_swr_port, wcd937x_set_swr_port), 2079 SOC_SINGLE_EXT("DMIC2 Switch", WCD937X_DMIC2, 1, 1, 0, 2080 wcd937x_get_swr_port, wcd937x_set_swr_port), 2081 SOC_SINGLE_EXT("DMIC3 Switch", WCD937X_DMIC3, 1, 1, 0, 2082 wcd937x_get_swr_port, wcd937x_set_swr_port), 2083 SOC_SINGLE_EXT("DMIC4 Switch", WCD937X_DMIC4, 1, 1, 0, 2084 wcd937x_get_swr_port, wcd937x_set_swr_port), 2085 SOC_SINGLE_EXT("DMIC5 Switch", WCD937X_DMIC5, 1, 1, 0, 2086 wcd937x_get_swr_port, wcd937x_set_swr_port), 2087 }; 2088 2089 static const struct snd_kcontrol_new adc1_switch[] = { 2090 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2091 }; 2092 2093 static const struct snd_kcontrol_new adc2_switch[] = { 2094 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2095 }; 2096 2097 static const struct snd_kcontrol_new adc3_switch[] = { 2098 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2099 }; 2100 2101 static const struct snd_kcontrol_new dmic1_switch[] = { 2102 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2103 }; 2104 2105 static const struct snd_kcontrol_new dmic2_switch[] = { 2106 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2107 }; 2108 2109 static const struct snd_kcontrol_new dmic3_switch[] = { 2110 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2111 }; 2112 2113 static const struct snd_kcontrol_new dmic4_switch[] = { 2114 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2115 }; 2116 2117 static const struct snd_kcontrol_new dmic5_switch[] = { 2118 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2119 }; 2120 2121 static const struct snd_kcontrol_new dmic6_switch[] = { 2122 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2123 }; 2124 2125 static const struct snd_kcontrol_new ear_rdac_switch[] = { 2126 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2127 }; 2128 2129 static const struct snd_kcontrol_new aux_rdac_switch[] = { 2130 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2131 }; 2132 2133 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 2134 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2135 }; 2136 2137 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 2138 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2139 }; 2140 2141 static const char * const adc2_mux_text[] = { 2142 "INP2", "INP3" 2143 }; 2144 2145 static const char * const rdac3_mux_text[] = { 2146 "RX1", "RX3" 2147 }; 2148 2149 static const struct soc_enum adc2_enum = 2150 SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7, 2151 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 2152 2153 static const struct soc_enum rdac3_enum = 2154 SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0, 2155 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 2156 2157 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 2158 2159 static const struct snd_kcontrol_new rx_rdac3_mux = SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 2160 2161 static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = { 2162 /* Input widgets */ 2163 SND_SOC_DAPM_INPUT("AMIC1"), 2164 SND_SOC_DAPM_INPUT("AMIC2"), 2165 SND_SOC_DAPM_INPUT("AMIC3"), 2166 SND_SOC_DAPM_INPUT("IN1_HPHL"), 2167 SND_SOC_DAPM_INPUT("IN2_HPHR"), 2168 SND_SOC_DAPM_INPUT("IN3_AUX"), 2169 2170 /* TX widgets */ 2171 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 2172 wcd937x_codec_enable_adc, 2173 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2174 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 2175 wcd937x_codec_enable_adc, 2176 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2177 2178 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, 2179 NULL, 0, wcd937x_enable_req, 2180 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2181 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0, 2182 NULL, 0, wcd937x_enable_req, 2183 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2184 2185 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 2186 2187 /* TX mixers */ 2188 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, 2189 adc1_switch, ARRAY_SIZE(adc1_switch), 2190 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2191 SND_SOC_DAPM_POST_PMD), 2192 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0, 2193 adc2_switch, ARRAY_SIZE(adc2_switch), 2194 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2195 SND_SOC_DAPM_POST_PMD), 2196 2197 /* MIC_BIAS widgets */ 2198 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2199 wcd937x_codec_enable_micbias, 2200 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2201 SND_SOC_DAPM_POST_PMD), 2202 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2203 wcd937x_codec_enable_micbias, 2204 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2205 SND_SOC_DAPM_POST_PMD), 2206 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2207 wcd937x_codec_enable_micbias, 2208 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2209 SND_SOC_DAPM_POST_PMD), 2210 2211 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 2212 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 2213 2214 /* RX widgets */ 2215 SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0, 2216 wcd937x_codec_enable_ear_pa, 2217 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2218 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2219 SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0, 2220 wcd937x_codec_enable_aux_pa, 2221 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2222 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2223 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0, 2224 wcd937x_codec_enable_hphl_pa, 2225 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2226 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2227 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0, 2228 wcd937x_codec_enable_hphr_pa, 2229 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2230 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2231 2232 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 2233 wcd937x_codec_hphl_dac_event, 2234 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2235 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2236 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 2237 wcd937x_codec_hphr_dac_event, 2238 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2239 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2240 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 2241 wcd937x_codec_ear_dac_event, 2242 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2243 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2244 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0, 2245 wcd937x_codec_aux_dac_event, 2246 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2247 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2248 2249 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 2250 2251 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, 2252 wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU | 2253 SND_SOC_DAPM_POST_PMD), 2254 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, 2255 wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU | 2256 SND_SOC_DAPM_POST_PMD), 2257 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, 2258 wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU | 2259 SND_SOC_DAPM_POST_PMD), 2260 2261 /* RX mixer widgets*/ 2262 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 2263 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 2264 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0, 2265 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)), 2266 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 2267 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 2268 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 2269 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 2270 2271 /* TX output widgets */ 2272 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 2273 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 2274 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 2275 SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"), 2276 2277 /* RX output widgets */ 2278 SND_SOC_DAPM_OUTPUT("EAR"), 2279 SND_SOC_DAPM_OUTPUT("AUX"), 2280 SND_SOC_DAPM_OUTPUT("HPHL"), 2281 SND_SOC_DAPM_OUTPUT("HPHR"), 2282 2283 /* MIC_BIAS pull up widgets */ 2284 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2285 wcd937x_codec_enable_micbias_pullup, 2286 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2287 SND_SOC_DAPM_POST_PMD), 2288 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2289 wcd937x_codec_enable_micbias_pullup, 2290 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2291 SND_SOC_DAPM_POST_PMD), 2292 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2293 wcd937x_codec_enable_micbias_pullup, 2294 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2295 SND_SOC_DAPM_POST_PMD), 2296 }; 2297 2298 static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = { 2299 /* Input widgets */ 2300 SND_SOC_DAPM_INPUT("AMIC4"), 2301 2302 /* TX widgets */ 2303 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 2304 wcd937x_codec_enable_adc, 2305 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2306 2307 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0, 2308 NULL, 0, wcd937x_enable_req, 2309 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2310 2311 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 2312 wcd937x_codec_enable_dmic, 2313 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2314 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 2315 wcd937x_codec_enable_dmic, 2316 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2317 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 2318 wcd937x_codec_enable_dmic, 2319 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2320 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 2321 wcd937x_codec_enable_dmic, 2322 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2323 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 2324 wcd937x_codec_enable_dmic, 2325 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2326 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 2327 wcd937x_codec_enable_dmic, 2328 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2329 2330 /* TX mixer widgets */ 2331 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 2332 0, dmic1_switch, ARRAY_SIZE(dmic1_switch), 2333 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2334 SND_SOC_DAPM_POST_PMD), 2335 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1, 2336 0, dmic2_switch, ARRAY_SIZE(dmic2_switch), 2337 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2338 SND_SOC_DAPM_POST_PMD), 2339 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2, 2340 0, dmic3_switch, ARRAY_SIZE(dmic3_switch), 2341 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2342 SND_SOC_DAPM_POST_PMD), 2343 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3, 2344 0, dmic4_switch, ARRAY_SIZE(dmic4_switch), 2345 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2346 SND_SOC_DAPM_POST_PMD), 2347 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4, 2348 0, dmic5_switch, ARRAY_SIZE(dmic5_switch), 2349 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2350 SND_SOC_DAPM_POST_PMD), 2351 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5, 2352 0, dmic6_switch, ARRAY_SIZE(dmic6_switch), 2353 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2354 SND_SOC_DAPM_POST_PMD), 2355 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch, 2356 ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl, 2357 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2358 2359 /* Output widgets */ 2360 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 2361 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 2362 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 2363 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 2364 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 2365 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 2366 }; 2367 2368 static const struct snd_soc_dapm_route wcd937x_audio_map[] = { 2369 { "ADC1_OUTPUT", NULL, "ADC1_MIXER" }, 2370 { "ADC1_MIXER", "Switch", "ADC1 REQ" }, 2371 { "ADC1 REQ", NULL, "ADC1" }, 2372 { "ADC1", NULL, "AMIC1" }, 2373 2374 { "ADC2_OUTPUT", NULL, "ADC2_MIXER" }, 2375 { "ADC2_MIXER", "Switch", "ADC2 REQ" }, 2376 { "ADC2 REQ", NULL, "ADC2" }, 2377 { "ADC2", NULL, "ADC2 MUX" }, 2378 { "ADC2 MUX", "INP3", "AMIC3" }, 2379 { "ADC2 MUX", "INP2", "AMIC2" }, 2380 2381 { "IN1_HPHL", NULL, "VDD_BUCK" }, 2382 { "IN1_HPHL", NULL, "CLS_H_PORT" }, 2383 { "RX1", NULL, "IN1_HPHL" }, 2384 { "RDAC1", NULL, "RX1" }, 2385 { "HPHL_RDAC", "Switch", "RDAC1" }, 2386 { "HPHL PGA", NULL, "HPHL_RDAC" }, 2387 { "HPHL", NULL, "HPHL PGA" }, 2388 2389 { "IN2_HPHR", NULL, "VDD_BUCK" }, 2390 { "IN2_HPHR", NULL, "CLS_H_PORT" }, 2391 { "RX2", NULL, "IN2_HPHR" }, 2392 { "RDAC2", NULL, "RX2" }, 2393 { "HPHR_RDAC", "Switch", "RDAC2" }, 2394 { "HPHR PGA", NULL, "HPHR_RDAC" }, 2395 { "HPHR", NULL, "HPHR PGA" }, 2396 2397 { "IN3_AUX", NULL, "VDD_BUCK" }, 2398 { "IN3_AUX", NULL, "CLS_H_PORT" }, 2399 { "RX3", NULL, "IN3_AUX" }, 2400 { "RDAC4", NULL, "RX3" }, 2401 { "AUX_RDAC", "Switch", "RDAC4" }, 2402 { "AUX PGA", NULL, "AUX_RDAC" }, 2403 { "AUX", NULL, "AUX PGA" }, 2404 2405 { "RDAC3_MUX", "RX3", "RX3" }, 2406 { "RDAC3_MUX", "RX1", "RX1" }, 2407 { "RDAC3", NULL, "RDAC3_MUX" }, 2408 { "EAR_RDAC", "Switch", "RDAC3" }, 2409 { "EAR PGA", NULL, "EAR_RDAC" }, 2410 { "EAR", NULL, "EAR PGA" }, 2411 }; 2412 2413 static const struct snd_soc_dapm_route wcd9375_audio_map[] = { 2414 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }, 2415 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }, 2416 { "ADC3_MIXER", "Switch", "ADC3 REQ" }, 2417 { "ADC3 REQ", NULL, "ADC3" }, 2418 { "ADC3", NULL, "AMIC4" }, 2419 2420 { "DMIC1_OUTPUT", NULL, "DMIC1_MIXER" }, 2421 { "DMIC1_MIXER", "Switch", "DMIC1" }, 2422 2423 { "DMIC2_OUTPUT", NULL, "DMIC2_MIXER" }, 2424 { "DMIC2_MIXER", "Switch", "DMIC2" }, 2425 2426 { "DMIC3_OUTPUT", NULL, "DMIC3_MIXER" }, 2427 { "DMIC3_MIXER", "Switch", "DMIC3" }, 2428 2429 { "DMIC4_OUTPUT", NULL, "DMIC4_MIXER" }, 2430 { "DMIC4_MIXER", "Switch", "DMIC4" }, 2431 2432 { "DMIC5_OUTPUT", NULL, "DMIC5_MIXER" }, 2433 { "DMIC5_MIXER", "Switch", "DMIC5" }, 2434 2435 { "DMIC6_OUTPUT", NULL, "DMIC6_MIXER" }, 2436 { "DMIC6_MIXER", "Switch", "DMIC6" }, 2437 }; 2438 2439 static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x) 2440 { 2441 int vout_ctl[3]; 2442 2443 /* Set micbias voltage */ 2444 vout_ctl[0] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb1_mv); 2445 vout_ctl[1] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb2_mv); 2446 vout_ctl[2] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb3_mv); 2447 if ((vout_ctl[0] | vout_ctl[1] | vout_ctl[2]) < 0) 2448 return -EINVAL; 2449 2450 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, WCD937X_ANA_MICB_VOUT, vout_ctl[0]); 2451 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, WCD937X_ANA_MICB_VOUT, vout_ctl[1]); 2452 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, WCD937X_ANA_MICB_VOUT, vout_ctl[2]); 2453 2454 return 0; 2455 } 2456 2457 static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data) 2458 { 2459 return IRQ_HANDLED; 2460 } 2461 2462 static const struct irq_chip wcd_irq_chip = { 2463 .name = "WCD937x", 2464 }; 2465 2466 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 2467 irq_hw_number_t hw) 2468 { 2469 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 2470 irq_set_nested_thread(virq, 1); 2471 irq_set_noprobe(virq); 2472 2473 return 0; 2474 } 2475 2476 static const struct irq_domain_ops wcd_domain_ops = { 2477 .map = wcd_irq_chip_map, 2478 }; 2479 2480 static int wcd937x_irq_init(struct wcd937x_priv *wcd, struct device *dev) 2481 { 2482 wcd->virq = irq_domain_create_linear(NULL, 1, &wcd_domain_ops, NULL); 2483 if (!(wcd->virq)) { 2484 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 2485 return -EINVAL; 2486 } 2487 2488 return devm_regmap_add_irq_chip(dev, wcd->regmap, 2489 irq_create_mapping(wcd->virq, 0), 2490 IRQF_ONESHOT, 0, &wcd937x_regmap_irq_chip, 2491 &wcd->irq_chip); 2492 } 2493 2494 static int wcd937x_soc_codec_probe(struct snd_soc_component *component) 2495 { 2496 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2497 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2498 struct sdw_slave *tx_sdw_dev = wcd937x->tx_sdw_dev; 2499 struct device *dev = component->dev; 2500 unsigned long time_left; 2501 int i, ret; 2502 u32 chipid; 2503 2504 time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete, 2505 msecs_to_jiffies(5000)); 2506 if (!time_left) { 2507 dev_err(dev, "soundwire device init timeout\n"); 2508 return -ETIMEDOUT; 2509 } 2510 2511 snd_soc_component_init_regmap(component, wcd937x->regmap); 2512 ret = pm_runtime_resume_and_get(dev); 2513 if (ret < 0) 2514 return ret; 2515 2516 chipid = (snd_soc_component_read(component, 2517 WCD937X_DIGITAL_EFUSE_REG_0) & 0x1e) >> 1; 2518 if (chipid != CHIPID_WCD9370 && chipid != CHIPID_WCD9375) { 2519 dev_err(dev, "Got unknown chip id: 0x%x\n", chipid); 2520 pm_runtime_put(dev); 2521 return -EINVAL; 2522 } 2523 2524 wcd937x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD937X); 2525 if (IS_ERR(wcd937x->clsh_info)) { 2526 pm_runtime_put(dev); 2527 return PTR_ERR(wcd937x->clsh_info); 2528 } 2529 2530 wcd937x_io_init(wcd937x->regmap); 2531 /* Set all interrupts as edge triggered */ 2532 for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++) 2533 regmap_write(wcd937x->regmap, (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0); 2534 2535 pm_runtime_put(dev); 2536 2537 wcd937x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2538 WCD937X_IRQ_HPHR_PDM_WD_INT); 2539 wcd937x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2540 WCD937X_IRQ_HPHL_PDM_WD_INT); 2541 wcd937x->aux_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2542 WCD937X_IRQ_AUX_PDM_WD_INT); 2543 2544 /* Request for watchdog interrupt */ 2545 ret = devm_request_threaded_irq(dev, wcd937x->hphr_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2546 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2547 "HPHR PDM WDOG INT", wcd937x); 2548 if (ret) 2549 dev_err(dev, "Failed to request HPHR watchdog interrupt (%d)\n", ret); 2550 2551 ret = devm_request_threaded_irq(dev, wcd937x->hphl_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2552 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2553 "HPHL PDM WDOG INT", wcd937x); 2554 if (ret) 2555 dev_err(dev, "Failed to request HPHL watchdog interrupt (%d)\n", ret); 2556 2557 ret = devm_request_threaded_irq(dev, wcd937x->aux_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2558 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2559 "AUX PDM WDOG INT", wcd937x); 2560 if (ret) 2561 dev_err(dev, "Failed to request Aux watchdog interrupt (%d)\n", ret); 2562 2563 /* Disable watchdog interrupt for HPH and AUX */ 2564 disable_irq_nosync(wcd937x->hphr_pdm_wd_int); 2565 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 2566 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 2567 2568 if (chipid == CHIPID_WCD9375) { 2569 ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets, 2570 ARRAY_SIZE(wcd9375_dapm_widgets)); 2571 if (ret < 0) { 2572 dev_err(component->dev, "Failed to add snd_ctls\n"); 2573 wcd_clsh_ctrl_free(wcd937x->clsh_info); 2574 return ret; 2575 } 2576 2577 ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map, 2578 ARRAY_SIZE(wcd9375_audio_map)); 2579 if (ret < 0) { 2580 dev_err(component->dev, "Failed to add routes\n"); 2581 wcd_clsh_ctrl_free(wcd937x->clsh_info); 2582 return ret; 2583 } 2584 } 2585 2586 ret = wcd937x_mbhc_init(component); 2587 if (ret) 2588 dev_err(component->dev, "mbhc initialization failed\n"); 2589 2590 return ret; 2591 } 2592 2593 static void wcd937x_soc_codec_remove(struct snd_soc_component *component) 2594 { 2595 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2596 2597 wcd937x_mbhc_deinit(component); 2598 free_irq(wcd937x->aux_pdm_wd_int, wcd937x); 2599 free_irq(wcd937x->hphl_pdm_wd_int, wcd937x); 2600 free_irq(wcd937x->hphr_pdm_wd_int, wcd937x); 2601 2602 wcd_clsh_ctrl_free(wcd937x->clsh_info); 2603 } 2604 2605 static int wcd937x_codec_set_jack(struct snd_soc_component *comp, 2606 struct snd_soc_jack *jack, void *data) 2607 { 2608 struct wcd937x_priv *wcd = dev_get_drvdata(comp->dev); 2609 int ret = 0; 2610 2611 if (jack) 2612 ret = wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 2613 else 2614 wcd_mbhc_stop(wcd->wcd_mbhc); 2615 2616 return ret; 2617 } 2618 2619 static const struct snd_soc_component_driver soc_codec_dev_wcd937x = { 2620 .name = "wcd937x_codec", 2621 .probe = wcd937x_soc_codec_probe, 2622 .remove = wcd937x_soc_codec_remove, 2623 .controls = wcd937x_snd_controls, 2624 .num_controls = ARRAY_SIZE(wcd937x_snd_controls), 2625 .dapm_widgets = wcd937x_dapm_widgets, 2626 .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets), 2627 .dapm_routes = wcd937x_audio_map, 2628 .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map), 2629 .set_jack = wcd937x_codec_set_jack, 2630 .endianness = 1, 2631 }; 2632 2633 static void wcd937x_dt_parse_micbias_info(struct device *dev, struct wcd937x_priv *wcd) 2634 { 2635 struct device_node *np = dev->of_node; 2636 u32 prop_val = 0; 2637 int ret = 0; 2638 2639 ret = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val); 2640 if (!ret) 2641 wcd->micb1_mv = prop_val / 1000; 2642 else 2643 dev_warn(dev, "Micbias1 DT property not found\n"); 2644 2645 ret = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val); 2646 if (!ret) 2647 wcd->micb2_mv = prop_val / 1000; 2648 else 2649 dev_warn(dev, "Micbias2 DT property not found\n"); 2650 2651 ret = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val); 2652 if (!ret) 2653 wcd->micb3_mv = prop_val / 1000; 2654 else 2655 dev_warn(dev, "Micbias3 DT property not found\n"); 2656 } 2657 2658 static bool wcd937x_swap_gnd_mic(struct snd_soc_component *component) 2659 { 2660 int value; 2661 struct wcd937x_priv *wcd937x; 2662 2663 wcd937x = snd_soc_component_get_drvdata(component); 2664 2665 value = gpiod_get_value(wcd937x->us_euro_gpio); 2666 gpiod_set_value(wcd937x->us_euro_gpio, !value); 2667 2668 return true; 2669 } 2670 2671 static int wcd937x_codec_hw_params(struct snd_pcm_substream *substream, 2672 struct snd_pcm_hw_params *params, 2673 struct snd_soc_dai *dai) 2674 { 2675 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2676 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2677 2678 return wcd937x_sdw_hw_params(wcd, substream, params, dai); 2679 } 2680 2681 static int wcd937x_codec_free(struct snd_pcm_substream *substream, 2682 struct snd_soc_dai *dai) 2683 { 2684 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2685 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2686 2687 return sdw_stream_remove_slave(wcd->sdev, wcd->sruntime); 2688 } 2689 2690 static int wcd937x_codec_set_sdw_stream(struct snd_soc_dai *dai, 2691 void *stream, int direction) 2692 { 2693 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2694 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2695 2696 wcd->sruntime = stream; 2697 2698 return 0; 2699 } 2700 2701 static int wcd937x_get_channel_map(const struct snd_soc_dai *dai, 2702 unsigned int *tx_num, unsigned int *tx_slot, 2703 unsigned int *rx_num, unsigned int *rx_slot) 2704 { 2705 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2706 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2707 int i; 2708 2709 switch (dai->id) { 2710 case AIF1_PB: 2711 if (!rx_slot || !rx_num) { 2712 dev_err(dai->dev, "Invalid rx_slot %p or rx_num %p\n", 2713 rx_slot, rx_num); 2714 return -EINVAL; 2715 } 2716 2717 for (i = 0; i < SDW_MAX_PORTS; i++) 2718 rx_slot[i] = wcd->master_channel_map[i]; 2719 2720 *rx_num = i; 2721 break; 2722 case AIF1_CAP: 2723 if (!tx_slot || !tx_num) { 2724 dev_err(dai->dev, "Invalid tx_slot %p or tx_num %p\n", 2725 tx_slot, tx_num); 2726 return -EINVAL; 2727 } 2728 2729 for (i = 0; i < SDW_MAX_PORTS; i++) 2730 tx_slot[i] = wcd->master_channel_map[i]; 2731 2732 *tx_num = i; 2733 break; 2734 default: 2735 break; 2736 } 2737 2738 return 0; 2739 } 2740 2741 static const struct snd_soc_dai_ops wcd937x_sdw_dai_ops = { 2742 .hw_params = wcd937x_codec_hw_params, 2743 .hw_free = wcd937x_codec_free, 2744 .set_stream = wcd937x_codec_set_sdw_stream, 2745 .get_channel_map = wcd937x_get_channel_map, 2746 }; 2747 2748 static struct snd_soc_dai_driver wcd937x_dais[] = { 2749 [0] = { 2750 .name = "wcd937x-sdw-rx", 2751 .playback = { 2752 .stream_name = "WCD AIF Playback", 2753 .rates = WCD937X_RATES | WCD937X_FRAC_RATES, 2754 .formats = WCD937X_FORMATS, 2755 .rate_min = 8000, 2756 .rate_max = 384000, 2757 .channels_min = 1, 2758 .channels_max = 4, 2759 }, 2760 .ops = &wcd937x_sdw_dai_ops, 2761 }, 2762 [1] = { 2763 .name = "wcd937x-sdw-tx", 2764 .capture = { 2765 .stream_name = "WCD AIF Capture", 2766 .rates = WCD937X_RATES, 2767 .formats = WCD937X_FORMATS, 2768 .rate_min = 8000, 2769 .rate_max = 192000, 2770 .channels_min = 1, 2771 .channels_max = 4, 2772 }, 2773 .ops = &wcd937x_sdw_dai_ops, 2774 }, 2775 }; 2776 2777 static int wcd937x_bind(struct device *dev) 2778 { 2779 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2780 int ret; 2781 2782 /* Give the SDW subdevices some more time to settle */ 2783 usleep_range(5000, 5010); 2784 2785 ret = component_bind_all(dev, wcd937x); 2786 if (ret) { 2787 dev_err(dev, "Slave bind failed, ret = %d\n", ret); 2788 return ret; 2789 } 2790 2791 wcd937x->rxdev = wcd937x_sdw_device_get(wcd937x->rxnode); 2792 if (!wcd937x->rxdev) { 2793 dev_err(dev, "could not find slave with matching of node\n"); 2794 return -EINVAL; 2795 } 2796 2797 wcd937x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd937x->rxdev); 2798 wcd937x->sdw_priv[AIF1_PB]->wcd937x = wcd937x; 2799 2800 wcd937x->txdev = wcd937x_sdw_device_get(wcd937x->txnode); 2801 if (!wcd937x->txdev) { 2802 dev_err(dev, "could not find txslave with matching of node\n"); 2803 return -EINVAL; 2804 } 2805 2806 wcd937x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd937x->txdev); 2807 wcd937x->sdw_priv[AIF1_CAP]->wcd937x = wcd937x; 2808 wcd937x->tx_sdw_dev = dev_to_sdw_dev(wcd937x->txdev); 2809 if (!wcd937x->tx_sdw_dev) { 2810 dev_err(dev, "could not get txslave with matching of dev\n"); 2811 return -EINVAL; 2812 } 2813 2814 /* 2815 * As TX is the main CSR reg interface, which should not be suspended first. 2816 * expicilty add the dependency link 2817 */ 2818 if (!device_link_add(wcd937x->rxdev, wcd937x->txdev, 2819 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2820 dev_err(dev, "Could not devlink TX and RX\n"); 2821 return -EINVAL; 2822 } 2823 2824 if (!device_link_add(dev, wcd937x->txdev, 2825 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2826 dev_err(dev, "Could not devlink WCD and TX\n"); 2827 return -EINVAL; 2828 } 2829 2830 if (!device_link_add(dev, wcd937x->rxdev, 2831 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2832 dev_err(dev, "Could not devlink WCD and RX\n"); 2833 return -EINVAL; 2834 } 2835 2836 wcd937x->regmap = dev_get_regmap(&wcd937x->tx_sdw_dev->dev, NULL); 2837 if (!wcd937x->regmap) { 2838 dev_err(dev, "could not get TX device regmap\n"); 2839 return -EINVAL; 2840 } 2841 2842 ret = wcd937x_irq_init(wcd937x, dev); 2843 if (ret) { 2844 dev_err(dev, "IRQ init failed: %d\n", ret); 2845 return ret; 2846 } 2847 2848 wcd937x->sdw_priv[AIF1_PB]->slave_irq = wcd937x->virq; 2849 wcd937x->sdw_priv[AIF1_CAP]->slave_irq = wcd937x->virq; 2850 2851 ret = wcd937x_set_micbias_data(wcd937x); 2852 if (ret < 0) { 2853 dev_err(dev, "Bad micbias pdata\n"); 2854 return ret; 2855 } 2856 2857 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x, 2858 wcd937x_dais, ARRAY_SIZE(wcd937x_dais)); 2859 if (ret) 2860 dev_err(dev, "Codec registration failed\n"); 2861 2862 return ret; 2863 } 2864 2865 static void wcd937x_unbind(struct device *dev) 2866 { 2867 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2868 2869 snd_soc_unregister_component(dev); 2870 device_link_remove(dev, wcd937x->txdev); 2871 device_link_remove(dev, wcd937x->rxdev); 2872 device_link_remove(wcd937x->rxdev, wcd937x->txdev); 2873 component_unbind_all(dev, wcd937x); 2874 mutex_destroy(&wcd937x->micb_lock); 2875 } 2876 2877 static const struct component_master_ops wcd937x_comp_ops = { 2878 .bind = wcd937x_bind, 2879 .unbind = wcd937x_unbind, 2880 }; 2881 2882 static int wcd937x_add_slave_components(struct wcd937x_priv *wcd937x, 2883 struct device *dev, 2884 struct component_match **matchptr) 2885 { 2886 struct device_node *np = dev->of_node; 2887 2888 wcd937x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 2889 if (!wcd937x->rxnode) { 2890 dev_err(dev, "Couldn't parse phandle to qcom,rx-device!\n"); 2891 return -ENODEV; 2892 } 2893 of_node_get(wcd937x->rxnode); 2894 component_match_add_release(dev, matchptr, component_release_of, 2895 component_compare_of, wcd937x->rxnode); 2896 2897 wcd937x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 2898 if (!wcd937x->txnode) { 2899 dev_err(dev, "Couldn't parse phandle to qcom,tx-device\n"); 2900 return -ENODEV; 2901 } 2902 of_node_get(wcd937x->txnode); 2903 component_match_add_release(dev, matchptr, component_release_of, 2904 component_compare_of, wcd937x->txnode); 2905 2906 return 0; 2907 } 2908 2909 static int wcd937x_probe(struct platform_device *pdev) 2910 { 2911 struct component_match *match = NULL; 2912 struct device *dev = &pdev->dev; 2913 struct wcd937x_priv *wcd937x; 2914 struct wcd_mbhc_config *cfg; 2915 int ret; 2916 2917 wcd937x = devm_kzalloc(dev, sizeof(*wcd937x), GFP_KERNEL); 2918 if (!wcd937x) 2919 return -ENOMEM; 2920 2921 dev_set_drvdata(dev, wcd937x); 2922 mutex_init(&wcd937x->micb_lock); 2923 2924 wcd937x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 2925 if (IS_ERR(wcd937x->reset_gpio)) 2926 return dev_err_probe(dev, PTR_ERR(wcd937x->reset_gpio), 2927 "failed to reset wcd gpio\n"); 2928 2929 wcd937x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", GPIOD_OUT_LOW); 2930 if (IS_ERR(wcd937x->us_euro_gpio)) 2931 return dev_err_probe(dev, PTR_ERR(wcd937x->us_euro_gpio), 2932 "us-euro swap Control GPIO not found\n"); 2933 2934 cfg = &wcd937x->mbhc_cfg; 2935 cfg->swap_gnd_mic = wcd937x_swap_gnd_mic; 2936 2937 wcd937x->supplies[0].supply = "vdd-rxtx"; 2938 wcd937x->supplies[1].supply = "vdd-px"; 2939 wcd937x->supplies[2].supply = "vdd-mic-bias"; 2940 wcd937x->supplies[3].supply = "vdd-buck"; 2941 2942 ret = devm_regulator_bulk_get(dev, WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2943 if (ret) 2944 return dev_err_probe(dev, ret, "Failed to get supplies\n"); 2945 2946 ret = regulator_bulk_enable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2947 if (ret) 2948 return dev_err_probe(dev, ret, "Failed to enable supplies\n"); 2949 2950 wcd937x_dt_parse_micbias_info(dev, wcd937x); 2951 2952 cfg->mbhc_micbias = MIC_BIAS_2; 2953 cfg->anc_micbias = MIC_BIAS_2; 2954 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 2955 cfg->num_btn = WCD937X_MBHC_MAX_BUTTONS; 2956 cfg->micb_mv = wcd937x->micb2_mv; 2957 cfg->linein_th = 5000; 2958 cfg->hs_thr = 1700; 2959 cfg->hph_thr = 50; 2960 2961 wcd_dt_parse_mbhc_data(dev, &wcd937x->mbhc_cfg); 2962 2963 ret = wcd937x_add_slave_components(wcd937x, dev, &match); 2964 if (ret) 2965 goto err_disable_regulators; 2966 2967 wcd937x_reset(wcd937x); 2968 2969 ret = component_master_add_with_match(dev, &wcd937x_comp_ops, match); 2970 if (ret) 2971 goto err_disable_regulators; 2972 2973 pm_runtime_set_autosuspend_delay(dev, 1000); 2974 pm_runtime_use_autosuspend(dev); 2975 pm_runtime_mark_last_busy(dev); 2976 pm_runtime_set_active(dev); 2977 pm_runtime_enable(dev); 2978 pm_runtime_idle(dev); 2979 2980 return 0; 2981 2982 err_disable_regulators: 2983 regulator_bulk_disable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2984 2985 return ret; 2986 } 2987 2988 static void wcd937x_remove(struct platform_device *pdev) 2989 { 2990 struct device *dev = &pdev->dev; 2991 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2992 2993 component_master_del(&pdev->dev, &wcd937x_comp_ops); 2994 2995 pm_runtime_disable(dev); 2996 pm_runtime_set_suspended(dev); 2997 pm_runtime_dont_use_autosuspend(dev); 2998 2999 regulator_bulk_disable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 3000 } 3001 3002 #if defined(CONFIG_OF) 3003 static const struct of_device_id wcd937x_of_match[] = { 3004 { .compatible = "qcom,wcd9370-codec" }, 3005 { .compatible = "qcom,wcd9375-codec" }, 3006 { } 3007 }; 3008 MODULE_DEVICE_TABLE(of, wcd937x_of_match); 3009 #endif 3010 3011 static struct platform_driver wcd937x_codec_driver = { 3012 .probe = wcd937x_probe, 3013 .remove = wcd937x_remove, 3014 .driver = { 3015 .name = "wcd937x_codec", 3016 .of_match_table = of_match_ptr(wcd937x_of_match), 3017 .suppress_bind_attrs = true, 3018 }, 3019 }; 3020 3021 module_platform_driver(wcd937x_codec_driver); 3022 MODULE_DESCRIPTION("WCD937X Codec driver"); 3023 MODULE_LICENSE("GPL"); 3024