1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2019, Linaro Limited 3 4 #include <linux/cleanup.h> 5 #include <linux/clk.h> 6 #include <linux/clk-provider.h> 7 #include <linux/interrupt.h> 8 #include <linux/kernel.h> 9 #include <linux/mfd/wcd934x/registers.h> 10 #include <linux/mfd/wcd934x/wcd934x.h> 11 #include <linux/module.h> 12 #include <linux/mutex.h> 13 #include <linux/of_clk.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/slimbus.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/soc-dapm.h> 22 #include <sound/tlv.h> 23 #include "wcd-clsh-v2.h" 24 #include "wcd-mbhc-v2.h" 25 26 #include <dt-bindings/sound/qcom,wcd934x.h> 27 28 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 29 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 30 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 31 /* Fractional Rates */ 32 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 33 SNDRV_PCM_RATE_176400) 34 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 35 SNDRV_PCM_FMTBIT_S24_LE) 36 37 /* slave port water mark level 38 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) 39 */ 40 #define SLAVE_PORT_WATER_MARK_6BYTES 0 41 #define SLAVE_PORT_WATER_MARK_9BYTES 1 42 #define SLAVE_PORT_WATER_MARK_12BYTES 2 43 #define SLAVE_PORT_WATER_MARK_15BYTES 3 44 #define SLAVE_PORT_WATER_MARK_SHIFT 1 45 #define SLAVE_PORT_ENABLE 1 46 #define SLAVE_PORT_DISABLE 0 47 #define WCD934X_SLIM_WATER_MARK_VAL \ 48 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ 49 (SLAVE_PORT_ENABLE)) 50 51 #define WCD934X_SLIM_NUM_PORT_REG 3 52 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2) 53 #define WCD934X_SLIM_IRQ_OVERFLOW BIT(0) 54 #define WCD934X_SLIM_IRQ_UNDERFLOW BIT(1) 55 #define WCD934X_SLIM_IRQ_PORT_CLOSED BIT(2) 56 57 #define WCD934X_MCLK_CLK_12P288MHZ 12288000 58 #define WCD934X_MCLK_CLK_9P6MHZ 9600000 59 60 /* Only valid for 9.6 MHz mclk */ 61 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000 62 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000 63 64 /* Only valid for 12.288 MHz mclk */ 65 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000 66 67 #define WCD934X_DMIC_CLK_DIV_2 0x0 68 #define WCD934X_DMIC_CLK_DIV_3 0x1 69 #define WCD934X_DMIC_CLK_DIV_4 0x2 70 #define WCD934X_DMIC_CLK_DIV_6 0x3 71 #define WCD934X_DMIC_CLK_DIV_8 0x4 72 #define WCD934X_DMIC_CLK_DIV_16 0x5 73 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02 74 75 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60 76 #define CF_MIN_3DB_4HZ 0x0 77 #define CF_MIN_3DB_75HZ 0x1 78 #define CF_MIN_3DB_150HZ 0x2 79 80 #define WCD934X_RX_START 16 81 #define WCD934X_NUM_INTERPOLATORS 9 82 #define WCD934X_RX_PATH_CTL_OFFSET 20 83 #define WCD934X_MAX_VALID_ADC_MUX 13 84 #define WCD934X_INVALID_ADC_MUX 9 85 86 #define WCD934X_SLIM_RX_CH(p) \ 87 {.port = p + WCD934X_RX_START, .shift = p,} 88 89 #define WCD934X_SLIM_TX_CH(p) \ 90 {.port = p, .shift = p,} 91 92 /* Feature masks to distinguish codec version */ 93 #define DSD_DISABLED_MASK 0 94 #define SLNQ_DISABLED_MASK 1 95 96 #define DSD_DISABLED BIT(DSD_DISABLED_MASK) 97 #define SLNQ_DISABLED BIT(SLNQ_DISABLED_MASK) 98 99 /* As fine version info cannot be retrieved before wcd probe. 100 * Define three coarse versions for possible future use before wcd probe. 101 */ 102 #define WCD_VERSION_WCD9340_1_0 0x400 103 #define WCD_VERSION_WCD9341_1_0 0x410 104 #define WCD_VERSION_WCD9340_1_1 0x401 105 #define WCD_VERSION_WCD9341_1_1 0x411 106 #define WCD934X_AMIC_PWR_LEVEL_LP 0 107 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT 1 108 #define WCD934X_AMIC_PWR_LEVEL_HP 2 109 #define WCD934X_AMIC_PWR_LEVEL_HYBRID 3 110 #define WCD934X_AMIC_PWR_LVL_MASK 0x60 111 #define WCD934X_AMIC_PWR_LVL_SHIFT 0x5 112 113 #define WCD934X_DEC_PWR_LVL_MASK 0x06 114 #define WCD934X_DEC_PWR_LVL_LP 0x02 115 #define WCD934X_DEC_PWR_LVL_HP 0x04 116 #define WCD934X_DEC_PWR_LVL_DF 0x00 117 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF 118 119 #define WCD934X_DEF_MICBIAS_MV 1800 120 #define WCD934X_MAX_MICBIAS_MV 2850 121 122 #define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX) 123 124 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \ 125 { \ 126 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 127 .info = wcd934x_iir_filter_info, \ 128 .get = wcd934x_get_iir_band_audio_mixer, \ 129 .put = wcd934x_put_iir_band_audio_mixer, \ 130 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \ 131 .iir_idx = iidx, \ 132 .band_idx = bidx, \ 133 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \ 134 } \ 135 } 136 137 /* Z value defined in milliohm */ 138 #define WCD934X_ZDET_VAL_32 32000 139 #define WCD934X_ZDET_VAL_400 400000 140 #define WCD934X_ZDET_VAL_1200 1200000 141 #define WCD934X_ZDET_VAL_100K 100000000 142 /* Z floating defined in ohms */ 143 #define WCD934X_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE 144 145 #define WCD934X_ZDET_NUM_MEASUREMENTS 900 146 #define WCD934X_MBHC_GET_C1(c) ((c & 0xC000) >> 14) 147 #define WCD934X_MBHC_GET_X1(x) (x & 0x3FFF) 148 /* Z value compared in milliOhm */ 149 #define WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000)) 150 #define WCD934X_MBHC_ZDET_CONST (86 * 16384) 151 #define WCD934X_MBHC_MOISTURE_RREF R_24_KOHM 152 #define WCD934X_MBHC_MAX_BUTTONS (8) 153 #define WCD_MBHC_HS_V_MAX 1600 154 155 #define WCD934X_INTERPOLATOR_PATH(id) \ 156 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \ 157 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \ 158 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \ 159 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \ 160 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \ 161 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \ 162 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \ 163 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \ 164 {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \ 165 {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \ 166 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \ 167 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \ 168 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \ 169 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \ 170 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \ 171 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \ 172 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \ 173 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \ 174 {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \ 175 {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \ 176 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \ 177 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \ 178 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \ 179 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \ 180 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \ 181 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \ 182 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \ 183 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \ 184 {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \ 185 {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \ 186 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \ 187 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \ 188 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \ 189 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \ 190 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \ 191 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \ 192 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \ 193 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \ 194 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \ 195 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \ 196 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \ 197 {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \ 198 {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \ 199 {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \ 200 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \ 201 {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \ 202 {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \ 203 {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \ 204 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"} 205 206 #define WCD934X_INTERPOLATOR_MIX2(id) \ 207 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \ 208 {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"} 209 210 #define WCD934X_SLIM_RX_AIF_PATH(id) \ 211 {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \ 212 {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \ 213 {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \ 214 {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \ 215 {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"} 216 217 #define WCD934X_ADC_MUX(id) \ 218 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \ 219 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \ 220 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \ 221 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \ 222 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \ 223 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \ 224 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \ 225 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \ 226 {"AMIC MUX" #id, "ADC1", "ADC1"}, \ 227 {"AMIC MUX" #id, "ADC2", "ADC2"}, \ 228 {"AMIC MUX" #id, "ADC3", "ADC3"}, \ 229 {"AMIC MUX" #id, "ADC4", "ADC4"} 230 231 #define WCD934X_IIR_INP_MUX(id) \ 232 {"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \ 233 {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \ 234 {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \ 235 {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \ 236 {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \ 237 {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \ 238 {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \ 239 {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \ 240 {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \ 241 {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \ 242 {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \ 243 {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \ 244 {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \ 245 {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \ 246 {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \ 247 {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \ 248 {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \ 249 {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \ 250 {"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \ 251 {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \ 252 {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \ 253 {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \ 254 {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \ 255 {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \ 256 {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \ 257 {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \ 258 {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \ 259 {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \ 260 {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \ 261 {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \ 262 {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \ 263 {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \ 264 {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \ 265 {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \ 266 {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \ 267 {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \ 268 {"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \ 269 {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \ 270 {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \ 271 {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \ 272 {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \ 273 {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \ 274 {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \ 275 {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \ 276 {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \ 277 {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \ 278 {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \ 279 {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \ 280 {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \ 281 {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \ 282 {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \ 283 {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \ 284 {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \ 285 {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \ 286 {"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \ 287 {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \ 288 {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \ 289 {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \ 290 {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \ 291 {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \ 292 {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \ 293 {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \ 294 {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \ 295 {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \ 296 {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \ 297 {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \ 298 {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \ 299 {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \ 300 {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \ 301 {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \ 302 {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \ 303 {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"} 304 305 #define WCD934X_SLIM_TX_AIF_PATH(id) \ 306 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 307 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 308 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 309 {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"} 310 311 #define WCD934X_MAX_MICBIAS MIC_BIAS_4 312 #define NUM_CODEC_DAIS 9 313 314 enum { 315 SIDO_SOURCE_INTERNAL, 316 SIDO_SOURCE_RCO_BG, 317 }; 318 319 enum { 320 INTERP_EAR = 0, 321 INTERP_HPHL, 322 INTERP_HPHR, 323 INTERP_LO1, 324 INTERP_LO2, 325 INTERP_LO3_NA, /* LO3 not avalible in Tavil */ 326 INTERP_LO4_NA, 327 INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */ 328 INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */ 329 INTERP_MAX, 330 }; 331 332 enum { 333 WCD934X_RX0 = 0, 334 WCD934X_RX1, 335 WCD934X_RX2, 336 WCD934X_RX3, 337 WCD934X_RX4, 338 WCD934X_RX5, 339 WCD934X_RX6, 340 WCD934X_RX7, 341 WCD934X_RX8, 342 WCD934X_RX9, 343 WCD934X_RX10, 344 WCD934X_RX11, 345 WCD934X_RX12, 346 WCD934X_RX_MAX, 347 }; 348 349 enum { 350 WCD934X_TX0 = 0, 351 WCD934X_TX1, 352 WCD934X_TX2, 353 WCD934X_TX3, 354 WCD934X_TX4, 355 WCD934X_TX5, 356 WCD934X_TX6, 357 WCD934X_TX7, 358 WCD934X_TX8, 359 WCD934X_TX9, 360 WCD934X_TX10, 361 WCD934X_TX11, 362 WCD934X_TX12, 363 WCD934X_TX13, 364 WCD934X_TX14, 365 WCD934X_TX15, 366 WCD934X_TX_MAX, 367 }; 368 369 struct wcd934x_slim_ch { 370 u32 ch_num; 371 u16 port; 372 u16 shift; 373 struct list_head list; 374 }; 375 376 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = { 377 WCD934X_SLIM_TX_CH(0), 378 WCD934X_SLIM_TX_CH(1), 379 WCD934X_SLIM_TX_CH(2), 380 WCD934X_SLIM_TX_CH(3), 381 WCD934X_SLIM_TX_CH(4), 382 WCD934X_SLIM_TX_CH(5), 383 WCD934X_SLIM_TX_CH(6), 384 WCD934X_SLIM_TX_CH(7), 385 WCD934X_SLIM_TX_CH(8), 386 WCD934X_SLIM_TX_CH(9), 387 WCD934X_SLIM_TX_CH(10), 388 WCD934X_SLIM_TX_CH(11), 389 WCD934X_SLIM_TX_CH(12), 390 WCD934X_SLIM_TX_CH(13), 391 WCD934X_SLIM_TX_CH(14), 392 WCD934X_SLIM_TX_CH(15), 393 }; 394 395 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = { 396 WCD934X_SLIM_RX_CH(0), /* 16 */ 397 WCD934X_SLIM_RX_CH(1), /* 17 */ 398 WCD934X_SLIM_RX_CH(2), 399 WCD934X_SLIM_RX_CH(3), 400 WCD934X_SLIM_RX_CH(4), 401 WCD934X_SLIM_RX_CH(5), 402 WCD934X_SLIM_RX_CH(6), 403 WCD934X_SLIM_RX_CH(7), 404 WCD934X_SLIM_RX_CH(8), 405 WCD934X_SLIM_RX_CH(9), 406 WCD934X_SLIM_RX_CH(10), 407 WCD934X_SLIM_RX_CH(11), 408 WCD934X_SLIM_RX_CH(12), 409 }; 410 411 /* Codec supports 2 IIR filters */ 412 enum { 413 IIR0 = 0, 414 IIR1, 415 IIR_MAX, 416 }; 417 418 /* Each IIR has 5 Filter Stages */ 419 enum { 420 BAND1 = 0, 421 BAND2, 422 BAND3, 423 BAND4, 424 BAND5, 425 BAND_MAX, 426 }; 427 428 enum { 429 COMPANDER_1, /* HPH_L */ 430 COMPANDER_2, /* HPH_R */ 431 COMPANDER_3, /* LO1_DIFF */ 432 COMPANDER_4, /* LO2_DIFF */ 433 COMPANDER_5, /* LO3_SE - not used in Tavil */ 434 COMPANDER_6, /* LO4_SE - not used in Tavil */ 435 COMPANDER_7, /* SWR SPK CH1 */ 436 COMPANDER_8, /* SWR SPK CH2 */ 437 COMPANDER_MAX, 438 }; 439 440 enum { 441 INTn_1_INP_SEL_ZERO = 0, 442 INTn_1_INP_SEL_DEC0, 443 INTn_1_INP_SEL_DEC1, 444 INTn_1_INP_SEL_IIR0, 445 INTn_1_INP_SEL_IIR1, 446 INTn_1_INP_SEL_RX0, 447 INTn_1_INP_SEL_RX1, 448 INTn_1_INP_SEL_RX2, 449 INTn_1_INP_SEL_RX3, 450 INTn_1_INP_SEL_RX4, 451 INTn_1_INP_SEL_RX5, 452 INTn_1_INP_SEL_RX6, 453 INTn_1_INP_SEL_RX7, 454 }; 455 456 enum { 457 INTn_2_INP_SEL_ZERO = 0, 458 INTn_2_INP_SEL_RX0, 459 INTn_2_INP_SEL_RX1, 460 INTn_2_INP_SEL_RX2, 461 INTn_2_INP_SEL_RX3, 462 INTn_2_INP_SEL_RX4, 463 INTn_2_INP_SEL_RX5, 464 INTn_2_INP_SEL_RX6, 465 INTn_2_INP_SEL_RX7, 466 INTn_2_INP_SEL_PROXIMITY, 467 }; 468 469 struct interp_sample_rate { 470 int sample_rate; 471 int rate_val; 472 }; 473 474 static const struct interp_sample_rate sr_val_tbl[] = { 475 {8000, 0x0}, 476 {16000, 0x1}, 477 {32000, 0x3}, 478 {48000, 0x4}, 479 {96000, 0x5}, 480 {192000, 0x6}, 481 {384000, 0x7}, 482 {44100, 0x9}, 483 {88200, 0xA}, 484 {176400, 0xB}, 485 {352800, 0xC}, 486 }; 487 488 struct wcd934x_mbhc_zdet_param { 489 u16 ldo_ctl; 490 u16 noff; 491 u16 nshift; 492 u16 btn5; 493 u16 btn6; 494 u16 btn7; 495 }; 496 497 struct wcd_slim_codec_dai_data { 498 struct list_head slim_ch_list; 499 struct slim_stream_config sconfig; 500 struct slim_stream_runtime *sruntime; 501 }; 502 503 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = { 504 { 505 .name = "WCD9335-IFC-DEV", 506 .range_min = 0x0, 507 .range_max = 0xffff, 508 .selector_reg = 0x800, 509 .selector_mask = 0xfff, 510 .selector_shift = 0, 511 .window_start = 0x800, 512 .window_len = 0x400, 513 }, 514 }; 515 516 static const struct regmap_config wcd934x_ifc_regmap_config = { 517 .reg_bits = 16, 518 .val_bits = 8, 519 .max_register = 0xffff, 520 .ranges = wcd934x_ifc_ranges, 521 .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges), 522 }; 523 524 struct wcd934x_codec { 525 struct device *dev; 526 struct clk_hw hw; 527 struct clk *extclk; 528 struct regmap *regmap; 529 struct regmap *if_regmap; 530 struct slim_device *sdev; 531 struct slim_device *sidev; 532 struct wcd_clsh_ctrl *clsh_ctrl; 533 struct snd_soc_component *component; 534 struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX]; 535 struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX]; 536 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS]; 537 int rate; 538 u32 version; 539 u32 hph_mode; 540 int num_rx_port; 541 int num_tx_port; 542 u32 tx_port_value[WCD934X_TX_MAX]; 543 u32 rx_port_value[WCD934X_RX_MAX]; 544 int sido_input_src; 545 int dmic_0_1_clk_cnt; 546 int dmic_2_3_clk_cnt; 547 int dmic_4_5_clk_cnt; 548 int dmic_sample_rate; 549 int comp_enabled[COMPANDER_MAX]; 550 int sysclk_users; 551 struct mutex sysclk_mutex; 552 /* mbhc module */ 553 struct wcd_mbhc *mbhc; 554 struct wcd_mbhc_config mbhc_cfg; 555 struct wcd_mbhc_intr intr_ids; 556 bool mbhc_started; 557 struct mutex micb_lock; 558 u32 micb_ref[WCD934X_MAX_MICBIAS]; 559 u32 pullup_ref[WCD934X_MAX_MICBIAS]; 560 u32 micb2_mv; 561 }; 562 563 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw) 564 565 struct wcd_iir_filter_ctl { 566 unsigned int iir_idx; 567 unsigned int band_idx; 568 struct soc_bytes_ext bytes_ext; 569 }; 570 571 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 572 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 573 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 574 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0); 575 576 /* Cutoff frequency for high pass filter */ 577 static const char * const cf_text[] = { 578 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ" 579 }; 580 581 static const char * const rx_cf_text[] = { 582 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ", 583 "CF_NEG_3DB_0P48HZ" 584 }; 585 586 static const char * const rx_hph_mode_mux_text[] = { 587 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB", 588 "Class-H Hi-Fi Low Power" 589 }; 590 591 static const char *const slim_rx_mux_text[] = { 592 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", 593 }; 594 595 static const char * const rx_int0_7_mix_mux_text[] = { 596 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 597 "RX6", "RX7", "PROXIMITY" 598 }; 599 600 static const char * const rx_int_mix_mux_text[] = { 601 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 602 "RX6", "RX7" 603 }; 604 605 static const char * const rx_prim_mix_text[] = { 606 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 607 "RX3", "RX4", "RX5", "RX6", "RX7" 608 }; 609 610 static const char * const rx_sidetone_mix_text[] = { 611 "ZERO", "SRC0", "SRC1", "SRC_SUM" 612 }; 613 614 static const char * const iir_inp_mux_text[] = { 615 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6", 616 "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7" 617 }; 618 619 static const char * const rx_int_dem_inp_mux_text[] = { 620 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 621 }; 622 623 static const char * const rx_int0_1_interp_mux_text[] = { 624 "ZERO", "RX INT0_1 MIX1", 625 }; 626 627 static const char * const rx_int1_1_interp_mux_text[] = { 628 "ZERO", "RX INT1_1 MIX1", 629 }; 630 631 static const char * const rx_int2_1_interp_mux_text[] = { 632 "ZERO", "RX INT2_1 MIX1", 633 }; 634 635 static const char * const rx_int3_1_interp_mux_text[] = { 636 "ZERO", "RX INT3_1 MIX1", 637 }; 638 639 static const char * const rx_int4_1_interp_mux_text[] = { 640 "ZERO", "RX INT4_1 MIX1", 641 }; 642 643 static const char * const rx_int7_1_interp_mux_text[] = { 644 "ZERO", "RX INT7_1 MIX1", 645 }; 646 647 static const char * const rx_int8_1_interp_mux_text[] = { 648 "ZERO", "RX INT8_1 MIX1", 649 }; 650 651 static const char * const rx_int0_2_interp_mux_text[] = { 652 "ZERO", "RX INT0_2 MUX", 653 }; 654 655 static const char * const rx_int1_2_interp_mux_text[] = { 656 "ZERO", "RX INT1_2 MUX", 657 }; 658 659 static const char * const rx_int2_2_interp_mux_text[] = { 660 "ZERO", "RX INT2_2 MUX", 661 }; 662 663 static const char * const rx_int3_2_interp_mux_text[] = { 664 "ZERO", "RX INT3_2 MUX", 665 }; 666 667 static const char * const rx_int4_2_interp_mux_text[] = { 668 "ZERO", "RX INT4_2 MUX", 669 }; 670 671 static const char * const rx_int7_2_interp_mux_text[] = { 672 "ZERO", "RX INT7_2 MUX", 673 }; 674 675 static const char * const rx_int8_2_interp_mux_text[] = { 676 "ZERO", "RX INT8_2 MUX", 677 }; 678 679 static const char * const dmic_mux_text[] = { 680 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5" 681 }; 682 683 static const char * const amic_mux_text[] = { 684 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4" 685 }; 686 687 static const char * const amic4_5_sel_text[] = { 688 "AMIC4", "AMIC5" 689 }; 690 691 static const char * const adc_mux_text[] = { 692 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2" 693 }; 694 695 static const char * const cdc_if_tx0_mux_text[] = { 696 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192" 697 }; 698 699 static const char * const cdc_if_tx1_mux_text[] = { 700 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192" 701 }; 702 703 static const char * const cdc_if_tx2_mux_text[] = { 704 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192" 705 }; 706 707 static const char * const cdc_if_tx3_mux_text[] = { 708 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192" 709 }; 710 711 static const char * const cdc_if_tx4_mux_text[] = { 712 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192" 713 }; 714 715 static const char * const cdc_if_tx5_mux_text[] = { 716 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192" 717 }; 718 719 static const char * const cdc_if_tx6_mux_text[] = { 720 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192" 721 }; 722 723 static const char * const cdc_if_tx7_mux_text[] = { 724 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192" 725 }; 726 727 static const char * const cdc_if_tx8_mux_text[] = { 728 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192" 729 }; 730 731 static const char * const cdc_if_tx9_mux_text[] = { 732 "ZERO", "DEC7", "DEC7_192" 733 }; 734 735 static const char * const cdc_if_tx10_mux_text[] = { 736 "ZERO", "DEC6", "DEC6_192" 737 }; 738 739 static const char * const cdc_if_tx11_mux_text[] = { 740 "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST" 741 }; 742 743 static const char * const cdc_if_tx11_inp1_mux_text[] = { 744 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", 745 "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12" 746 }; 747 748 static const char * const cdc_if_tx13_mux_text[] = { 749 "CDC_DEC_5", "MAD_BRDCST" 750 }; 751 752 static const char * const cdc_if_tx13_inp1_mux_text[] = { 753 "ZERO", "DEC5", "DEC5_192" 754 }; 755 756 static const struct soc_enum cf_dec0_enum = 757 SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text); 758 759 static const struct soc_enum cf_dec1_enum = 760 SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text); 761 762 static const struct soc_enum cf_dec2_enum = 763 SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text); 764 765 static const struct soc_enum cf_dec3_enum = 766 SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text); 767 768 static const struct soc_enum cf_dec4_enum = 769 SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text); 770 771 static const struct soc_enum cf_dec5_enum = 772 SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text); 773 774 static const struct soc_enum cf_dec6_enum = 775 SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text); 776 777 static const struct soc_enum cf_dec7_enum = 778 SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text); 779 780 static const struct soc_enum cf_dec8_enum = 781 SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text); 782 783 static const struct soc_enum cf_int0_1_enum = 784 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text); 785 786 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2, 787 rx_cf_text); 788 789 static const struct soc_enum cf_int1_1_enum = 790 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text); 791 792 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2, 793 rx_cf_text); 794 795 static const struct soc_enum cf_int2_1_enum = 796 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text); 797 798 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2, 799 rx_cf_text); 800 801 static const struct soc_enum cf_int3_1_enum = 802 SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text); 803 804 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2, 805 rx_cf_text); 806 807 static const struct soc_enum cf_int4_1_enum = 808 SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text); 809 810 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2, 811 rx_cf_text); 812 813 static const struct soc_enum cf_int7_1_enum = 814 SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text); 815 816 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2, 817 rx_cf_text); 818 819 static const struct soc_enum cf_int8_1_enum = 820 SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text); 821 822 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2, 823 rx_cf_text); 824 825 static const struct soc_enum rx_hph_mode_mux_enum = 826 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 827 rx_hph_mode_mux_text); 828 829 static const struct soc_enum slim_rx_mux_enum = 830 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text); 831 832 static const struct soc_enum rx_int0_2_mux_chain_enum = 833 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10, 834 rx_int0_7_mix_mux_text); 835 836 static const struct soc_enum rx_int1_2_mux_chain_enum = 837 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9, 838 rx_int_mix_mux_text); 839 840 static const struct soc_enum rx_int2_2_mux_chain_enum = 841 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9, 842 rx_int_mix_mux_text); 843 844 static const struct soc_enum rx_int3_2_mux_chain_enum = 845 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9, 846 rx_int_mix_mux_text); 847 848 static const struct soc_enum rx_int4_2_mux_chain_enum = 849 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9, 850 rx_int_mix_mux_text); 851 852 static const struct soc_enum rx_int7_2_mux_chain_enum = 853 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10, 854 rx_int0_7_mix_mux_text); 855 856 static const struct soc_enum rx_int8_2_mux_chain_enum = 857 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9, 858 rx_int_mix_mux_text); 859 860 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum = 861 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13, 862 rx_prim_mix_text); 863 864 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum = 865 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13, 866 rx_prim_mix_text); 867 868 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum = 869 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13, 870 rx_prim_mix_text); 871 872 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum = 873 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13, 874 rx_prim_mix_text); 875 876 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum = 877 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13, 878 rx_prim_mix_text); 879 880 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum = 881 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13, 882 rx_prim_mix_text); 883 884 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum = 885 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13, 886 rx_prim_mix_text); 887 888 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum = 889 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13, 890 rx_prim_mix_text); 891 892 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum = 893 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13, 894 rx_prim_mix_text); 895 896 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum = 897 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13, 898 rx_prim_mix_text); 899 900 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum = 901 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13, 902 rx_prim_mix_text); 903 904 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum = 905 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13, 906 rx_prim_mix_text); 907 908 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum = 909 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13, 910 rx_prim_mix_text); 911 912 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum = 913 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13, 914 rx_prim_mix_text); 915 916 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum = 917 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13, 918 rx_prim_mix_text); 919 920 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum = 921 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13, 922 rx_prim_mix_text); 923 924 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum = 925 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13, 926 rx_prim_mix_text); 927 928 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum = 929 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13, 930 rx_prim_mix_text); 931 932 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum = 933 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13, 934 rx_prim_mix_text); 935 936 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum = 937 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13, 938 rx_prim_mix_text); 939 940 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum = 941 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13, 942 rx_prim_mix_text); 943 944 static const struct soc_enum rx_int0_mix2_inp_mux_enum = 945 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4, 946 rx_sidetone_mix_text); 947 948 static const struct soc_enum rx_int1_mix2_inp_mux_enum = 949 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4, 950 rx_sidetone_mix_text); 951 952 static const struct soc_enum rx_int2_mix2_inp_mux_enum = 953 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4, 954 rx_sidetone_mix_text); 955 956 static const struct soc_enum rx_int3_mix2_inp_mux_enum = 957 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4, 958 rx_sidetone_mix_text); 959 960 static const struct soc_enum rx_int4_mix2_inp_mux_enum = 961 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4, 962 rx_sidetone_mix_text); 963 964 static const struct soc_enum rx_int7_mix2_inp_mux_enum = 965 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4, 966 rx_sidetone_mix_text); 967 968 static const struct soc_enum iir0_inp0_mux_enum = 969 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0, 970 0, 18, iir_inp_mux_text); 971 972 static const struct soc_enum iir0_inp1_mux_enum = 973 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1, 974 0, 18, iir_inp_mux_text); 975 976 static const struct soc_enum iir0_inp2_mux_enum = 977 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2, 978 0, 18, iir_inp_mux_text); 979 980 static const struct soc_enum iir0_inp3_mux_enum = 981 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3, 982 0, 18, iir_inp_mux_text); 983 984 static const struct soc_enum iir1_inp0_mux_enum = 985 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0, 986 0, 18, iir_inp_mux_text); 987 988 static const struct soc_enum iir1_inp1_mux_enum = 989 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1, 990 0, 18, iir_inp_mux_text); 991 992 static const struct soc_enum iir1_inp2_mux_enum = 993 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2, 994 0, 18, iir_inp_mux_text); 995 996 static const struct soc_enum iir1_inp3_mux_enum = 997 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3, 998 0, 18, iir_inp_mux_text); 999 1000 static const struct soc_enum rx_int0_dem_inp_mux_enum = 1001 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0, 1002 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1003 rx_int_dem_inp_mux_text); 1004 1005 static const struct soc_enum rx_int1_dem_inp_mux_enum = 1006 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0, 1007 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1008 rx_int_dem_inp_mux_text); 1009 1010 static const struct soc_enum rx_int2_dem_inp_mux_enum = 1011 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0, 1012 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1013 rx_int_dem_inp_mux_text); 1014 1015 static const struct soc_enum tx_adc_mux0_enum = 1016 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 1017 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1018 static const struct soc_enum tx_adc_mux1_enum = 1019 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 1020 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1021 static const struct soc_enum tx_adc_mux2_enum = 1022 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 1023 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1024 static const struct soc_enum tx_adc_mux3_enum = 1025 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 1026 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1027 static const struct soc_enum tx_adc_mux4_enum = 1028 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2, 1029 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1030 static const struct soc_enum tx_adc_mux5_enum = 1031 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2, 1032 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1033 static const struct soc_enum tx_adc_mux6_enum = 1034 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2, 1035 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1036 static const struct soc_enum tx_adc_mux7_enum = 1037 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2, 1038 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1039 static const struct soc_enum tx_adc_mux8_enum = 1040 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4, 1041 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1042 1043 static const struct soc_enum rx_int0_1_interp_mux_enum = 1044 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1045 rx_int0_1_interp_mux_text); 1046 1047 static const struct soc_enum rx_int1_1_interp_mux_enum = 1048 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1049 rx_int1_1_interp_mux_text); 1050 1051 static const struct soc_enum rx_int2_1_interp_mux_enum = 1052 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1053 rx_int2_1_interp_mux_text); 1054 1055 static const struct soc_enum rx_int3_1_interp_mux_enum = 1056 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_1_interp_mux_text); 1057 1058 static const struct soc_enum rx_int4_1_interp_mux_enum = 1059 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_1_interp_mux_text); 1060 1061 static const struct soc_enum rx_int7_1_interp_mux_enum = 1062 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_1_interp_mux_text); 1063 1064 static const struct soc_enum rx_int8_1_interp_mux_enum = 1065 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_1_interp_mux_text); 1066 1067 static const struct soc_enum rx_int0_2_interp_mux_enum = 1068 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int0_2_interp_mux_text); 1069 1070 static const struct soc_enum rx_int1_2_interp_mux_enum = 1071 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int1_2_interp_mux_text); 1072 1073 static const struct soc_enum rx_int2_2_interp_mux_enum = 1074 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int2_2_interp_mux_text); 1075 1076 static const struct soc_enum rx_int3_2_interp_mux_enum = 1077 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_2_interp_mux_text); 1078 1079 static const struct soc_enum rx_int4_2_interp_mux_enum = 1080 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_2_interp_mux_text); 1081 1082 static const struct soc_enum rx_int7_2_interp_mux_enum = 1083 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_2_interp_mux_text); 1084 1085 static const struct soc_enum rx_int8_2_interp_mux_enum = 1086 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_2_interp_mux_text); 1087 1088 static const struct soc_enum tx_dmic_mux0_enum = 1089 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7, 1090 dmic_mux_text); 1091 1092 static const struct soc_enum tx_dmic_mux1_enum = 1093 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7, 1094 dmic_mux_text); 1095 1096 static const struct soc_enum tx_dmic_mux2_enum = 1097 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7, 1098 dmic_mux_text); 1099 1100 static const struct soc_enum tx_dmic_mux3_enum = 1101 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7, 1102 dmic_mux_text); 1103 1104 static const struct soc_enum tx_dmic_mux4_enum = 1105 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7, 1106 dmic_mux_text); 1107 1108 static const struct soc_enum tx_dmic_mux5_enum = 1109 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7, 1110 dmic_mux_text); 1111 1112 static const struct soc_enum tx_dmic_mux6_enum = 1113 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7, 1114 dmic_mux_text); 1115 1116 static const struct soc_enum tx_dmic_mux7_enum = 1117 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7, 1118 dmic_mux_text); 1119 1120 static const struct soc_enum tx_dmic_mux8_enum = 1121 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7, 1122 dmic_mux_text); 1123 1124 static const struct soc_enum tx_amic_mux0_enum = 1125 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5, 1126 amic_mux_text); 1127 static const struct soc_enum tx_amic_mux1_enum = 1128 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5, 1129 amic_mux_text); 1130 static const struct soc_enum tx_amic_mux2_enum = 1131 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5, 1132 amic_mux_text); 1133 static const struct soc_enum tx_amic_mux3_enum = 1134 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5, 1135 amic_mux_text); 1136 static const struct soc_enum tx_amic_mux4_enum = 1137 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5, 1138 amic_mux_text); 1139 static const struct soc_enum tx_amic_mux5_enum = 1140 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5, 1141 amic_mux_text); 1142 static const struct soc_enum tx_amic_mux6_enum = 1143 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5, 1144 amic_mux_text); 1145 static const struct soc_enum tx_amic_mux7_enum = 1146 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5, 1147 amic_mux_text); 1148 static const struct soc_enum tx_amic_mux8_enum = 1149 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5, 1150 amic_mux_text); 1151 1152 static const struct soc_enum tx_amic4_5_enum = 1153 SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text); 1154 1155 static const struct soc_enum cdc_if_tx0_mux_enum = 1156 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 1157 ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text); 1158 static const struct soc_enum cdc_if_tx1_mux_enum = 1159 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 1160 ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text); 1161 static const struct soc_enum cdc_if_tx2_mux_enum = 1162 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 1163 ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text); 1164 static const struct soc_enum cdc_if_tx3_mux_enum = 1165 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 1166 ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text); 1167 static const struct soc_enum cdc_if_tx4_mux_enum = 1168 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 1169 ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text); 1170 static const struct soc_enum cdc_if_tx5_mux_enum = 1171 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 1172 ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text); 1173 static const struct soc_enum cdc_if_tx6_mux_enum = 1174 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 1175 ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text); 1176 static const struct soc_enum cdc_if_tx7_mux_enum = 1177 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 1178 ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text); 1179 static const struct soc_enum cdc_if_tx8_mux_enum = 1180 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 1181 ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text); 1182 static const struct soc_enum cdc_if_tx9_mux_enum = 1183 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2, 1184 ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text); 1185 static const struct soc_enum cdc_if_tx10_mux_enum = 1186 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4, 1187 ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text); 1188 static const struct soc_enum cdc_if_tx11_inp1_mux_enum = 1189 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0, 1190 ARRAY_SIZE(cdc_if_tx11_inp1_mux_text), 1191 cdc_if_tx11_inp1_mux_text); 1192 static const struct soc_enum cdc_if_tx11_mux_enum = 1193 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0, 1194 ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text); 1195 static const struct soc_enum cdc_if_tx13_inp1_mux_enum = 1196 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4, 1197 ARRAY_SIZE(cdc_if_tx13_inp1_mux_text), 1198 cdc_if_tx13_inp1_mux_text); 1199 static const struct soc_enum cdc_if_tx13_mux_enum = 1200 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0, 1201 ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text); 1202 1203 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 1204 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD934X_ANA_MBHC_MECH, 0x80), 1205 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD934X_ANA_MBHC_MECH, 0x40), 1206 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD934X_ANA_MBHC_MECH, 0x20), 1207 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 1208 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD934X_ANA_MBHC_ELECT, 0x08), 1209 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0xC0), 1210 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD934X_ANA_MBHC_MECH, 0x04), 1211 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x10), 1212 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x08), 1213 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD934X_ANA_MBHC_MECH, 0x01), 1214 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD934X_ANA_MBHC_ELECT, 0x06), 1215 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD934X_ANA_MBHC_ELECT, 0x80), 1216 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 1217 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD934X_MBHC_NEW_CTL_1, 0x03), 1218 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD934X_MBHC_NEW_CTL_2, 0x03), 1219 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x08), 1220 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD934X_ANA_MBHC_RESULT_3, 0x10), 1221 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x20), 1222 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x80), 1223 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x40), 1224 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD934X_HPH_OCP_CTL, 0x10), 1225 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x07), 1226 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD934X_ANA_MBHC_ELECT, 0x70), 1227 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0xFF), 1228 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD934X_ANA_MICB2, 0xC0), 1229 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD934X_HPH_CNP_WG_TIME, 0xFF), 1230 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD934X_ANA_HPH, 0x40), 1231 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD934X_ANA_HPH, 0x80), 1232 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD934X_ANA_HPH, 0xC0), 1233 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD934X_ANA_MBHC_RESULT_3, 0x10), 1234 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD934X_MBHC_CTL_BCS, 0x02), 1235 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD934X_MBHC_STATUS_SPARE_1, 0x01), 1236 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD934X_MBHC_NEW_CTL_2, 0x70), 1237 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD934X_MBHC_NEW_FSM_STATUS, 0x20), 1238 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD934X_HPH_PA_CTL2, 0x40), 1239 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD934X_HPH_PA_CTL2, 0x10), 1240 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD934X_HPH_L_TEST, 0x01), 1241 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD934X_HPH_R_TEST, 0x01), 1242 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x04), 1243 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x08), 1244 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD934X_MBHC_NEW_CTL_1, 0x08), 1245 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD934X_MBHC_NEW_FSM_STATUS, 0x40), 1246 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD934X_MBHC_NEW_FSM_STATUS, 0x80), 1247 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD934X_MBHC_NEW_ADC_RESULT, 0xFF), 1248 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD934X_ANA_MICB2, 0x3F), 1249 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD934X_MBHC_NEW_CTL_1, 0x10), 1250 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD934X_MBHC_NEW_CTL_1, 0x04), 1251 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD934X_ANA_MBHC_ZDET, 0x02), 1252 }; 1253 1254 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src) 1255 { 1256 if (sido_src == wcd->sido_input_src) 1257 return 0; 1258 1259 if (sido_src == SIDO_SOURCE_RCO_BG) { 1260 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO, 1261 WCD934X_ANA_RCO_BG_EN_MASK, 1262 WCD934X_ANA_RCO_BG_ENABLE); 1263 usleep_range(100, 110); 1264 } 1265 wcd->sido_input_src = sido_src; 1266 1267 return 0; 1268 } 1269 1270 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd) 1271 { 1272 mutex_lock(&wcd->sysclk_mutex); 1273 1274 if (++wcd->sysclk_users != 1) { 1275 mutex_unlock(&wcd->sysclk_mutex); 1276 return 0; 1277 } 1278 mutex_unlock(&wcd->sysclk_mutex); 1279 1280 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1281 WCD934X_ANA_BIAS_EN_MASK, 1282 WCD934X_ANA_BIAS_EN); 1283 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1284 WCD934X_ANA_PRECHRG_EN_MASK, 1285 WCD934X_ANA_PRECHRG_EN); 1286 /* 1287 * 1ms delay is required after pre-charge is enabled 1288 * as per HW requirement 1289 */ 1290 usleep_range(1000, 1100); 1291 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1292 WCD934X_ANA_PRECHRG_EN_MASK, 0); 1293 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1294 WCD934X_ANA_PRECHRG_MODE_MASK, 0); 1295 1296 /* 1297 * In data clock contrl register is changed 1298 * to CLK_SYS_MCLK_PRG 1299 */ 1300 1301 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1302 WCD934X_EXT_CLK_BUF_EN_MASK, 1303 WCD934X_EXT_CLK_BUF_EN); 1304 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1305 WCD934X_EXT_CLK_DIV_RATIO_MASK, 1306 WCD934X_EXT_CLK_DIV_BY_2); 1307 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1308 WCD934X_MCLK_SRC_MASK, 1309 WCD934X_MCLK_SRC_EXT_CLK); 1310 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1311 WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN); 1312 regmap_update_bits(wcd->regmap, 1313 WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 1314 WCD934X_CDC_FS_MCLK_CNT_EN_MASK, 1315 WCD934X_CDC_FS_MCLK_CNT_ENABLE); 1316 regmap_update_bits(wcd->regmap, 1317 WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL, 1318 WCD934X_MCLK_EN_MASK, 1319 WCD934X_MCLK_EN); 1320 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE, 1321 WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0); 1322 /* 1323 * 10us sleep is required after clock is enabled 1324 * as per HW requirement 1325 */ 1326 usleep_range(10, 15); 1327 1328 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG); 1329 1330 return 0; 1331 } 1332 1333 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd) 1334 { 1335 mutex_lock(&wcd->sysclk_mutex); 1336 if (--wcd->sysclk_users != 0) { 1337 mutex_unlock(&wcd->sysclk_mutex); 1338 return 0; 1339 } 1340 mutex_unlock(&wcd->sysclk_mutex); 1341 1342 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1343 WCD934X_EXT_CLK_BUF_EN_MASK | 1344 WCD934X_MCLK_EN_MASK, 0x0); 1345 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1346 WCD934X_ANA_BIAS_EN_MASK, 0); 1347 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1348 WCD934X_ANA_PRECHRG_EN_MASK, 0); 1349 1350 return 0; 1351 } 1352 1353 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable) 1354 { 1355 int ret = 0; 1356 1357 if (enable) { 1358 ret = clk_prepare_enable(wcd->extclk); 1359 1360 if (ret) { 1361 dev_err(wcd->dev, "%s: ext clk enable failed\n", 1362 __func__); 1363 return ret; 1364 } 1365 ret = wcd934x_enable_ana_bias_and_sysclk(wcd); 1366 } else { 1367 int val; 1368 1369 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1370 &val); 1371 1372 /* Don't disable clock if soundwire using it.*/ 1373 if (val & WCD934X_CDC_SWR_CLK_EN_MASK) 1374 return 0; 1375 1376 wcd934x_disable_ana_bias_and_syclk(wcd); 1377 clk_disable_unprepare(wcd->extclk); 1378 } 1379 1380 return ret; 1381 } 1382 1383 static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w, 1384 struct snd_kcontrol *kc, int event) 1385 { 1386 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 1387 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 1388 1389 switch (event) { 1390 case SND_SOC_DAPM_PRE_PMU: 1391 return __wcd934x_cdc_mclk_enable(wcd, true); 1392 case SND_SOC_DAPM_POST_PMD: 1393 return __wcd934x_cdc_mclk_enable(wcd, false); 1394 } 1395 1396 return 0; 1397 } 1398 1399 static int wcd934x_get_version(struct wcd934x_codec *wcd) 1400 { 1401 int val1, val2, ver, ret; 1402 struct regmap *regmap; 1403 u16 id_minor; 1404 u32 version_mask = 0; 1405 1406 regmap = wcd->regmap; 1407 ver = 0; 1408 1409 ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0, 1410 (u8 *)&id_minor, sizeof(u16)); 1411 1412 if (ret) 1413 return ret; 1414 1415 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1); 1416 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2); 1417 1418 version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK; 1419 version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK; 1420 1421 switch (version_mask) { 1422 case DSD_DISABLED | SLNQ_DISABLED: 1423 if (id_minor == 0) 1424 ver = WCD_VERSION_WCD9340_1_0; 1425 else if (id_minor == 0x01) 1426 ver = WCD_VERSION_WCD9340_1_1; 1427 break; 1428 case SLNQ_DISABLED: 1429 if (id_minor == 0) 1430 ver = WCD_VERSION_WCD9341_1_0; 1431 else if (id_minor == 0x01) 1432 ver = WCD_VERSION_WCD9341_1_1; 1433 break; 1434 } 1435 1436 wcd->version = ver; 1437 dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver); 1438 1439 return 0; 1440 } 1441 1442 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd) 1443 { 1444 int rc, val; 1445 1446 __wcd934x_cdc_mclk_enable(wcd, true); 1447 1448 regmap_update_bits(wcd->regmap, 1449 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL, 1450 WCD934X_EFUSE_SENSE_STATE_MASK, 1451 WCD934X_EFUSE_SENSE_STATE_DEF); 1452 regmap_update_bits(wcd->regmap, 1453 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL, 1454 WCD934X_EFUSE_SENSE_EN_MASK, 1455 WCD934X_EFUSE_SENSE_ENABLE); 1456 /* 1457 * 5ms sleep required after enabling efuse control 1458 * before checking the status. 1459 */ 1460 usleep_range(5000, 5500); 1461 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG); 1462 1463 rc = regmap_read(wcd->regmap, 1464 WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val); 1465 if (rc || (!(val & 0x01))) 1466 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n", 1467 __func__, val, rc); 1468 1469 __wcd934x_cdc_mclk_enable(wcd, false); 1470 } 1471 1472 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable) 1473 { 1474 if (enable) { 1475 __wcd934x_cdc_mclk_enable(wcd, true); 1476 regmap_update_bits(wcd->regmap, 1477 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1478 WCD934X_CDC_SWR_CLK_EN_MASK, 1479 WCD934X_CDC_SWR_CLK_ENABLE); 1480 } else { 1481 regmap_update_bits(wcd->regmap, 1482 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1483 WCD934X_CDC_SWR_CLK_EN_MASK, 0); 1484 __wcd934x_cdc_mclk_enable(wcd, false); 1485 } 1486 1487 return 0; 1488 } 1489 1490 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1491 u8 rate_val, u32 rate) 1492 { 1493 struct snd_soc_component *comp = dai->component; 1494 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 1495 struct wcd934x_slim_ch *ch; 1496 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; 1497 int inp, j; 1498 1499 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1500 inp = ch->shift + INTn_1_INP_SEL_RX0; 1501 /* 1502 * Loop through all interpolator MUX inputs and find out 1503 * to which interpolator input, the slim rx port 1504 * is connected 1505 */ 1506 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) { 1507 /* Interpolators 5 and 6 are not aviliable in Tavil */ 1508 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA) 1509 continue; 1510 1511 cfg0 = snd_soc_component_read(comp, 1512 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j)); 1513 cfg1 = snd_soc_component_read(comp, 1514 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)); 1515 1516 inp0_sel = cfg0 & 1517 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1518 inp1_sel = (cfg0 >> 4) & 1519 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1520 inp2_sel = (cfg1 >> 4) & 1521 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1522 1523 if ((inp0_sel == inp) || (inp1_sel == inp) || 1524 (inp2_sel == inp)) { 1525 /* rate is in Hz */ 1526 /* 1527 * Ear and speaker primary path does not support 1528 * native sample rates 1529 */ 1530 if ((j == INTERP_EAR || j == INTERP_SPKR1 || 1531 j == INTERP_SPKR2) && rate == 44100) 1532 dev_err(wcd->dev, 1533 "Cannot set 44.1KHz on INT%d\n", 1534 j); 1535 else 1536 snd_soc_component_update_bits(comp, 1537 WCD934X_CDC_RX_PATH_CTL(j), 1538 WCD934X_CDC_MIX_PCM_RATE_MASK, 1539 rate_val); 1540 } 1541 } 1542 } 1543 1544 return 0; 1545 } 1546 1547 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1548 int rate_val, u32 rate) 1549 { 1550 struct snd_soc_component *component = dai->component; 1551 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 1552 struct wcd934x_slim_ch *ch; 1553 int val, j; 1554 1555 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1556 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) { 1557 /* Interpolators 5 and 6 are not aviliable in Tavil */ 1558 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA) 1559 continue; 1560 val = snd_soc_component_read(component, 1561 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) & 1562 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1563 1564 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) { 1565 /* 1566 * Ear mix path supports only 48, 96, 192, 1567 * 384KHz only 1568 */ 1569 if ((j == INTERP_EAR) && 1570 (rate_val < 0x4 || 1571 rate_val > 0x7)) { 1572 dev_err(component->dev, 1573 "Invalid rate for AIF_PB DAI(%d)\n", 1574 dai->id); 1575 return -EINVAL; 1576 } 1577 1578 snd_soc_component_update_bits(component, 1579 WCD934X_CDC_RX_PATH_MIX_CTL(j), 1580 WCD934X_CDC_MIX_PCM_RATE_MASK, 1581 rate_val); 1582 } 1583 } 1584 } 1585 1586 return 0; 1587 } 1588 1589 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai, 1590 u32 sample_rate) 1591 { 1592 int rate_val = 0; 1593 int i, ret; 1594 1595 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) { 1596 if (sample_rate == sr_val_tbl[i].sample_rate) { 1597 rate_val = sr_val_tbl[i].rate_val; 1598 break; 1599 } 1600 } 1601 if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) { 1602 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate); 1603 return -EINVAL; 1604 } 1605 1606 ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val, 1607 sample_rate); 1608 if (ret) 1609 return ret; 1610 ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val, 1611 sample_rate); 1612 1613 return ret; 1614 } 1615 1616 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai, 1617 u8 rate_val, u32 rate) 1618 { 1619 struct snd_soc_component *comp = dai->component; 1620 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 1621 u8 shift = 0, shift_val = 0, tx_mux_sel; 1622 struct wcd934x_slim_ch *ch; 1623 int tx_port, tx_port_reg; 1624 int decimator = -1; 1625 1626 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1627 tx_port = ch->port; 1628 /* Find the SB TX MUX input - which decimator is connected */ 1629 switch (tx_port) { 1630 case 0 ... 3: 1631 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0; 1632 shift = (tx_port << 1); 1633 shift_val = 0x03; 1634 break; 1635 case 4 ... 7: 1636 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1; 1637 shift = ((tx_port - 4) << 1); 1638 shift_val = 0x03; 1639 break; 1640 case 8 ... 10: 1641 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2; 1642 shift = ((tx_port - 8) << 1); 1643 shift_val = 0x03; 1644 break; 1645 case 11: 1646 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3; 1647 shift = 0; 1648 shift_val = 0x0F; 1649 break; 1650 case 13: 1651 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3; 1652 shift = 4; 1653 shift_val = 0x03; 1654 break; 1655 default: 1656 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n", 1657 tx_port, dai->id); 1658 return -EINVAL; 1659 } 1660 1661 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) & 1662 (shift_val << shift); 1663 1664 tx_mux_sel = tx_mux_sel >> shift; 1665 switch (tx_port) { 1666 case 0 ... 8: 1667 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3)) 1668 decimator = tx_port; 1669 break; 1670 case 9 ... 10: 1671 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1672 decimator = ((tx_port == 9) ? 7 : 6); 1673 break; 1674 case 11: 1675 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7)) 1676 decimator = tx_mux_sel - 1; 1677 break; 1678 case 13: 1679 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1680 decimator = 5; 1681 break; 1682 default: 1683 dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n", 1684 tx_port); 1685 return -EINVAL; 1686 } 1687 1688 snd_soc_component_update_bits(comp, 1689 WCD934X_CDC_TX_PATH_CTL(decimator), 1690 WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK, 1691 rate_val); 1692 } 1693 1694 return 0; 1695 } 1696 1697 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd, 1698 struct wcd_slim_codec_dai_data *dai_data, 1699 int direction) 1700 { 1701 struct list_head *slim_ch_list = &dai_data->slim_ch_list; 1702 struct slim_stream_config *cfg = &dai_data->sconfig; 1703 struct wcd934x_slim_ch *ch; 1704 u16 payload = 0; 1705 int ret, i; 1706 1707 cfg->ch_count = 0; 1708 cfg->direction = direction; 1709 cfg->port_mask = 0; 1710 1711 /* Configure slave interface device */ 1712 list_for_each_entry(ch, slim_ch_list, list) { 1713 cfg->ch_count++; 1714 payload |= 1 << ch->shift; 1715 cfg->port_mask |= BIT(ch->port); 1716 } 1717 1718 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL); 1719 if (!cfg->chs) 1720 return -ENOMEM; 1721 1722 i = 0; 1723 list_for_each_entry(ch, slim_ch_list, list) { 1724 cfg->chs[i++] = ch->ch_num; 1725 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1726 /* write to interface device */ 1727 ret = regmap_write(wcd->if_regmap, 1728 WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port), 1729 payload); 1730 1731 if (ret < 0) 1732 goto err; 1733 1734 /* configure the slave port for water mark and enable*/ 1735 ret = regmap_write(wcd->if_regmap, 1736 WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port), 1737 WCD934X_SLIM_WATER_MARK_VAL); 1738 if (ret < 0) 1739 goto err; 1740 } else { 1741 ret = regmap_write(wcd->if_regmap, 1742 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port), 1743 payload & 0x00FF); 1744 if (ret < 0) 1745 goto err; 1746 1747 /* ports 8,9 */ 1748 ret = regmap_write(wcd->if_regmap, 1749 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port), 1750 (payload & 0xFF00) >> 8); 1751 if (ret < 0) 1752 goto err; 1753 1754 /* configure the slave port for water mark and enable*/ 1755 ret = regmap_write(wcd->if_regmap, 1756 WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port), 1757 WCD934X_SLIM_WATER_MARK_VAL); 1758 1759 if (ret < 0) 1760 goto err; 1761 } 1762 } 1763 1764 dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM"); 1765 1766 return 0; 1767 1768 err: 1769 dev_err(wcd->dev, "Error Setting slim hw params\n"); 1770 kfree(cfg->chs); 1771 cfg->chs = NULL; 1772 1773 return ret; 1774 } 1775 1776 static int wcd934x_hw_params(struct snd_pcm_substream *substream, 1777 struct snd_pcm_hw_params *params, 1778 struct snd_soc_dai *dai) 1779 { 1780 struct wcd934x_codec *wcd; 1781 int ret, tx_fs_rate = 0; 1782 1783 wcd = snd_soc_component_get_drvdata(dai->component); 1784 1785 switch (substream->stream) { 1786 case SNDRV_PCM_STREAM_PLAYBACK: 1787 ret = wcd934x_set_interpolator_rate(dai, params_rate(params)); 1788 if (ret) { 1789 dev_err(wcd->dev, "cannot set sample rate: %u\n", 1790 params_rate(params)); 1791 return ret; 1792 } 1793 switch (params_width(params)) { 1794 case 16 ... 24: 1795 wcd->dai[dai->id].sconfig.bps = params_width(params); 1796 break; 1797 default: 1798 dev_err(wcd->dev, "Invalid format 0x%x\n", 1799 params_width(params)); 1800 return -EINVAL; 1801 } 1802 break; 1803 1804 case SNDRV_PCM_STREAM_CAPTURE: 1805 switch (params_rate(params)) { 1806 case 8000: 1807 tx_fs_rate = 0; 1808 break; 1809 case 16000: 1810 tx_fs_rate = 1; 1811 break; 1812 case 32000: 1813 tx_fs_rate = 3; 1814 break; 1815 case 48000: 1816 tx_fs_rate = 4; 1817 break; 1818 case 96000: 1819 tx_fs_rate = 5; 1820 break; 1821 case 192000: 1822 tx_fs_rate = 6; 1823 break; 1824 case 384000: 1825 tx_fs_rate = 7; 1826 break; 1827 default: 1828 dev_err(wcd->dev, "Invalid TX sample rate: %d\n", 1829 params_rate(params)); 1830 return -EINVAL; 1831 1832 } 1833 1834 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate, 1835 params_rate(params)); 1836 if (ret < 0) { 1837 dev_err(wcd->dev, "Cannot set TX Decimator rate\n"); 1838 return ret; 1839 } 1840 switch (params_width(params)) { 1841 case 16 ... 32: 1842 wcd->dai[dai->id].sconfig.bps = params_width(params); 1843 break; 1844 default: 1845 dev_err(wcd->dev, "Invalid format 0x%x\n", 1846 params_width(params)); 1847 return -EINVAL; 1848 } 1849 break; 1850 default: 1851 dev_err(wcd->dev, "Invalid stream type %d\n", 1852 substream->stream); 1853 return -EINVAL; 1854 } 1855 1856 wcd->dai[dai->id].sconfig.rate = params_rate(params); 1857 1858 return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream); 1859 } 1860 1861 static int wcd934x_hw_free(struct snd_pcm_substream *substream, 1862 struct snd_soc_dai *dai) 1863 { 1864 struct wcd_slim_codec_dai_data *dai_data; 1865 struct wcd934x_codec *wcd; 1866 1867 wcd = snd_soc_component_get_drvdata(dai->component); 1868 1869 dai_data = &wcd->dai[dai->id]; 1870 1871 kfree(dai_data->sconfig.chs); 1872 1873 return 0; 1874 } 1875 1876 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd, 1877 struct snd_soc_dai *dai) 1878 { 1879 struct wcd_slim_codec_dai_data *dai_data; 1880 struct wcd934x_codec *wcd; 1881 struct slim_stream_config *cfg; 1882 1883 wcd = snd_soc_component_get_drvdata(dai->component); 1884 1885 dai_data = &wcd->dai[dai->id]; 1886 1887 switch (cmd) { 1888 case SNDRV_PCM_TRIGGER_START: 1889 case SNDRV_PCM_TRIGGER_RESUME: 1890 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1891 cfg = &dai_data->sconfig; 1892 slim_stream_prepare(dai_data->sruntime, cfg); 1893 slim_stream_enable(dai_data->sruntime); 1894 break; 1895 case SNDRV_PCM_TRIGGER_STOP: 1896 case SNDRV_PCM_TRIGGER_SUSPEND: 1897 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1898 slim_stream_disable(dai_data->sruntime); 1899 slim_stream_unprepare(dai_data->sruntime); 1900 break; 1901 default: 1902 break; 1903 } 1904 1905 return 0; 1906 } 1907 1908 static int wcd934x_set_channel_map(struct snd_soc_dai *dai, 1909 unsigned int tx_num, 1910 const unsigned int *tx_slot, 1911 unsigned int rx_num, 1912 const unsigned int *rx_slot) 1913 { 1914 struct wcd934x_codec *wcd; 1915 int i; 1916 1917 wcd = snd_soc_component_get_drvdata(dai->component); 1918 1919 if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) { 1920 dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n", 1921 tx_num, rx_num); 1922 return -EINVAL; 1923 } 1924 1925 if (!tx_slot || !rx_slot) { 1926 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n", 1927 tx_slot, rx_slot); 1928 return -EINVAL; 1929 } 1930 1931 wcd->num_rx_port = rx_num; 1932 for (i = 0; i < rx_num; i++) { 1933 wcd->rx_chs[i].ch_num = rx_slot[i]; 1934 INIT_LIST_HEAD(&wcd->rx_chs[i].list); 1935 } 1936 1937 wcd->num_tx_port = tx_num; 1938 for (i = 0; i < tx_num; i++) { 1939 wcd->tx_chs[i].ch_num = tx_slot[i]; 1940 INIT_LIST_HEAD(&wcd->tx_chs[i].list); 1941 } 1942 1943 return 0; 1944 } 1945 1946 static int wcd934x_get_channel_map(const struct snd_soc_dai *dai, 1947 unsigned int *tx_num, unsigned int *tx_slot, 1948 unsigned int *rx_num, unsigned int *rx_slot) 1949 { 1950 struct wcd934x_slim_ch *ch; 1951 struct wcd934x_codec *wcd; 1952 int i = 0; 1953 1954 wcd = snd_soc_component_get_drvdata(dai->component); 1955 1956 switch (dai->id) { 1957 case AIF1_PB: 1958 case AIF2_PB: 1959 case AIF3_PB: 1960 case AIF4_PB: 1961 if (!rx_slot || !rx_num) { 1962 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n", 1963 rx_slot, rx_num); 1964 return -EINVAL; 1965 } 1966 1967 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 1968 rx_slot[i++] = ch->ch_num; 1969 1970 *rx_num = i; 1971 break; 1972 case AIF1_CAP: 1973 case AIF2_CAP: 1974 case AIF3_CAP: 1975 if (!tx_slot || !tx_num) { 1976 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n", 1977 tx_slot, tx_num); 1978 return -EINVAL; 1979 } 1980 1981 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 1982 tx_slot[i++] = ch->ch_num; 1983 1984 *tx_num = i; 1985 break; 1986 default: 1987 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id); 1988 break; 1989 } 1990 1991 return 0; 1992 } 1993 1994 static const struct snd_soc_dai_ops wcd934x_dai_ops = { 1995 .hw_params = wcd934x_hw_params, 1996 .hw_free = wcd934x_hw_free, 1997 .trigger = wcd934x_trigger, 1998 .set_channel_map = wcd934x_set_channel_map, 1999 .get_channel_map = wcd934x_get_channel_map, 2000 }; 2001 2002 static struct snd_soc_dai_driver wcd934x_slim_dais[] = { 2003 [0] = { 2004 .name = "wcd934x_rx1", 2005 .id = AIF1_PB, 2006 .playback = { 2007 .stream_name = "AIF1 Playback", 2008 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2009 .formats = WCD934X_FORMATS_S16_S24_LE, 2010 .rate_max = 192000, 2011 .rate_min = 8000, 2012 .channels_min = 1, 2013 .channels_max = 2, 2014 }, 2015 .ops = &wcd934x_dai_ops, 2016 }, 2017 [1] = { 2018 .name = "wcd934x_tx1", 2019 .id = AIF1_CAP, 2020 .capture = { 2021 .stream_name = "AIF1 Capture", 2022 .rates = WCD934X_RATES_MASK, 2023 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2024 .rate_min = 8000, 2025 .rate_max = 192000, 2026 .channels_min = 1, 2027 .channels_max = 4, 2028 }, 2029 .ops = &wcd934x_dai_ops, 2030 }, 2031 [2] = { 2032 .name = "wcd934x_rx2", 2033 .id = AIF2_PB, 2034 .playback = { 2035 .stream_name = "AIF2 Playback", 2036 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2037 .formats = WCD934X_FORMATS_S16_S24_LE, 2038 .rate_min = 8000, 2039 .rate_max = 192000, 2040 .channels_min = 1, 2041 .channels_max = 2, 2042 }, 2043 .ops = &wcd934x_dai_ops, 2044 }, 2045 [3] = { 2046 .name = "wcd934x_tx2", 2047 .id = AIF2_CAP, 2048 .capture = { 2049 .stream_name = "AIF2 Capture", 2050 .rates = WCD934X_RATES_MASK, 2051 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2052 .rate_min = 8000, 2053 .rate_max = 192000, 2054 .channels_min = 1, 2055 .channels_max = 4, 2056 }, 2057 .ops = &wcd934x_dai_ops, 2058 }, 2059 [4] = { 2060 .name = "wcd934x_rx3", 2061 .id = AIF3_PB, 2062 .playback = { 2063 .stream_name = "AIF3 Playback", 2064 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2065 .formats = WCD934X_FORMATS_S16_S24_LE, 2066 .rate_min = 8000, 2067 .rate_max = 192000, 2068 .channels_min = 1, 2069 .channels_max = 2, 2070 }, 2071 .ops = &wcd934x_dai_ops, 2072 }, 2073 [5] = { 2074 .name = "wcd934x_tx3", 2075 .id = AIF3_CAP, 2076 .capture = { 2077 .stream_name = "AIF3 Capture", 2078 .rates = WCD934X_RATES_MASK, 2079 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2080 .rate_min = 8000, 2081 .rate_max = 192000, 2082 .channels_min = 1, 2083 .channels_max = 4, 2084 }, 2085 .ops = &wcd934x_dai_ops, 2086 }, 2087 [6] = { 2088 .name = "wcd934x_rx4", 2089 .id = AIF4_PB, 2090 .playback = { 2091 .stream_name = "AIF4 Playback", 2092 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2093 .formats = WCD934X_FORMATS_S16_S24_LE, 2094 .rate_min = 8000, 2095 .rate_max = 192000, 2096 .channels_min = 1, 2097 .channels_max = 2, 2098 }, 2099 .ops = &wcd934x_dai_ops, 2100 }, 2101 }; 2102 2103 static int swclk_gate_enable(struct clk_hw *hw) 2104 { 2105 return wcd934x_swrm_clock(to_wcd934x_codec(hw), true); 2106 } 2107 2108 static void swclk_gate_disable(struct clk_hw *hw) 2109 { 2110 wcd934x_swrm_clock(to_wcd934x_codec(hw), false); 2111 } 2112 2113 static int swclk_gate_is_enabled(struct clk_hw *hw) 2114 { 2115 struct wcd934x_codec *wcd = to_wcd934x_codec(hw); 2116 int ret, val; 2117 2118 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val); 2119 ret = val & WCD934X_CDC_SWR_CLK_EN_MASK; 2120 2121 return ret; 2122 } 2123 2124 static unsigned long swclk_recalc_rate(struct clk_hw *hw, 2125 unsigned long parent_rate) 2126 { 2127 return parent_rate / 2; 2128 } 2129 2130 static const struct clk_ops swclk_gate_ops = { 2131 .prepare = swclk_gate_enable, 2132 .unprepare = swclk_gate_disable, 2133 .is_enabled = swclk_gate_is_enabled, 2134 .recalc_rate = swclk_recalc_rate, 2135 2136 }; 2137 2138 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd) 2139 { 2140 struct clk *parent = wcd->extclk; 2141 struct device *dev = wcd->dev; 2142 struct device_node *np = dev->parent->of_node; 2143 const char *parent_clk_name = NULL; 2144 const char *clk_name = "mclk"; 2145 struct clk_hw *hw; 2146 struct clk_init_data init; 2147 int ret; 2148 2149 if (of_property_read_u32(np, "clock-frequency", &wcd->rate)) 2150 return NULL; 2151 2152 parent_clk_name = __clk_get_name(parent); 2153 2154 of_property_read_string(np, "clock-output-names", &clk_name); 2155 2156 init.name = clk_name; 2157 init.ops = &swclk_gate_ops; 2158 init.flags = 0; 2159 init.parent_names = &parent_clk_name; 2160 init.num_parents = 1; 2161 wcd->hw.init = &init; 2162 2163 hw = &wcd->hw; 2164 ret = devm_clk_hw_register(wcd->dev->parent, hw); 2165 if (ret) 2166 return ERR_PTR(ret); 2167 2168 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 2169 if (ret) 2170 return ERR_PTR(ret); 2171 2172 return NULL; 2173 } 2174 2175 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias, 2176 u32 *micb_mv) 2177 { 2178 int mv; 2179 2180 if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) { 2181 dev_err(dev, "%s value not found, using default\n", micbias); 2182 mv = WCD934X_DEF_MICBIAS_MV; 2183 } else { 2184 /* convert it to milli volts */ 2185 mv = mv/1000; 2186 } 2187 2188 if (mv < 1000 || mv > 2850) { 2189 dev_err(dev, "%s value not in valid range, using default\n", 2190 micbias); 2191 mv = WCD934X_DEF_MICBIAS_MV; 2192 } 2193 2194 if (micb_mv) 2195 *micb_mv = mv; 2196 2197 return (mv - 1000) / 50; 2198 } 2199 2200 static int wcd934x_init_dmic(struct snd_soc_component *comp) 2201 { 2202 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4; 2203 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 2204 u32 def_dmic_rate, dmic_clk_drv; 2205 2206 vout_ctl_1 = wcd934x_get_micbias_val(comp->dev, 2207 "qcom,micbias1-microvolt", NULL); 2208 vout_ctl_2 = wcd934x_get_micbias_val(comp->dev, 2209 "qcom,micbias2-microvolt", 2210 &wcd->micb2_mv); 2211 vout_ctl_3 = wcd934x_get_micbias_val(comp->dev, 2212 "qcom,micbias3-microvolt", NULL); 2213 vout_ctl_4 = wcd934x_get_micbias_val(comp->dev, 2214 "qcom,micbias4-microvolt", NULL); 2215 2216 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1, 2217 WCD934X_MICB_VAL_MASK, vout_ctl_1); 2218 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2, 2219 WCD934X_MICB_VAL_MASK, vout_ctl_2); 2220 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3, 2221 WCD934X_MICB_VAL_MASK, vout_ctl_3); 2222 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4, 2223 WCD934X_MICB_VAL_MASK, vout_ctl_4); 2224 2225 if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ) 2226 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ; 2227 else 2228 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ; 2229 2230 wcd->dmic_sample_rate = def_dmic_rate; 2231 2232 dmic_clk_drv = 0; 2233 snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0, 2234 0x0C, dmic_clk_drv << 2); 2235 2236 return 0; 2237 } 2238 2239 static void wcd934x_hw_init(struct wcd934x_codec *wcd) 2240 { 2241 struct regmap *rm = wcd->regmap; 2242 2243 /* set SPKR rate to FS_2P4_3P072 */ 2244 regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08); 2245 regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08); 2246 2247 /* Take DMICs out of reset */ 2248 regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00); 2249 } 2250 2251 static int wcd934x_comp_init(struct snd_soc_component *component) 2252 { 2253 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2254 2255 wcd934x_hw_init(wcd); 2256 wcd934x_enable_efuse_sensing(wcd); 2257 wcd934x_get_version(wcd); 2258 2259 return 0; 2260 } 2261 2262 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data) 2263 { 2264 struct wcd934x_codec *wcd = data; 2265 unsigned long status = 0; 2266 unsigned int i, j, port_id; 2267 unsigned int val, int_val = 0; 2268 irqreturn_t ret = IRQ_NONE; 2269 bool tx; 2270 unsigned short reg = 0; 2271 2272 for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0; 2273 i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) { 2274 regmap_read(wcd->if_regmap, i, &val); 2275 status |= ((u32)val << (8 * j)); 2276 } 2277 2278 for_each_set_bit(j, &status, 32) { 2279 tx = false; 2280 port_id = j; 2281 2282 if (j >= 16) { 2283 tx = true; 2284 port_id = j - 16; 2285 } 2286 2287 regmap_read(wcd->if_regmap, 2288 WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); 2289 if (val) { 2290 if (!tx) 2291 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + 2292 (port_id / 8); 2293 else 2294 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + 2295 (port_id / 8); 2296 regmap_read(wcd->if_regmap, reg, &int_val); 2297 } 2298 2299 if (val & WCD934X_SLIM_IRQ_OVERFLOW) 2300 dev_err_ratelimited(wcd->dev, 2301 "overflow error on %s port %d, value %x\n", 2302 (tx ? "TX" : "RX"), port_id, val); 2303 2304 if (val & WCD934X_SLIM_IRQ_UNDERFLOW) 2305 dev_err_ratelimited(wcd->dev, 2306 "underflow error on %s port %d, value %x\n", 2307 (tx ? "TX" : "RX"), port_id, val); 2308 2309 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) || 2310 (val & WCD934X_SLIM_IRQ_UNDERFLOW)) { 2311 if (!tx) 2312 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + 2313 (port_id / 8); 2314 else 2315 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + 2316 (port_id / 8); 2317 regmap_read( 2318 wcd->if_regmap, reg, &int_val); 2319 if (int_val & (1 << (port_id % 8))) { 2320 int_val = int_val ^ (1 << (port_id % 8)); 2321 regmap_write(wcd->if_regmap, 2322 reg, int_val); 2323 } 2324 } 2325 2326 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED) 2327 dev_err_ratelimited(wcd->dev, 2328 "Port Closed %s port %d, value %x\n", 2329 (tx ? "TX" : "RX"), port_id, val); 2330 2331 regmap_write(wcd->if_regmap, 2332 WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8), 2333 BIT(j % 8)); 2334 ret = IRQ_HANDLED; 2335 } 2336 2337 return ret; 2338 } 2339 2340 static void wcd934x_mbhc_clk_setup(struct snd_soc_component *component, 2341 bool enable) 2342 { 2343 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_CTL_1, 2344 WCD934X_MBHC_CTL_RCO_EN_MASK, enable); 2345 } 2346 2347 static void wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 2348 bool enable) 2349 { 2350 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_ELECT, 2351 WCD934X_ANA_MBHC_BIAS_EN, enable); 2352 } 2353 2354 static void wcd934x_mbhc_program_btn_thr(struct snd_soc_component *component, 2355 int *btn_low, int *btn_high, 2356 int num_btn, bool is_micbias) 2357 { 2358 int i, vth; 2359 2360 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 2361 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 2362 __func__, num_btn); 2363 return; 2364 } 2365 2366 for (i = 0; i < num_btn; i++) { 2367 vth = ((btn_high[i] * 2) / 25) & 0x3F; 2368 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_BTN0 + i, 2369 WCD934X_MBHC_BTN_VTH_MASK, vth); 2370 } 2371 } 2372 2373 static bool wcd934x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 2374 { 2375 u8 val; 2376 2377 if (micb_num == MIC_BIAS_2) { 2378 val = snd_soc_component_read_field(component, WCD934X_ANA_MICB2, 2379 WCD934X_ANA_MICB2_ENABLE_MASK); 2380 if (val == WCD934X_MICB_ENABLE) 2381 return true; 2382 } 2383 return false; 2384 } 2385 2386 static void wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 2387 enum mbhc_hs_pullup_iref pull_up_cur) 2388 { 2389 /* Default pull up current to 2uA */ 2390 if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA || 2391 pull_up_cur == I_DEFAULT) 2392 pull_up_cur = I_2P0_UA; 2393 2394 2395 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 2396 WCD934X_HSDET_PULLUP_C_MASK, pull_up_cur); 2397 } 2398 2399 static int wcd934x_micbias_control(struct snd_soc_component *component, 2400 int micb_num, int req, bool is_dapm) 2401 { 2402 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2403 int micb_index = micb_num - 1; 2404 u16 micb_reg; 2405 2406 switch (micb_num) { 2407 case MIC_BIAS_1: 2408 micb_reg = WCD934X_ANA_MICB1; 2409 break; 2410 case MIC_BIAS_2: 2411 micb_reg = WCD934X_ANA_MICB2; 2412 break; 2413 case MIC_BIAS_3: 2414 micb_reg = WCD934X_ANA_MICB3; 2415 break; 2416 case MIC_BIAS_4: 2417 micb_reg = WCD934X_ANA_MICB4; 2418 break; 2419 default: 2420 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2421 __func__, micb_num); 2422 return -EINVAL; 2423 } 2424 mutex_lock(&wcd934x->micb_lock); 2425 2426 switch (req) { 2427 case MICB_PULLUP_ENABLE: 2428 wcd934x->pullup_ref[micb_index]++; 2429 if ((wcd934x->pullup_ref[micb_index] == 1) && 2430 (wcd934x->micb_ref[micb_index] == 0)) 2431 snd_soc_component_write_field(component, micb_reg, 2432 WCD934X_ANA_MICB_EN_MASK, 2433 WCD934X_MICB_PULL_UP); 2434 break; 2435 case MICB_PULLUP_DISABLE: 2436 if (wcd934x->pullup_ref[micb_index] > 0) 2437 wcd934x->pullup_ref[micb_index]--; 2438 2439 if ((wcd934x->pullup_ref[micb_index] == 0) && 2440 (wcd934x->micb_ref[micb_index] == 0)) 2441 snd_soc_component_write_field(component, micb_reg, 2442 WCD934X_ANA_MICB_EN_MASK, 0); 2443 break; 2444 case MICB_ENABLE: 2445 wcd934x->micb_ref[micb_index]++; 2446 if (wcd934x->micb_ref[micb_index] == 1) { 2447 snd_soc_component_write_field(component, micb_reg, 2448 WCD934X_ANA_MICB_EN_MASK, 2449 WCD934X_MICB_ENABLE); 2450 if (micb_num == MIC_BIAS_2) 2451 wcd_mbhc_event_notify(wcd934x->mbhc, 2452 WCD_EVENT_POST_MICBIAS_2_ON); 2453 } 2454 2455 if (micb_num == MIC_BIAS_2 && is_dapm) 2456 wcd_mbhc_event_notify(wcd934x->mbhc, 2457 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 2458 break; 2459 case MICB_DISABLE: 2460 if (wcd934x->micb_ref[micb_index] > 0) 2461 wcd934x->micb_ref[micb_index]--; 2462 2463 if ((wcd934x->micb_ref[micb_index] == 0) && 2464 (wcd934x->pullup_ref[micb_index] > 0)) 2465 snd_soc_component_write_field(component, micb_reg, 2466 WCD934X_ANA_MICB_EN_MASK, 2467 WCD934X_MICB_PULL_UP); 2468 else if ((wcd934x->micb_ref[micb_index] == 0) && 2469 (wcd934x->pullup_ref[micb_index] == 0)) { 2470 if (micb_num == MIC_BIAS_2) 2471 wcd_mbhc_event_notify(wcd934x->mbhc, 2472 WCD_EVENT_PRE_MICBIAS_2_OFF); 2473 2474 snd_soc_component_write_field(component, micb_reg, 2475 WCD934X_ANA_MICB_EN_MASK, 0); 2476 if (micb_num == MIC_BIAS_2) 2477 wcd_mbhc_event_notify(wcd934x->mbhc, 2478 WCD_EVENT_POST_MICBIAS_2_OFF); 2479 } 2480 if (is_dapm && micb_num == MIC_BIAS_2) 2481 wcd_mbhc_event_notify(wcd934x->mbhc, 2482 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 2483 break; 2484 } 2485 2486 mutex_unlock(&wcd934x->micb_lock); 2487 2488 return 0; 2489 } 2490 2491 static int wcd934x_mbhc_request_micbias(struct snd_soc_component *component, 2492 int micb_num, int req) 2493 { 2494 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2495 int ret; 2496 2497 if (req == MICB_ENABLE) 2498 __wcd934x_cdc_mclk_enable(wcd, true); 2499 2500 ret = wcd934x_micbias_control(component, micb_num, req, false); 2501 2502 if (req == MICB_DISABLE) 2503 __wcd934x_cdc_mclk_enable(wcd, false); 2504 2505 return ret; 2506 } 2507 2508 static void wcd934x_mbhc_micb_ramp_control(struct snd_soc_component *component, 2509 bool enable) 2510 { 2511 if (enable) { 2512 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2513 WCD934X_RAMP_SHIFT_CTRL_MASK, 0x3); 2514 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2515 WCD934X_RAMP_EN_MASK, 1); 2516 } else { 2517 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2518 WCD934X_RAMP_EN_MASK, 0); 2519 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2520 WCD934X_RAMP_SHIFT_CTRL_MASK, 0); 2521 } 2522 } 2523 2524 static int wcd934x_get_micb_vout_ctl_val(u32 micb_mv) 2525 { 2526 /* min micbias voltage is 1V and maximum is 2.85V */ 2527 if (micb_mv < 1000 || micb_mv > 2850) 2528 return -EINVAL; 2529 2530 return (micb_mv - 1000) / 50; 2531 } 2532 2533 static int wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 2534 int req_volt, int micb_num) 2535 { 2536 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2537 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 2538 2539 switch (micb_num) { 2540 case MIC_BIAS_1: 2541 micb_reg = WCD934X_ANA_MICB1; 2542 break; 2543 case MIC_BIAS_2: 2544 micb_reg = WCD934X_ANA_MICB2; 2545 break; 2546 case MIC_BIAS_3: 2547 micb_reg = WCD934X_ANA_MICB3; 2548 break; 2549 case MIC_BIAS_4: 2550 micb_reg = WCD934X_ANA_MICB4; 2551 break; 2552 default: 2553 return -EINVAL; 2554 } 2555 mutex_lock(&wcd934x->micb_lock); 2556 /* 2557 * If requested micbias voltage is same as current micbias 2558 * voltage, then just return. Otherwise, adjust voltage as 2559 * per requested value. If micbias is already enabled, then 2560 * to avoid slow micbias ramp-up or down enable pull-up 2561 * momentarily, change the micbias value and then re-enable 2562 * micbias. 2563 */ 2564 micb_en = snd_soc_component_read_field(component, micb_reg, 2565 WCD934X_ANA_MICB_EN_MASK); 2566 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 2567 WCD934X_MICB_VAL_MASK); 2568 2569 req_vout_ctl = wcd934x_get_micb_vout_ctl_val(req_volt); 2570 if (req_vout_ctl < 0) { 2571 ret = -EINVAL; 2572 goto exit; 2573 } 2574 2575 if (cur_vout_ctl == req_vout_ctl) { 2576 ret = 0; 2577 goto exit; 2578 } 2579 2580 if (micb_en == WCD934X_MICB_ENABLE) 2581 snd_soc_component_write_field(component, micb_reg, 2582 WCD934X_ANA_MICB_EN_MASK, 2583 WCD934X_MICB_PULL_UP); 2584 2585 snd_soc_component_write_field(component, micb_reg, 2586 WCD934X_MICB_VAL_MASK, 2587 req_vout_ctl); 2588 2589 if (micb_en == WCD934X_MICB_ENABLE) { 2590 snd_soc_component_write_field(component, micb_reg, 2591 WCD934X_ANA_MICB_EN_MASK, 2592 WCD934X_MICB_ENABLE); 2593 /* 2594 * Add 2ms delay as per HW requirement after enabling 2595 * micbias 2596 */ 2597 usleep_range(2000, 2100); 2598 } 2599 exit: 2600 mutex_unlock(&wcd934x->micb_lock); 2601 return ret; 2602 } 2603 2604 static int wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 2605 int micb_num, bool req_en) 2606 { 2607 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2608 int rc, micb_mv; 2609 2610 if (micb_num != MIC_BIAS_2) 2611 return -EINVAL; 2612 /* 2613 * If device tree micbias level is already above the minimum 2614 * voltage needed to detect threshold microphone, then do 2615 * not change the micbias, just return. 2616 */ 2617 if (wcd934x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 2618 return 0; 2619 2620 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd934x->micb2_mv; 2621 2622 rc = wcd934x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 2623 2624 return rc; 2625 } 2626 2627 static void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x, 2628 s16 *d1_a, u16 noff, 2629 int32_t *zdet) 2630 { 2631 int i; 2632 int val, val1; 2633 s16 c1; 2634 s32 x1, d1; 2635 int32_t denom; 2636 static const int minCode_param[] = { 2637 3277, 1639, 820, 410, 205, 103, 52, 26 2638 }; 2639 2640 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x20); 2641 for (i = 0; i < WCD934X_ZDET_NUM_MEASUREMENTS; i++) { 2642 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val); 2643 if (val & 0x80) 2644 break; 2645 } 2646 val = val << 0x8; 2647 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val1); 2648 val |= val1; 2649 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x00); 2650 x1 = WCD934X_MBHC_GET_X1(val); 2651 c1 = WCD934X_MBHC_GET_C1(val); 2652 /* If ramp is not complete, give additional 5ms */ 2653 if ((c1 < 2) && x1) 2654 usleep_range(5000, 5050); 2655 2656 if (!c1 || !x1) { 2657 dev_err(wcd934x->dev, "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n", 2658 __func__, c1, x1); 2659 goto ramp_down; 2660 } 2661 d1 = d1_a[c1]; 2662 denom = (x1 * d1) - (1 << (14 - noff)); 2663 if (denom > 0) 2664 *zdet = (WCD934X_MBHC_ZDET_CONST * 1000) / denom; 2665 else if (x1 < minCode_param[noff]) 2666 *zdet = WCD934X_ZDET_FLOATING_IMPEDANCE; 2667 2668 dev_dbg(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%di (milliohm)\n", 2669 __func__, d1, c1, x1, *zdet); 2670 ramp_down: 2671 i = 0; 2672 2673 while (x1) { 2674 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val); 2675 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val1); 2676 val = val << 0x08; 2677 val |= val1; 2678 x1 = WCD934X_MBHC_GET_X1(val); 2679 i++; 2680 if (i == WCD934X_ZDET_NUM_MEASUREMENTS) 2681 break; 2682 } 2683 } 2684 2685 static void wcd934x_mbhc_zdet_ramp(struct snd_soc_component *component, 2686 struct wcd934x_mbhc_zdet_param *zdet_param, 2687 int32_t *zl, int32_t *zr, s16 *d1_a) 2688 { 2689 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev); 2690 int32_t zdet = 0; 2691 2692 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, 2693 WCD934X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 2694 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN5, 2695 WCD934X_VTH_MASK, zdet_param->btn5); 2696 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN6, 2697 WCD934X_VTH_MASK, zdet_param->btn6); 2698 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN7, 2699 WCD934X_VTH_MASK, zdet_param->btn7); 2700 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, 2701 WCD934X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 2702 snd_soc_component_update_bits(component, WCD934X_MBHC_NEW_ZDET_RAMP_CTL, 2703 0x0F, zdet_param->nshift); 2704 2705 if (!zl) 2706 goto z_right; 2707 /* Start impedance measurement for HPH_L */ 2708 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x80); 2709 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet); 2710 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x00); 2711 2712 *zl = zdet; 2713 2714 z_right: 2715 if (!zr) 2716 return; 2717 /* Start impedance measurement for HPH_R */ 2718 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x40); 2719 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet); 2720 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x00); 2721 2722 *zr = zdet; 2723 } 2724 2725 static void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2726 int32_t *z_val, int flag_l_r) 2727 { 2728 s16 q1; 2729 int q1_cal; 2730 2731 if (*z_val < (WCD934X_ZDET_VAL_400/1000)) 2732 q1 = snd_soc_component_read(component, 2733 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r)); 2734 else 2735 q1 = snd_soc_component_read(component, 2736 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r)); 2737 if (q1 & 0x80) 2738 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 2739 else 2740 q1_cal = (10000 + (q1 * 25)); 2741 if (q1_cal > 0) 2742 *z_val = ((*z_val) * 10000) / q1_cal; 2743 } 2744 2745 static void wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 2746 uint32_t *zl, uint32_t *zr) 2747 { 2748 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev); 2749 s16 reg0, reg1, reg2, reg3, reg4; 2750 int32_t z1L, z1R, z1Ls; 2751 int zMono, z_diff1, z_diff2; 2752 bool is_fsm_disable = false; 2753 struct wcd934x_mbhc_zdet_param zdet_param[] = { 2754 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 2755 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 2756 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 2757 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 2758 }; 2759 struct wcd934x_mbhc_zdet_param *zdet_param_ptr = NULL; 2760 s16 d1_a[][4] = { 2761 {0, 30, 90, 30}, 2762 {0, 30, 30, 5}, 2763 {0, 30, 30, 5}, 2764 {0, 30, 30, 5}, 2765 }; 2766 s16 *d1 = NULL; 2767 2768 reg0 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN5); 2769 reg1 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN6); 2770 reg2 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN7); 2771 reg3 = snd_soc_component_read(component, WCD934X_MBHC_CTL_CLK); 2772 reg4 = snd_soc_component_read(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL); 2773 2774 if (snd_soc_component_read(component, WCD934X_ANA_MBHC_ELECT) & 0x80) { 2775 is_fsm_disable = true; 2776 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x00); 2777 } 2778 2779 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 2780 if (wcd934x->mbhc_cfg.hphl_swh) 2781 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x00); 2782 2783 /* Turn off 100k pull down on HPHL */ 2784 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x00); 2785 2786 /* First get impedance on Left */ 2787 d1 = d1_a[1]; 2788 zdet_param_ptr = &zdet_param[1]; 2789 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2790 2791 if (!WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L)) 2792 goto left_ch_impedance; 2793 2794 /* Second ramp for left ch */ 2795 if (z1L < WCD934X_ZDET_VAL_32) { 2796 zdet_param_ptr = &zdet_param[0]; 2797 d1 = d1_a[0]; 2798 } else if ((z1L > WCD934X_ZDET_VAL_400) && 2799 (z1L <= WCD934X_ZDET_VAL_1200)) { 2800 zdet_param_ptr = &zdet_param[2]; 2801 d1 = d1_a[2]; 2802 } else if (z1L > WCD934X_ZDET_VAL_1200) { 2803 zdet_param_ptr = &zdet_param[3]; 2804 d1 = d1_a[3]; 2805 } 2806 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2807 2808 left_ch_impedance: 2809 if ((z1L == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2810 (z1L > WCD934X_ZDET_VAL_100K)) { 2811 *zl = WCD934X_ZDET_FLOATING_IMPEDANCE; 2812 zdet_param_ptr = &zdet_param[1]; 2813 d1 = d1_a[1]; 2814 } else { 2815 *zl = z1L/1000; 2816 wcd934x_wcd_mbhc_qfuse_cal(component, zl, 0); 2817 } 2818 dev_info(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 2819 __func__, *zl); 2820 2821 /* Start of right impedance ramp and calculation */ 2822 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2823 if (WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) { 2824 if (((z1R > WCD934X_ZDET_VAL_1200) && 2825 (zdet_param_ptr->noff == 0x6)) || 2826 ((*zl) != WCD934X_ZDET_FLOATING_IMPEDANCE)) 2827 goto right_ch_impedance; 2828 /* Second ramp for right ch */ 2829 if (z1R < WCD934X_ZDET_VAL_32) { 2830 zdet_param_ptr = &zdet_param[0]; 2831 d1 = d1_a[0]; 2832 } else if ((z1R > WCD934X_ZDET_VAL_400) && 2833 (z1R <= WCD934X_ZDET_VAL_1200)) { 2834 zdet_param_ptr = &zdet_param[2]; 2835 d1 = d1_a[2]; 2836 } else if (z1R > WCD934X_ZDET_VAL_1200) { 2837 zdet_param_ptr = &zdet_param[3]; 2838 d1 = d1_a[3]; 2839 } 2840 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2841 } 2842 right_ch_impedance: 2843 if ((z1R == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2844 (z1R > WCD934X_ZDET_VAL_100K)) { 2845 *zr = WCD934X_ZDET_FLOATING_IMPEDANCE; 2846 } else { 2847 *zr = z1R/1000; 2848 wcd934x_wcd_mbhc_qfuse_cal(component, zr, 1); 2849 } 2850 dev_err(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 2851 __func__, *zr); 2852 2853 /* Mono/stereo detection */ 2854 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) && 2855 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE)) { 2856 dev_dbg(component->dev, 2857 "%s: plug type is invalid or extension cable\n", 2858 __func__); 2859 goto zdet_complete; 2860 } 2861 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2862 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2863 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 2864 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 2865 dev_dbg(component->dev, 2866 "%s: Mono plug type with one ch floating or shorted to GND\n", 2867 __func__); 2868 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO); 2869 goto zdet_complete; 2870 } 2871 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST, 2872 WCD934X_HPHPA_GND_OVR_MASK, 1); 2873 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2874 WCD934X_HPHPA_GND_R_MASK, 1); 2875 if (*zl < (WCD934X_ZDET_VAL_32/1000)) 2876 wcd934x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1); 2877 else 2878 wcd934x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1); 2879 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2880 WCD934X_HPHPA_GND_R_MASK, 0); 2881 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST, 2882 WCD934X_HPHPA_GND_OVR_MASK, 0); 2883 z1Ls /= 1000; 2884 wcd934x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0); 2885 /* Parallel of left Z and 9 ohm pull down resistor */ 2886 zMono = ((*zl) * 9) / ((*zl) + 9); 2887 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls); 2888 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl)); 2889 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) { 2890 dev_err(component->dev, "%s: stereo plug type detected\n", 2891 __func__); 2892 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_STEREO); 2893 } else { 2894 dev_err(component->dev, "%s: MONO plug type detected\n", 2895 __func__); 2896 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO); 2897 } 2898 2899 zdet_complete: 2900 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN5, reg0); 2901 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN6, reg1); 2902 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN7, reg2); 2903 /* Turn on 100k pull down on HPHL */ 2904 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x01); 2905 2906 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 2907 if (wcd934x->mbhc_cfg.hphl_swh) 2908 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x80); 2909 2910 snd_soc_component_write(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, reg4); 2911 snd_soc_component_write(component, WCD934X_MBHC_CTL_CLK, reg3); 2912 if (is_fsm_disable) 2913 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x80); 2914 } 2915 2916 static void wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 2917 bool enable) 2918 { 2919 if (enable) { 2920 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2921 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 1); 2922 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2923 WCD934X_MBHC_GND_DET_EN_MASK, 1); 2924 } else { 2925 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2926 WCD934X_MBHC_GND_DET_EN_MASK, 0); 2927 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2928 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 0); 2929 } 2930 } 2931 2932 static void wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 2933 bool enable) 2934 { 2935 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2936 WCD934X_HPHPA_GND_R_MASK, enable); 2937 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2938 WCD934X_HPHPA_GND_L_MASK, enable); 2939 } 2940 2941 static const struct wcd_mbhc_cb mbhc_cb = { 2942 .clk_setup = wcd934x_mbhc_clk_setup, 2943 .mbhc_bias = wcd934x_mbhc_mbhc_bias_control, 2944 .set_btn_thr = wcd934x_mbhc_program_btn_thr, 2945 .micbias_enable_status = wcd934x_mbhc_micb_en_status, 2946 .hph_pull_up_control = wcd934x_mbhc_hph_l_pull_up_control, 2947 .mbhc_micbias_control = wcd934x_mbhc_request_micbias, 2948 .mbhc_micb_ramp_control = wcd934x_mbhc_micb_ramp_control, 2949 .mbhc_micb_ctrl_thr_mic = wcd934x_mbhc_micb_ctrl_threshold_mic, 2950 .compute_impedance = wcd934x_wcd_mbhc_calc_impedance, 2951 .mbhc_gnd_det_ctrl = wcd934x_mbhc_gnd_det_ctrl, 2952 .hph_pull_down_ctrl = wcd934x_mbhc_hph_pull_down_ctrl, 2953 }; 2954 2955 static int wcd934x_get_hph_type(struct snd_kcontrol *kcontrol, 2956 struct snd_ctl_elem_value *ucontrol) 2957 { 2958 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2959 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 2960 2961 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd->mbhc); 2962 2963 return 0; 2964 } 2965 2966 static int wcd934x_hph_impedance_get(struct snd_kcontrol *kcontrol, 2967 struct snd_ctl_elem_value *ucontrol) 2968 { 2969 uint32_t zl, zr; 2970 bool hphr; 2971 struct soc_mixer_control *mc; 2972 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2973 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 2974 2975 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2976 hphr = mc->shift; 2977 wcd_mbhc_get_impedance(wcd->mbhc, &zl, &zr); 2978 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 2979 ucontrol->value.integer.value[0] = hphr ? zr : zl; 2980 2981 return 0; 2982 } 2983 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 2984 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 2985 wcd934x_get_hph_type, NULL), 2986 }; 2987 2988 static const struct snd_kcontrol_new impedance_detect_controls[] = { 2989 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 2990 wcd934x_hph_impedance_get, NULL), 2991 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 2992 wcd934x_hph_impedance_get, NULL), 2993 }; 2994 2995 static int wcd934x_mbhc_init(struct snd_soc_component *component) 2996 { 2997 struct wcd934x_ddata *data = dev_get_drvdata(component->dev->parent); 2998 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 2999 struct wcd_mbhc_intr *intr_ids = &wcd->intr_ids; 3000 3001 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(data->irq_data, 3002 WCD934X_IRQ_MBHC_SW_DET); 3003 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(data->irq_data, 3004 WCD934X_IRQ_MBHC_BUTTON_PRESS_DET); 3005 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(data->irq_data, 3006 WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET); 3007 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(data->irq_data, 3008 WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 3009 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(data->irq_data, 3010 WCD934X_IRQ_MBHC_ELECT_INS_REM_DET); 3011 intr_ids->hph_left_ocp = regmap_irq_get_virq(data->irq_data, 3012 WCD934X_IRQ_HPH_PA_OCPL_FAULT); 3013 intr_ids->hph_right_ocp = regmap_irq_get_virq(data->irq_data, 3014 WCD934X_IRQ_HPH_PA_OCPR_FAULT); 3015 3016 wcd->mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 3017 if (IS_ERR(wcd->mbhc)) { 3018 wcd->mbhc = NULL; 3019 return -EINVAL; 3020 } 3021 3022 snd_soc_add_component_controls(component, impedance_detect_controls, 3023 ARRAY_SIZE(impedance_detect_controls)); 3024 snd_soc_add_component_controls(component, hph_type_detect_controls, 3025 ARRAY_SIZE(hph_type_detect_controls)); 3026 3027 return 0; 3028 } 3029 3030 static void wcd934x_mbhc_deinit(struct snd_soc_component *component) 3031 { 3032 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 3033 3034 if (!wcd->mbhc) 3035 return; 3036 3037 wcd_mbhc_deinit(wcd->mbhc); 3038 } 3039 3040 static int wcd934x_comp_probe(struct snd_soc_component *component) 3041 { 3042 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3043 int i; 3044 3045 snd_soc_component_init_regmap(component, wcd->regmap); 3046 wcd->component = component; 3047 3048 /* Class-H Init*/ 3049 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version); 3050 if (IS_ERR(wcd->clsh_ctrl)) 3051 return PTR_ERR(wcd->clsh_ctrl); 3052 3053 /* Default HPH Mode to Class-H Low HiFi */ 3054 wcd->hph_mode = CLS_H_LOHIFI; 3055 3056 wcd934x_comp_init(component); 3057 3058 for (i = 0; i < NUM_CODEC_DAIS; i++) 3059 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list); 3060 3061 wcd934x_init_dmic(component); 3062 3063 if (wcd934x_mbhc_init(component)) 3064 dev_err(component->dev, "Failed to Initialize MBHC\n"); 3065 3066 return 0; 3067 } 3068 3069 static void wcd934x_comp_remove(struct snd_soc_component *comp) 3070 { 3071 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 3072 3073 wcd934x_mbhc_deinit(comp); 3074 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 3075 } 3076 3077 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp, 3078 int clk_id, int source, 3079 unsigned int freq, int dir) 3080 { 3081 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 3082 int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ; 3083 3084 wcd->rate = freq; 3085 3086 if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ) 3087 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ; 3088 3089 snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG, 3090 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 3091 val); 3092 3093 return clk_set_rate(wcd->extclk, freq); 3094 } 3095 3096 static uint32_t get_iir_band_coeff(struct snd_soc_component *component, 3097 int iir_idx, int band_idx, int coeff_idx) 3098 { 3099 u32 value = 0; 3100 int reg, b2_reg; 3101 3102 /* Address does not automatically update if reading */ 3103 reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx; 3104 b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx; 3105 3106 snd_soc_component_write(component, reg, 3107 ((band_idx * BAND_MAX + coeff_idx) * 3108 sizeof(uint32_t)) & 0x7F); 3109 3110 value |= snd_soc_component_read(component, b2_reg); 3111 snd_soc_component_write(component, reg, 3112 ((band_idx * BAND_MAX + coeff_idx) 3113 * sizeof(uint32_t) + 1) & 0x7F); 3114 3115 value |= (snd_soc_component_read(component, b2_reg) << 8); 3116 snd_soc_component_write(component, reg, 3117 ((band_idx * BAND_MAX + coeff_idx) 3118 * sizeof(uint32_t) + 2) & 0x7F); 3119 3120 value |= (snd_soc_component_read(component, b2_reg) << 16); 3121 snd_soc_component_write(component, reg, 3122 ((band_idx * BAND_MAX + coeff_idx) 3123 * sizeof(uint32_t) + 3) & 0x7F); 3124 3125 /* Mask bits top 2 bits since they are reserved */ 3126 value |= (snd_soc_component_read(component, b2_reg) << 24); 3127 return value; 3128 } 3129 3130 static void set_iir_band_coeff(struct snd_soc_component *component, 3131 int iir_idx, int band_idx, uint32_t value) 3132 { 3133 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx; 3134 3135 snd_soc_component_write(component, reg, (value & 0xFF)); 3136 snd_soc_component_write(component, reg, (value >> 8) & 0xFF); 3137 snd_soc_component_write(component, reg, (value >> 16) & 0xFF); 3138 /* Mask top 2 bits, 7-8 are reserved */ 3139 snd_soc_component_write(component, reg, (value >> 24) & 0x3F); 3140 } 3141 3142 static int wcd934x_put_iir_band_audio_mixer( 3143 struct snd_kcontrol *kcontrol, 3144 struct snd_ctl_elem_value *ucontrol) 3145 { 3146 struct snd_soc_component *component = 3147 snd_soc_kcontrol_component(kcontrol); 3148 struct wcd_iir_filter_ctl *ctl = 3149 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3150 struct soc_bytes_ext *params = &ctl->bytes_ext; 3151 int iir_idx = ctl->iir_idx; 3152 int band_idx = ctl->band_idx; 3153 u32 coeff[BAND_MAX]; 3154 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx; 3155 3156 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max); 3157 3158 /* Mask top bit it is reserved */ 3159 /* Updates addr automatically for each B2 write */ 3160 snd_soc_component_write(component, reg, (band_idx * BAND_MAX * 3161 sizeof(uint32_t)) & 0x7F); 3162 3163 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]); 3164 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]); 3165 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]); 3166 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]); 3167 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]); 3168 3169 return 0; 3170 } 3171 3172 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol, 3173 struct snd_ctl_elem_value *ucontrol) 3174 { 3175 struct snd_soc_component *component = 3176 snd_soc_kcontrol_component(kcontrol); 3177 struct wcd_iir_filter_ctl *ctl = 3178 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3179 struct soc_bytes_ext *params = &ctl->bytes_ext; 3180 int iir_idx = ctl->iir_idx; 3181 int band_idx = ctl->band_idx; 3182 u32 coeff[BAND_MAX]; 3183 3184 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0); 3185 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1); 3186 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2); 3187 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3); 3188 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4); 3189 3190 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max); 3191 3192 return 0; 3193 } 3194 3195 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol, 3196 struct snd_ctl_elem_info *ucontrol) 3197 { 3198 struct wcd_iir_filter_ctl *ctl = 3199 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3200 struct soc_bytes_ext *params = &ctl->bytes_ext; 3201 3202 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 3203 ucontrol->count = params->max; 3204 3205 return 0; 3206 } 3207 3208 static int wcd934x_compander_get(struct snd_kcontrol *kc, 3209 struct snd_ctl_elem_value *ucontrol) 3210 { 3211 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3212 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 3213 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3214 3215 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp]; 3216 3217 return 0; 3218 } 3219 3220 static int wcd934x_compander_set(struct snd_kcontrol *kc, 3221 struct snd_ctl_elem_value *ucontrol) 3222 { 3223 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3224 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3225 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 3226 int value = ucontrol->value.integer.value[0]; 3227 int sel; 3228 3229 if (wcd->comp_enabled[comp] == value) 3230 return 0; 3231 3232 wcd->comp_enabled[comp] = value; 3233 sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER : 3234 WCD934X_HPH_GAIN_SRC_SEL_REGISTER; 3235 3236 /* Any specific register configuration for compander */ 3237 switch (comp) { 3238 case COMPANDER_1: 3239 /* Set Gain Source Select based on compander enable/disable */ 3240 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN, 3241 WCD934X_HPH_GAIN_SRC_SEL_MASK, 3242 sel); 3243 break; 3244 case COMPANDER_2: 3245 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN, 3246 WCD934X_HPH_GAIN_SRC_SEL_MASK, 3247 sel); 3248 break; 3249 case COMPANDER_3: 3250 case COMPANDER_4: 3251 case COMPANDER_7: 3252 case COMPANDER_8: 3253 break; 3254 default: 3255 return 0; 3256 } 3257 3258 return 1; 3259 } 3260 3261 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc, 3262 struct snd_ctl_elem_value *ucontrol) 3263 { 3264 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3265 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3266 3267 ucontrol->value.enumerated.item[0] = wcd->hph_mode; 3268 3269 return 0; 3270 } 3271 3272 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc, 3273 struct snd_ctl_elem_value *ucontrol) 3274 { 3275 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3276 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3277 u32 mode_val; 3278 3279 mode_val = ucontrol->value.enumerated.item[0]; 3280 3281 if (mode_val == wcd->hph_mode) 3282 return 0; 3283 3284 if (mode_val == 0) { 3285 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n"); 3286 mode_val = CLS_H_LOHIFI; 3287 } 3288 wcd->hph_mode = mode_val; 3289 3290 return 1; 3291 } 3292 3293 static int slim_rx_mux_get(struct snd_kcontrol *kc, 3294 struct snd_ctl_elem_value *ucontrol) 3295 { 3296 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 3297 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 3298 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev); 3299 3300 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift]; 3301 3302 return 0; 3303 } 3304 3305 static int slim_rx_mux_to_dai_id(int mux) 3306 { 3307 int aif_id; 3308 3309 switch (mux) { 3310 case 1: 3311 aif_id = AIF1_PB; 3312 break; 3313 case 2: 3314 aif_id = AIF2_PB; 3315 break; 3316 case 3: 3317 aif_id = AIF3_PB; 3318 break; 3319 case 4: 3320 aif_id = AIF4_PB; 3321 break; 3322 default: 3323 aif_id = -1; 3324 break; 3325 } 3326 3327 return aif_id; 3328 } 3329 3330 static int slim_rx_mux_put(struct snd_kcontrol *kc, 3331 struct snd_ctl_elem_value *ucontrol) 3332 { 3333 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 3334 struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev); 3335 struct soc_enum *e = (struct soc_enum *)kc->private_value; 3336 struct snd_soc_dapm_update *update = NULL; 3337 struct wcd934x_slim_ch *ch, *c; 3338 u32 port_id = w->shift; 3339 bool found = false; 3340 int mux_idx; 3341 int prev_mux_idx = wcd->rx_port_value[port_id]; 3342 int aif_id; 3343 3344 mux_idx = ucontrol->value.enumerated.item[0]; 3345 3346 if (mux_idx == prev_mux_idx) 3347 return 0; 3348 3349 switch(mux_idx) { 3350 case 0: 3351 aif_id = slim_rx_mux_to_dai_id(prev_mux_idx); 3352 if (aif_id < 0) 3353 return 0; 3354 3355 list_for_each_entry_safe(ch, c, &wcd->dai[aif_id].slim_ch_list, list) { 3356 if (ch->port == port_id + WCD934X_RX_START) { 3357 found = true; 3358 list_del_init(&ch->list); 3359 break; 3360 } 3361 } 3362 if (!found) 3363 return 0; 3364 3365 break; 3366 case 1 ... 4: 3367 aif_id = slim_rx_mux_to_dai_id(mux_idx); 3368 if (aif_id < 0) 3369 return 0; 3370 3371 if (list_empty(&wcd->rx_chs[port_id].list)) { 3372 list_add_tail(&wcd->rx_chs[port_id].list, 3373 &wcd->dai[aif_id].slim_ch_list); 3374 } else { 3375 dev_err(wcd->dev ,"SLIM_RX%d PORT is busy\n", port_id); 3376 return 0; 3377 } 3378 break; 3379 3380 default: 3381 dev_err(wcd->dev, "Unknown AIF %d\n", mux_idx); 3382 goto err; 3383 } 3384 3385 wcd->rx_port_value[port_id] = mux_idx; 3386 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id], 3387 e, update); 3388 3389 return 1; 3390 err: 3391 return -EINVAL; 3392 } 3393 3394 static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc, 3395 struct snd_ctl_elem_value *ucontrol) 3396 { 3397 struct soc_enum *e = (struct soc_enum *)kc->private_value; 3398 struct snd_soc_component *component; 3399 int reg, val; 3400 3401 component = snd_soc_dapm_kcontrol_component(kc); 3402 val = ucontrol->value.enumerated.item[0]; 3403 if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0) 3404 reg = WCD934X_CDC_RX0_RX_PATH_CFG0; 3405 else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0) 3406 reg = WCD934X_CDC_RX1_RX_PATH_CFG0; 3407 else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0) 3408 reg = WCD934X_CDC_RX2_RX_PATH_CFG0; 3409 else 3410 return -EINVAL; 3411 3412 /* Set Look Ahead Delay */ 3413 if (val) 3414 snd_soc_component_update_bits(component, reg, 3415 WCD934X_RX_DLY_ZN_EN_MASK, 3416 WCD934X_RX_DLY_ZN_ENABLE); 3417 else 3418 snd_soc_component_update_bits(component, reg, 3419 WCD934X_RX_DLY_ZN_EN_MASK, 3420 WCD934X_RX_DLY_ZN_DISABLE); 3421 3422 return snd_soc_dapm_put_enum_double(kc, ucontrol); 3423 } 3424 3425 static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol, 3426 struct snd_ctl_elem_value *ucontrol) 3427 { 3428 struct snd_soc_component *comp; 3429 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 3430 unsigned int val; 3431 u16 mic_sel_reg = 0; 3432 u8 mic_sel; 3433 3434 comp = snd_soc_dapm_kcontrol_component(kcontrol); 3435 3436 val = ucontrol->value.enumerated.item[0]; 3437 if (val > e->items - 1) 3438 return -EINVAL; 3439 3440 switch (e->reg) { 3441 case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1: 3442 if (e->shift_l == 0) 3443 mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0; 3444 else if (e->shift_l == 2) 3445 mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0; 3446 else if (e->shift_l == 4) 3447 mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0; 3448 break; 3449 case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1: 3450 if (e->shift_l == 0) 3451 mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0; 3452 else if (e->shift_l == 2) 3453 mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0; 3454 break; 3455 case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1: 3456 if (e->shift_l == 0) 3457 mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0; 3458 else if (e->shift_l == 2) 3459 mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0; 3460 break; 3461 case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1: 3462 if (e->shift_l == 0) 3463 mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0; 3464 else if (e->shift_l == 2) 3465 mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0; 3466 break; 3467 default: 3468 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n", 3469 __func__, e->reg); 3470 return -EINVAL; 3471 } 3472 3473 /* ADC: 0, DMIC: 1 */ 3474 mic_sel = val ? 0x0 : 0x1; 3475 if (mic_sel_reg) 3476 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7), 3477 mic_sel << 7); 3478 3479 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 3480 } 3481 3482 static const struct snd_kcontrol_new rx_int0_2_mux = 3483 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum); 3484 3485 static const struct snd_kcontrol_new rx_int1_2_mux = 3486 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum); 3487 3488 static const struct snd_kcontrol_new rx_int2_2_mux = 3489 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum); 3490 3491 static const struct snd_kcontrol_new rx_int3_2_mux = 3492 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum); 3493 3494 static const struct snd_kcontrol_new rx_int4_2_mux = 3495 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum); 3496 3497 static const struct snd_kcontrol_new rx_int7_2_mux = 3498 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum); 3499 3500 static const struct snd_kcontrol_new rx_int8_2_mux = 3501 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum); 3502 3503 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 3504 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum); 3505 3506 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 3507 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum); 3508 3509 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 3510 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum); 3511 3512 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 3513 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum); 3514 3515 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 3516 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum); 3517 3518 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 3519 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum); 3520 3521 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 3522 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum); 3523 3524 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 3525 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum); 3526 3527 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 3528 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum); 3529 3530 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux = 3531 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum); 3532 3533 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux = 3534 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum); 3535 3536 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux = 3537 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum); 3538 3539 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux = 3540 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum); 3541 3542 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux = 3543 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum); 3544 3545 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux = 3546 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum); 3547 3548 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux = 3549 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum); 3550 3551 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux = 3552 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum); 3553 3554 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux = 3555 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum); 3556 3557 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux = 3558 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum); 3559 3560 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux = 3561 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum); 3562 3563 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux = 3564 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum); 3565 3566 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux = 3567 SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum); 3568 3569 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux = 3570 SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum); 3571 3572 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux = 3573 SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum); 3574 3575 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux = 3576 SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum); 3577 3578 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux = 3579 SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum); 3580 3581 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux = 3582 SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum); 3583 3584 static const struct snd_kcontrol_new iir0_inp0_mux = 3585 SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum); 3586 static const struct snd_kcontrol_new iir0_inp1_mux = 3587 SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum); 3588 static const struct snd_kcontrol_new iir0_inp2_mux = 3589 SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum); 3590 static const struct snd_kcontrol_new iir0_inp3_mux = 3591 SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum); 3592 3593 static const struct snd_kcontrol_new iir1_inp0_mux = 3594 SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum); 3595 static const struct snd_kcontrol_new iir1_inp1_mux = 3596 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum); 3597 static const struct snd_kcontrol_new iir1_inp2_mux = 3598 SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum); 3599 static const struct snd_kcontrol_new iir1_inp3_mux = 3600 SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum); 3601 3602 static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = { 3603 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum, 3604 slim_rx_mux_get, slim_rx_mux_put), 3605 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum, 3606 slim_rx_mux_get, slim_rx_mux_put), 3607 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum, 3608 slim_rx_mux_get, slim_rx_mux_put), 3609 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum, 3610 slim_rx_mux_get, slim_rx_mux_put), 3611 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum, 3612 slim_rx_mux_get, slim_rx_mux_put), 3613 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum, 3614 slim_rx_mux_get, slim_rx_mux_put), 3615 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum, 3616 slim_rx_mux_get, slim_rx_mux_put), 3617 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum, 3618 slim_rx_mux_get, slim_rx_mux_put), 3619 }; 3620 3621 static const struct snd_kcontrol_new rx_int1_asrc_switch[] = { 3622 SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0), 3623 }; 3624 3625 static const struct snd_kcontrol_new rx_int2_asrc_switch[] = { 3626 SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0), 3627 }; 3628 3629 static const struct snd_kcontrol_new rx_int3_asrc_switch[] = { 3630 SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0), 3631 }; 3632 3633 static const struct snd_kcontrol_new rx_int4_asrc_switch[] = { 3634 SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0), 3635 }; 3636 3637 static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 3638 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum, 3639 snd_soc_dapm_get_enum_double, 3640 wcd934x_int_dem_inp_mux_put); 3641 3642 static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 3643 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum, 3644 snd_soc_dapm_get_enum_double, 3645 wcd934x_int_dem_inp_mux_put); 3646 3647 static const struct snd_kcontrol_new rx_int2_dem_inp_mux = 3648 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum, 3649 snd_soc_dapm_get_enum_double, 3650 wcd934x_int_dem_inp_mux_put); 3651 3652 static const struct snd_kcontrol_new rx_int0_1_interp_mux = 3653 SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum); 3654 3655 static const struct snd_kcontrol_new rx_int1_1_interp_mux = 3656 SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum); 3657 3658 static const struct snd_kcontrol_new rx_int2_1_interp_mux = 3659 SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum); 3660 3661 static const struct snd_kcontrol_new rx_int3_1_interp_mux = 3662 SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum); 3663 3664 static const struct snd_kcontrol_new rx_int4_1_interp_mux = 3665 SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum); 3666 3667 static const struct snd_kcontrol_new rx_int7_1_interp_mux = 3668 SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum); 3669 3670 static const struct snd_kcontrol_new rx_int8_1_interp_mux = 3671 SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum); 3672 3673 static const struct snd_kcontrol_new rx_int0_2_interp_mux = 3674 SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum); 3675 3676 static const struct snd_kcontrol_new rx_int1_2_interp_mux = 3677 SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum); 3678 3679 static const struct snd_kcontrol_new rx_int2_2_interp_mux = 3680 SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum); 3681 3682 static const struct snd_kcontrol_new rx_int3_2_interp_mux = 3683 SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum); 3684 3685 static const struct snd_kcontrol_new rx_int4_2_interp_mux = 3686 SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum); 3687 3688 static const struct snd_kcontrol_new rx_int7_2_interp_mux = 3689 SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum); 3690 3691 static const struct snd_kcontrol_new rx_int8_2_interp_mux = 3692 SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum); 3693 3694 static const struct snd_kcontrol_new tx_dmic_mux0 = 3695 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum); 3696 3697 static const struct snd_kcontrol_new tx_dmic_mux1 = 3698 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum); 3699 3700 static const struct snd_kcontrol_new tx_dmic_mux2 = 3701 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum); 3702 3703 static const struct snd_kcontrol_new tx_dmic_mux3 = 3704 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum); 3705 3706 static const struct snd_kcontrol_new tx_dmic_mux4 = 3707 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum); 3708 3709 static const struct snd_kcontrol_new tx_dmic_mux5 = 3710 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum); 3711 3712 static const struct snd_kcontrol_new tx_dmic_mux6 = 3713 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum); 3714 3715 static const struct snd_kcontrol_new tx_dmic_mux7 = 3716 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum); 3717 3718 static const struct snd_kcontrol_new tx_dmic_mux8 = 3719 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum); 3720 3721 static const struct snd_kcontrol_new tx_amic_mux0 = 3722 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum); 3723 3724 static const struct snd_kcontrol_new tx_amic_mux1 = 3725 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum); 3726 3727 static const struct snd_kcontrol_new tx_amic_mux2 = 3728 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum); 3729 3730 static const struct snd_kcontrol_new tx_amic_mux3 = 3731 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum); 3732 3733 static const struct snd_kcontrol_new tx_amic_mux4 = 3734 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum); 3735 3736 static const struct snd_kcontrol_new tx_amic_mux5 = 3737 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum); 3738 3739 static const struct snd_kcontrol_new tx_amic_mux6 = 3740 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum); 3741 3742 static const struct snd_kcontrol_new tx_amic_mux7 = 3743 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum); 3744 3745 static const struct snd_kcontrol_new tx_amic_mux8 = 3746 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum); 3747 3748 static const struct snd_kcontrol_new tx_amic4_5 = 3749 SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum); 3750 3751 static const struct snd_kcontrol_new tx_adc_mux0_mux = 3752 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum, 3753 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3754 static const struct snd_kcontrol_new tx_adc_mux1_mux = 3755 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum, 3756 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3757 static const struct snd_kcontrol_new tx_adc_mux2_mux = 3758 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum, 3759 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3760 static const struct snd_kcontrol_new tx_adc_mux3_mux = 3761 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum, 3762 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3763 static const struct snd_kcontrol_new tx_adc_mux4_mux = 3764 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum, 3765 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3766 static const struct snd_kcontrol_new tx_adc_mux5_mux = 3767 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum, 3768 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3769 static const struct snd_kcontrol_new tx_adc_mux6_mux = 3770 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum, 3771 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3772 static const struct snd_kcontrol_new tx_adc_mux7_mux = 3773 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum, 3774 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3775 static const struct snd_kcontrol_new tx_adc_mux8_mux = 3776 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum, 3777 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3778 3779 static const struct snd_kcontrol_new cdc_if_tx0_mux = 3780 SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum); 3781 static const struct snd_kcontrol_new cdc_if_tx1_mux = 3782 SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum); 3783 static const struct snd_kcontrol_new cdc_if_tx2_mux = 3784 SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum); 3785 static const struct snd_kcontrol_new cdc_if_tx3_mux = 3786 SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum); 3787 static const struct snd_kcontrol_new cdc_if_tx4_mux = 3788 SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum); 3789 static const struct snd_kcontrol_new cdc_if_tx5_mux = 3790 SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum); 3791 static const struct snd_kcontrol_new cdc_if_tx6_mux = 3792 SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum); 3793 static const struct snd_kcontrol_new cdc_if_tx7_mux = 3794 SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum); 3795 static const struct snd_kcontrol_new cdc_if_tx8_mux = 3796 SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum); 3797 static const struct snd_kcontrol_new cdc_if_tx9_mux = 3798 SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum); 3799 static const struct snd_kcontrol_new cdc_if_tx10_mux = 3800 SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum); 3801 static const struct snd_kcontrol_new cdc_if_tx11_mux = 3802 SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum); 3803 static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux = 3804 SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum); 3805 static const struct snd_kcontrol_new cdc_if_tx13_mux = 3806 SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum); 3807 static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux = 3808 SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum); 3809 3810 static int slim_tx_mixer_get(struct snd_kcontrol *kc, 3811 struct snd_ctl_elem_value *ucontrol) 3812 { 3813 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 3814 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev); 3815 struct soc_mixer_control *mixer = 3816 (struct soc_mixer_control *)kc->private_value; 3817 int port_id = mixer->shift; 3818 3819 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id]; 3820 3821 return 0; 3822 } 3823 3824 static int slim_tx_mixer_put(struct snd_kcontrol *kc, 3825 struct snd_ctl_elem_value *ucontrol) 3826 { 3827 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc); 3828 struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev); 3829 struct snd_soc_dapm_update *update = NULL; 3830 struct soc_mixer_control *mixer = 3831 (struct soc_mixer_control *)kc->private_value; 3832 int enable = ucontrol->value.integer.value[0]; 3833 struct wcd934x_slim_ch *ch, *c; 3834 int dai_id = widget->shift; 3835 int port_id = mixer->shift; 3836 3837 /* only add to the list if value not set */ 3838 if (enable == wcd->tx_port_value[port_id]) 3839 return 0; 3840 3841 if (enable) { 3842 if (list_empty(&wcd->tx_chs[port_id].list)) { 3843 list_add_tail(&wcd->tx_chs[port_id].list, 3844 &wcd->dai[dai_id].slim_ch_list); 3845 } else { 3846 dev_err(wcd->dev ,"SLIM_TX%d PORT is busy\n", port_id); 3847 return 0; 3848 } 3849 } else { 3850 bool found = false; 3851 3852 list_for_each_entry_safe(ch, c, &wcd->dai[dai_id].slim_ch_list, list) { 3853 if (ch->port == port_id) { 3854 found = true; 3855 list_del_init(&wcd->tx_chs[port_id].list); 3856 break; 3857 } 3858 } 3859 if (!found) 3860 return 0; 3861 } 3862 3863 wcd->tx_port_value[port_id] = enable; 3864 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update); 3865 3866 return 1; 3867 } 3868 3869 static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = { 3870 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3871 slim_tx_mixer_get, slim_tx_mixer_put), 3872 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3873 slim_tx_mixer_get, slim_tx_mixer_put), 3874 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3875 slim_tx_mixer_get, slim_tx_mixer_put), 3876 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3877 slim_tx_mixer_get, slim_tx_mixer_put), 3878 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3879 slim_tx_mixer_get, slim_tx_mixer_put), 3880 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3881 slim_tx_mixer_get, slim_tx_mixer_put), 3882 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3883 slim_tx_mixer_get, slim_tx_mixer_put), 3884 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3885 slim_tx_mixer_get, slim_tx_mixer_put), 3886 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3887 slim_tx_mixer_get, slim_tx_mixer_put), 3888 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3889 slim_tx_mixer_get, slim_tx_mixer_put), 3890 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3891 slim_tx_mixer_get, slim_tx_mixer_put), 3892 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3893 slim_tx_mixer_get, slim_tx_mixer_put), 3894 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3895 slim_tx_mixer_get, slim_tx_mixer_put), 3896 }; 3897 3898 static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = { 3899 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3900 slim_tx_mixer_get, slim_tx_mixer_put), 3901 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3902 slim_tx_mixer_get, slim_tx_mixer_put), 3903 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3904 slim_tx_mixer_get, slim_tx_mixer_put), 3905 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3906 slim_tx_mixer_get, slim_tx_mixer_put), 3907 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3908 slim_tx_mixer_get, slim_tx_mixer_put), 3909 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3910 slim_tx_mixer_get, slim_tx_mixer_put), 3911 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3912 slim_tx_mixer_get, slim_tx_mixer_put), 3913 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3914 slim_tx_mixer_get, slim_tx_mixer_put), 3915 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3916 slim_tx_mixer_get, slim_tx_mixer_put), 3917 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3918 slim_tx_mixer_get, slim_tx_mixer_put), 3919 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3920 slim_tx_mixer_get, slim_tx_mixer_put), 3921 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3922 slim_tx_mixer_get, slim_tx_mixer_put), 3923 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3924 slim_tx_mixer_get, slim_tx_mixer_put), 3925 }; 3926 3927 static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = { 3928 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3929 slim_tx_mixer_get, slim_tx_mixer_put), 3930 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3931 slim_tx_mixer_get, slim_tx_mixer_put), 3932 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3933 slim_tx_mixer_get, slim_tx_mixer_put), 3934 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3935 slim_tx_mixer_get, slim_tx_mixer_put), 3936 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3937 slim_tx_mixer_get, slim_tx_mixer_put), 3938 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3939 slim_tx_mixer_get, slim_tx_mixer_put), 3940 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3941 slim_tx_mixer_get, slim_tx_mixer_put), 3942 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3943 slim_tx_mixer_get, slim_tx_mixer_put), 3944 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3945 slim_tx_mixer_get, slim_tx_mixer_put), 3946 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3947 slim_tx_mixer_get, slim_tx_mixer_put), 3948 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3949 slim_tx_mixer_get, slim_tx_mixer_put), 3950 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3951 slim_tx_mixer_get, slim_tx_mixer_put), 3952 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3953 slim_tx_mixer_get, slim_tx_mixer_put), 3954 }; 3955 3956 static const struct snd_kcontrol_new wcd934x_snd_controls[] = { 3957 /* Gain Controls */ 3958 SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain), 3959 SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain), 3960 SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain), 3961 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER, 3962 3, 16, 1, line_gain), 3963 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER, 3964 3, 16, 1, line_gain), 3965 3966 SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain), 3967 SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain), 3968 SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain), 3969 SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain), 3970 3971 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL, 3972 -84, 40, digital_gain), /* -84dB min - 40dB max */ 3973 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL, 3974 -84, 40, digital_gain), 3975 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL, 3976 -84, 40, digital_gain), 3977 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL, 3978 -84, 40, digital_gain), 3979 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL, 3980 -84, 40, digital_gain), 3981 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL, 3982 -84, 40, digital_gain), 3983 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL, 3984 -84, 40, digital_gain), 3985 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", 3986 WCD934X_CDC_RX0_RX_VOL_MIX_CTL, 3987 -84, 40, digital_gain), 3988 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", 3989 WCD934X_CDC_RX1_RX_VOL_MIX_CTL, 3990 -84, 40, digital_gain), 3991 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", 3992 WCD934X_CDC_RX2_RX_VOL_MIX_CTL, 3993 -84, 40, digital_gain), 3994 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", 3995 WCD934X_CDC_RX3_RX_VOL_MIX_CTL, 3996 -84, 40, digital_gain), 3997 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", 3998 WCD934X_CDC_RX4_RX_VOL_MIX_CTL, 3999 -84, 40, digital_gain), 4000 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", 4001 WCD934X_CDC_RX7_RX_VOL_MIX_CTL, 4002 -84, 40, digital_gain), 4003 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", 4004 WCD934X_CDC_RX8_RX_VOL_MIX_CTL, 4005 -84, 40, digital_gain), 4006 4007 SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL, 4008 -84, 40, digital_gain), 4009 SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL, 4010 -84, 40, digital_gain), 4011 SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL, 4012 -84, 40, digital_gain), 4013 SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL, 4014 -84, 40, digital_gain), 4015 SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL, 4016 -84, 40, digital_gain), 4017 SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL, 4018 -84, 40, digital_gain), 4019 SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL, 4020 -84, 40, digital_gain), 4021 SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL, 4022 -84, 40, digital_gain), 4023 SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL, 4024 -84, 40, digital_gain), 4025 4026 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume", 4027 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40, 4028 digital_gain), 4029 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume", 4030 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40, 4031 digital_gain), 4032 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume", 4033 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40, 4034 digital_gain), 4035 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume", 4036 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40, 4037 digital_gain), 4038 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume", 4039 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40, 4040 digital_gain), 4041 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", 4042 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40, 4043 digital_gain), 4044 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", 4045 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40, 4046 digital_gain), 4047 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", 4048 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40, 4049 digital_gain), 4050 4051 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum), 4052 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), 4053 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), 4054 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), 4055 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), 4056 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum), 4057 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum), 4058 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum), 4059 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum), 4060 4061 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum), 4062 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum), 4063 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum), 4064 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum), 4065 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum), 4066 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum), 4067 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum), 4068 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum), 4069 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum), 4070 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum), 4071 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum), 4072 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum), 4073 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum), 4074 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum), 4075 4076 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 4077 wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put), 4078 4079 SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4080 0, 1, 0), 4081 SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4082 1, 1, 0), 4083 SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4084 2, 1, 0), 4085 SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4086 3, 1, 0), 4087 SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4088 4, 1, 0), 4089 SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4090 0, 1, 0), 4091 SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4092 1, 1, 0), 4093 SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4094 2, 1, 0), 4095 SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4096 3, 1, 0), 4097 SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4098 4, 1, 0), 4099 WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1), 4100 WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2), 4101 WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3), 4102 WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4), 4103 WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5), 4104 4105 WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1), 4106 WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2), 4107 WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3), 4108 WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4), 4109 WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5), 4110 4111 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0, 4112 wcd934x_compander_get, wcd934x_compander_set), 4113 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0, 4114 wcd934x_compander_get, wcd934x_compander_set), 4115 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0, 4116 wcd934x_compander_get, wcd934x_compander_set), 4117 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0, 4118 wcd934x_compander_get, wcd934x_compander_set), 4119 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0, 4120 wcd934x_compander_get, wcd934x_compander_set), 4121 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0, 4122 wcd934x_compander_get, wcd934x_compander_set), 4123 }; 4124 4125 static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai, 4126 struct snd_soc_component *component) 4127 { 4128 int port_num = 0; 4129 unsigned short reg = 0; 4130 unsigned int val = 0; 4131 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 4132 struct wcd934x_slim_ch *ch; 4133 4134 list_for_each_entry(ch, &dai->slim_ch_list, list) { 4135 if (ch->port >= WCD934X_RX_START) { 4136 port_num = ch->port - WCD934X_RX_START; 4137 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); 4138 } else { 4139 port_num = ch->port; 4140 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); 4141 } 4142 4143 regmap_read(wcd->if_regmap, reg, &val); 4144 if (!(val & BIT(port_num % 8))) 4145 regmap_write(wcd->if_regmap, reg, 4146 val | BIT(port_num % 8)); 4147 } 4148 } 4149 4150 static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w, 4151 struct snd_kcontrol *kc, int event) 4152 { 4153 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4154 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4155 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift]; 4156 4157 switch (event) { 4158 case SND_SOC_DAPM_POST_PMU: 4159 wcd934x_codec_enable_int_port(dai, comp); 4160 break; 4161 } 4162 4163 return 0; 4164 } 4165 4166 static void wcd934x_codec_hd2_control(struct snd_soc_component *component, 4167 u16 interp_idx, int event) 4168 { 4169 u16 hd2_scale_reg; 4170 u16 hd2_enable_reg = 0; 4171 4172 switch (interp_idx) { 4173 case INTERP_HPHL: 4174 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3; 4175 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0; 4176 break; 4177 case INTERP_HPHR: 4178 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3; 4179 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0; 4180 break; 4181 default: 4182 return; 4183 } 4184 4185 if (SND_SOC_DAPM_EVENT_ON(event)) { 4186 snd_soc_component_update_bits(component, hd2_scale_reg, 4187 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 4188 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125); 4189 snd_soc_component_update_bits(component, hd2_enable_reg, 4190 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK, 4191 WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE); 4192 } 4193 4194 if (SND_SOC_DAPM_EVENT_OFF(event)) { 4195 snd_soc_component_update_bits(component, hd2_enable_reg, 4196 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK, 4197 WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE); 4198 snd_soc_component_update_bits(component, hd2_scale_reg, 4199 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 4200 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000); 4201 } 4202 } 4203 4204 static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp, 4205 u16 interp_idx, int event) 4206 { 4207 u8 hph_dly_mask; 4208 u16 hph_lut_bypass_reg = 0; 4209 4210 switch (interp_idx) { 4211 case INTERP_HPHL: 4212 hph_dly_mask = 1; 4213 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT; 4214 break; 4215 case INTERP_HPHR: 4216 hph_dly_mask = 2; 4217 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT; 4218 break; 4219 default: 4220 return; 4221 } 4222 4223 if (SND_SOC_DAPM_EVENT_ON(event)) { 4224 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0, 4225 hph_dly_mask, 0x0); 4226 snd_soc_component_update_bits(comp, hph_lut_bypass_reg, 4227 WCD934X_HPH_LUT_BYPASS_MASK, 4228 WCD934X_HPH_LUT_BYPASS_ENABLE); 4229 } 4230 4231 if (SND_SOC_DAPM_EVENT_OFF(event)) { 4232 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0, 4233 hph_dly_mask, hph_dly_mask); 4234 snd_soc_component_update_bits(comp, hph_lut_bypass_reg, 4235 WCD934X_HPH_LUT_BYPASS_MASK, 4236 WCD934X_HPH_LUT_BYPASS_DISABLE); 4237 } 4238 } 4239 4240 static int wcd934x_config_compander(struct snd_soc_component *comp, 4241 int interp_n, int event) 4242 { 4243 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4244 int compander; 4245 u16 comp_ctl0_reg, rx_path_cfg0_reg; 4246 4247 /* EAR does not have compander */ 4248 if (!interp_n) 4249 return 0; 4250 4251 compander = interp_n - 1; 4252 if (!wcd->comp_enabled[compander]) 4253 return 0; 4254 4255 comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8); 4256 rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20); 4257 4258 switch (event) { 4259 case SND_SOC_DAPM_PRE_PMU: 4260 /* Enable Compander Clock */ 4261 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4262 WCD934X_COMP_CLK_EN_MASK, 4263 WCD934X_COMP_CLK_ENABLE); 4264 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4265 WCD934X_COMP_SOFT_RST_MASK, 4266 WCD934X_COMP_SOFT_RST_ENABLE); 4267 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4268 WCD934X_COMP_SOFT_RST_MASK, 4269 WCD934X_COMP_SOFT_RST_DISABLE); 4270 snd_soc_component_update_bits(comp, rx_path_cfg0_reg, 4271 WCD934X_HPH_CMP_EN_MASK, 4272 WCD934X_HPH_CMP_ENABLE); 4273 break; 4274 case SND_SOC_DAPM_POST_PMD: 4275 snd_soc_component_update_bits(comp, rx_path_cfg0_reg, 4276 WCD934X_HPH_CMP_EN_MASK, 4277 WCD934X_HPH_CMP_DISABLE); 4278 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4279 WCD934X_COMP_HALT_MASK, 4280 WCD934X_COMP_HALT); 4281 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4282 WCD934X_COMP_SOFT_RST_MASK, 4283 WCD934X_COMP_SOFT_RST_ENABLE); 4284 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4285 WCD934X_COMP_SOFT_RST_MASK, 4286 WCD934X_COMP_SOFT_RST_DISABLE); 4287 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4288 WCD934X_COMP_CLK_EN_MASK, 0x0); 4289 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4290 WCD934X_COMP_SOFT_RST_MASK, 0x0); 4291 break; 4292 } 4293 4294 return 0; 4295 } 4296 4297 static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w, 4298 struct snd_kcontrol *kc, int event) 4299 { 4300 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4301 int interp_idx = w->shift; 4302 u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20); 4303 4304 switch (event) { 4305 case SND_SOC_DAPM_PRE_PMU: 4306 /* Clk enable */ 4307 snd_soc_component_update_bits(comp, main_reg, 4308 WCD934X_RX_CLK_EN_MASK, 4309 WCD934X_RX_CLK_ENABLE); 4310 wcd934x_codec_hd2_control(comp, interp_idx, event); 4311 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event); 4312 wcd934x_config_compander(comp, interp_idx, event); 4313 break; 4314 case SND_SOC_DAPM_POST_PMD: 4315 wcd934x_config_compander(comp, interp_idx, event); 4316 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event); 4317 wcd934x_codec_hd2_control(comp, interp_idx, event); 4318 /* Clk Disable */ 4319 snd_soc_component_update_bits(comp, main_reg, 4320 WCD934X_RX_CLK_EN_MASK, 0); 4321 /* Reset enable and disable */ 4322 snd_soc_component_update_bits(comp, main_reg, 4323 WCD934X_RX_RESET_MASK, 4324 WCD934X_RX_RESET_ENABLE); 4325 snd_soc_component_update_bits(comp, main_reg, 4326 WCD934X_RX_RESET_MASK, 4327 WCD934X_RX_RESET_DISABLE); 4328 /* Reset rate to 48K*/ 4329 snd_soc_component_update_bits(comp, main_reg, 4330 WCD934X_RX_PCM_RATE_MASK, 4331 WCD934X_RX_PCM_RATE_F_48K); 4332 break; 4333 } 4334 4335 return 0; 4336 } 4337 4338 static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w, 4339 struct snd_kcontrol *kc, int event) 4340 { 4341 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4342 int offset_val = 0; 4343 u16 gain_reg, mix_reg; 4344 int val = 0; 4345 4346 gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL + 4347 (w->shift * WCD934X_RX_PATH_CTL_OFFSET); 4348 mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL + 4349 (w->shift * WCD934X_RX_PATH_CTL_OFFSET); 4350 4351 switch (event) { 4352 case SND_SOC_DAPM_PRE_PMU: 4353 /* Clk enable */ 4354 snd_soc_component_update_bits(comp, mix_reg, 4355 WCD934X_CDC_RX_MIX_CLK_EN_MASK, 4356 WCD934X_CDC_RX_MIX_CLK_ENABLE); 4357 break; 4358 4359 case SND_SOC_DAPM_POST_PMU: 4360 val = snd_soc_component_read(comp, gain_reg); 4361 val += offset_val; 4362 snd_soc_component_write(comp, gain_reg, val); 4363 break; 4364 } 4365 4366 return 0; 4367 } 4368 4369 static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w, 4370 struct snd_kcontrol *kcontrol, int event) 4371 { 4372 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4373 int reg = w->reg; 4374 4375 switch (event) { 4376 case SND_SOC_DAPM_POST_PMU: 4377 /* B1 GAIN */ 4378 snd_soc_component_write(comp, reg, 4379 snd_soc_component_read(comp, reg)); 4380 /* B2 GAIN */ 4381 reg++; 4382 snd_soc_component_write(comp, reg, 4383 snd_soc_component_read(comp, reg)); 4384 /* B3 GAIN */ 4385 reg++; 4386 snd_soc_component_write(comp, reg, 4387 snd_soc_component_read(comp, reg)); 4388 /* B4 GAIN */ 4389 reg++; 4390 snd_soc_component_write(comp, reg, 4391 snd_soc_component_read(comp, reg)); 4392 /* B5 GAIN */ 4393 reg++; 4394 snd_soc_component_write(comp, reg, 4395 snd_soc_component_read(comp, reg)); 4396 break; 4397 default: 4398 break; 4399 } 4400 return 0; 4401 } 4402 4403 static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w, 4404 struct snd_kcontrol *kcontrol, 4405 int event) 4406 { 4407 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4408 u16 gain_reg; 4409 4410 gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift * 4411 WCD934X_RX_PATH_CTL_OFFSET); 4412 4413 switch (event) { 4414 case SND_SOC_DAPM_POST_PMU: 4415 snd_soc_component_write(comp, gain_reg, 4416 snd_soc_component_read(comp, gain_reg)); 4417 break; 4418 } 4419 4420 return 0; 4421 } 4422 4423 static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 4424 struct snd_kcontrol *kc, int event) 4425 { 4426 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4427 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4428 4429 switch (event) { 4430 case SND_SOC_DAPM_PRE_PMU: 4431 /* Disable AutoChop timer during power up */ 4432 snd_soc_component_update_bits(comp, 4433 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4434 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4435 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4436 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 4437 4438 break; 4439 case SND_SOC_DAPM_POST_PMD: 4440 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4441 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 4442 break; 4443 } 4444 4445 return 0; 4446 } 4447 4448 static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 4449 struct snd_kcontrol *kcontrol, 4450 int event) 4451 { 4452 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4453 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4454 int hph_mode = wcd->hph_mode; 4455 u8 dem_inp; 4456 4457 switch (event) { 4458 case SND_SOC_DAPM_PRE_PMU: 4459 /* Read DEM INP Select */ 4460 dem_inp = snd_soc_component_read(comp, 4461 WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03; 4462 4463 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 4464 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 4465 return -EINVAL; 4466 } 4467 if (hph_mode != CLS_H_LP) 4468 /* Ripple freq control enable */ 4469 snd_soc_component_update_bits(comp, 4470 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4471 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 4472 WCD934X_SIDO_RIPPLE_FREQ_ENABLE); 4473 /* Disable AutoChop timer during power up */ 4474 snd_soc_component_update_bits(comp, 4475 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4476 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4477 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4478 WCD_CLSH_STATE_HPHL, hph_mode); 4479 4480 break; 4481 case SND_SOC_DAPM_POST_PMD: 4482 /* 1000us required as per HW requirement */ 4483 usleep_range(1000, 1100); 4484 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4485 WCD_CLSH_STATE_HPHL, hph_mode); 4486 if (hph_mode != CLS_H_LP) 4487 /* Ripple freq control disable */ 4488 snd_soc_component_update_bits(comp, 4489 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4490 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0); 4491 4492 break; 4493 default: 4494 break; 4495 } 4496 4497 return 0; 4498 } 4499 4500 static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 4501 struct snd_kcontrol *kcontrol, 4502 int event) 4503 { 4504 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4505 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4506 int hph_mode = wcd->hph_mode; 4507 u8 dem_inp; 4508 4509 switch (event) { 4510 case SND_SOC_DAPM_PRE_PMU: 4511 dem_inp = snd_soc_component_read(comp, 4512 WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03; 4513 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 4514 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 4515 return -EINVAL; 4516 } 4517 if (hph_mode != CLS_H_LP) 4518 /* Ripple freq control enable */ 4519 snd_soc_component_update_bits(comp, 4520 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4521 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 4522 WCD934X_SIDO_RIPPLE_FREQ_ENABLE); 4523 /* Disable AutoChop timer during power up */ 4524 snd_soc_component_update_bits(comp, 4525 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4526 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4527 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4528 WCD_CLSH_STATE_HPHR, 4529 hph_mode); 4530 break; 4531 case SND_SOC_DAPM_POST_PMD: 4532 /* 1000us required as per HW requirement */ 4533 usleep_range(1000, 1100); 4534 4535 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4536 WCD_CLSH_STATE_HPHR, hph_mode); 4537 if (hph_mode != CLS_H_LP) 4538 /* Ripple freq control disable */ 4539 snd_soc_component_update_bits(comp, 4540 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4541 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0); 4542 break; 4543 default: 4544 break; 4545 } 4546 4547 return 0; 4548 } 4549 4550 static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w, 4551 struct snd_kcontrol *kc, int event) 4552 { 4553 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4554 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4555 4556 switch (event) { 4557 case SND_SOC_DAPM_PRE_PMU: 4558 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4559 WCD_CLSH_STATE_LO, CLS_AB); 4560 break; 4561 case SND_SOC_DAPM_POST_PMD: 4562 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4563 WCD_CLSH_STATE_LO, CLS_AB); 4564 break; 4565 } 4566 4567 return 0; 4568 } 4569 4570 static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 4571 struct snd_kcontrol *kcontrol, 4572 int event) 4573 { 4574 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4575 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4576 4577 switch (event) { 4578 case SND_SOC_DAPM_POST_PMU: 4579 /* 4580 * 7ms sleep is required after PA is enabled as per 4581 * HW requirement. If compander is disabled, then 4582 * 20ms delay is needed. 4583 */ 4584 usleep_range(20000, 20100); 4585 4586 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST, 4587 WCD934X_HPH_OCP_DET_MASK, 4588 WCD934X_HPH_OCP_DET_ENABLE); 4589 /* Remove Mute on primary path */ 4590 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL, 4591 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4592 0); 4593 /* Enable GM3 boost */ 4594 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL, 4595 WCD934X_HPH_GM3_BOOST_EN_MASK, 4596 WCD934X_HPH_GM3_BOOST_ENABLE); 4597 /* Enable AutoChop timer at the end of power up */ 4598 snd_soc_component_update_bits(comp, 4599 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4600 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 4601 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE); 4602 /* Remove mix path mute */ 4603 snd_soc_component_update_bits(comp, 4604 WCD934X_CDC_RX1_RX_PATH_MIX_CTL, 4605 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00); 4606 break; 4607 case SND_SOC_DAPM_PRE_PMD: 4608 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 4609 /* Enable DSD Mute before PA disable */ 4610 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST, 4611 WCD934X_HPH_OCP_DET_MASK, 4612 WCD934X_HPH_OCP_DET_DISABLE); 4613 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL, 4614 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4615 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4616 snd_soc_component_update_bits(comp, 4617 WCD934X_CDC_RX1_RX_PATH_MIX_CTL, 4618 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4619 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4620 break; 4621 case SND_SOC_DAPM_POST_PMD: 4622 /* 4623 * 5ms sleep is required after PA disable. If compander is 4624 * disabled, then 20ms delay is needed after PA disable. 4625 */ 4626 usleep_range(20000, 20100); 4627 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 4628 break; 4629 } 4630 4631 return 0; 4632 } 4633 4634 static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 4635 struct snd_kcontrol *kcontrol, 4636 int event) 4637 { 4638 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4639 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4640 4641 switch (event) { 4642 case SND_SOC_DAPM_POST_PMU: 4643 /* 4644 * 7ms sleep is required after PA is enabled as per 4645 * HW requirement. If compander is disabled, then 4646 * 20ms delay is needed. 4647 */ 4648 usleep_range(20000, 20100); 4649 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST, 4650 WCD934X_HPH_OCP_DET_MASK, 4651 WCD934X_HPH_OCP_DET_ENABLE); 4652 /* Remove mute */ 4653 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL, 4654 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4655 0); 4656 /* Enable GM3 boost */ 4657 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL, 4658 WCD934X_HPH_GM3_BOOST_EN_MASK, 4659 WCD934X_HPH_GM3_BOOST_ENABLE); 4660 /* Enable AutoChop timer at the end of power up */ 4661 snd_soc_component_update_bits(comp, 4662 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4663 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 4664 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE); 4665 /* Remove mix path mute if it is enabled */ 4666 if ((snd_soc_component_read(comp, 4667 WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10) 4668 snd_soc_component_update_bits(comp, 4669 WCD934X_CDC_RX2_RX_PATH_MIX_CTL, 4670 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 4671 WCD934X_CDC_RX_PGA_MUTE_DISABLE); 4672 break; 4673 case SND_SOC_DAPM_PRE_PMD: 4674 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_PRE_HPHR_PA_OFF); 4675 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST, 4676 WCD934X_HPH_OCP_DET_MASK, 4677 WCD934X_HPH_OCP_DET_DISABLE); 4678 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL, 4679 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4680 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4681 snd_soc_component_update_bits(comp, 4682 WCD934X_CDC_RX2_RX_PATH_MIX_CTL, 4683 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 4684 WCD934X_CDC_RX_PGA_MUTE_ENABLE); 4685 break; 4686 case SND_SOC_DAPM_POST_PMD: 4687 /* 4688 * 5ms sleep is required after PA disable. If compander is 4689 * disabled, then 20ms delay is needed after PA disable. 4690 */ 4691 usleep_range(20000, 20100); 4692 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHR_PA_OFF); 4693 break; 4694 } 4695 4696 return 0; 4697 } 4698 4699 static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp, 4700 unsigned int dmic, 4701 struct wcd934x_codec *wcd) 4702 { 4703 u8 tx_stream_fs; 4704 u8 adc_mux_index = 0, adc_mux_sel = 0; 4705 bool dec_found = false; 4706 u16 adc_mux_ctl_reg, tx_fs_reg; 4707 u32 dmic_fs; 4708 4709 while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) { 4710 if (adc_mux_index < 4) { 4711 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4712 (adc_mux_index * 2); 4713 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) { 4714 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4715 adc_mux_index - 4; 4716 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) { 4717 ++adc_mux_index; 4718 continue; 4719 } 4720 adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg) 4721 & 0xF8) >> 3) - 1; 4722 4723 if (adc_mux_sel == dmic) { 4724 dec_found = true; 4725 break; 4726 } 4727 4728 ++adc_mux_index; 4729 } 4730 4731 if (dec_found && adc_mux_index <= 8) { 4732 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index); 4733 tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F; 4734 if (tx_stream_fs <= 4) 4735 dmic_fs = min(wcd->dmic_sample_rate, WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ); 4736 else 4737 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ; 4738 } else { 4739 dmic_fs = wcd->dmic_sample_rate; 4740 } 4741 4742 return dmic_fs; 4743 } 4744 4745 static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp, 4746 u32 mclk_rate, u32 dmic_clk_rate) 4747 { 4748 u32 div_factor; 4749 u8 dmic_ctl_val; 4750 4751 /* Default value to return in case of error */ 4752 if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ) 4753 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2; 4754 else 4755 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3; 4756 4757 if (dmic_clk_rate == 0) { 4758 dev_err(comp->dev, 4759 "%s: dmic_sample_rate cannot be 0\n", 4760 __func__); 4761 goto done; 4762 } 4763 4764 div_factor = mclk_rate / dmic_clk_rate; 4765 switch (div_factor) { 4766 case 2: 4767 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2; 4768 break; 4769 case 3: 4770 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3; 4771 break; 4772 case 4: 4773 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4; 4774 break; 4775 case 6: 4776 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6; 4777 break; 4778 case 8: 4779 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8; 4780 break; 4781 case 16: 4782 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16; 4783 break; 4784 default: 4785 dev_err(comp->dev, 4786 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n", 4787 __func__, div_factor, mclk_rate, dmic_clk_rate); 4788 break; 4789 } 4790 4791 done: 4792 return dmic_ctl_val; 4793 } 4794 4795 static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 4796 struct snd_kcontrol *kcontrol, int event) 4797 { 4798 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4799 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4800 u8 dmic_clk_en = 0x01; 4801 u16 dmic_clk_reg; 4802 s32 *dmic_clk_cnt; 4803 u8 dmic_rate_val, dmic_rate_shift = 1; 4804 unsigned int dmic; 4805 u32 dmic_sample_rate; 4806 int ret; 4807 char *wname; 4808 4809 wname = strpbrk(w->name, "012345"); 4810 if (!wname) { 4811 dev_err(comp->dev, "%s: widget not found\n", __func__); 4812 return -EINVAL; 4813 } 4814 4815 ret = kstrtouint(wname, 10, &dmic); 4816 if (ret < 0) { 4817 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n", 4818 __func__); 4819 return -EINVAL; 4820 } 4821 4822 switch (dmic) { 4823 case 0: 4824 case 1: 4825 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt; 4826 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL; 4827 break; 4828 case 2: 4829 case 3: 4830 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt; 4831 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL; 4832 break; 4833 case 4: 4834 case 5: 4835 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt; 4836 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL; 4837 break; 4838 default: 4839 dev_err(comp->dev, "%s: Invalid DMIC Selection\n", 4840 __func__); 4841 return -EINVAL; 4842 } 4843 4844 switch (event) { 4845 case SND_SOC_DAPM_PRE_PMU: 4846 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic, 4847 wcd); 4848 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate, 4849 dmic_sample_rate); 4850 (*dmic_clk_cnt)++; 4851 if (*dmic_clk_cnt == 1) { 4852 dmic_rate_val = dmic_rate_val << dmic_rate_shift; 4853 snd_soc_component_update_bits(comp, dmic_clk_reg, 4854 WCD934X_DMIC_RATE_MASK, 4855 dmic_rate_val); 4856 snd_soc_component_update_bits(comp, dmic_clk_reg, 4857 dmic_clk_en, dmic_clk_en); 4858 } 4859 4860 break; 4861 case SND_SOC_DAPM_POST_PMD: 4862 (*dmic_clk_cnt)--; 4863 if (*dmic_clk_cnt == 0) 4864 snd_soc_component_update_bits(comp, dmic_clk_reg, 4865 dmic_clk_en, 0); 4866 break; 4867 } 4868 4869 return 0; 4870 } 4871 4872 static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp, 4873 int adc_mux_n) 4874 { 4875 u16 mask, shift, adc_mux_in_reg; 4876 u16 amic_mux_sel_reg; 4877 bool is_amic; 4878 4879 if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX || 4880 adc_mux_n == WCD934X_INVALID_ADC_MUX) 4881 return 0; 4882 4883 if (adc_mux_n < 3) { 4884 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4885 adc_mux_n; 4886 mask = 0x03; 4887 shift = 0; 4888 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4889 2 * adc_mux_n; 4890 } else if (adc_mux_n < 4) { 4891 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4892 mask = 0x03; 4893 shift = 0; 4894 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4895 2 * adc_mux_n; 4896 } else if (adc_mux_n < 7) { 4897 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4898 (adc_mux_n - 4); 4899 mask = 0x0C; 4900 shift = 2; 4901 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4902 adc_mux_n - 4; 4903 } else if (adc_mux_n < 8) { 4904 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4905 mask = 0x0C; 4906 shift = 2; 4907 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4908 adc_mux_n - 4; 4909 } else if (adc_mux_n < 12) { 4910 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4911 ((adc_mux_n == 8) ? (adc_mux_n - 8) : 4912 (adc_mux_n - 9)); 4913 mask = 0x30; 4914 shift = 4; 4915 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4916 adc_mux_n - 4; 4917 } else if (adc_mux_n < 13) { 4918 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4919 mask = 0x30; 4920 shift = 4; 4921 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4922 adc_mux_n - 4; 4923 } else { 4924 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1; 4925 mask = 0xC0; 4926 shift = 6; 4927 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4928 adc_mux_n - 4; 4929 } 4930 4931 is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg) 4932 & mask) >> shift) == 1); 4933 if (!is_amic) 4934 return 0; 4935 4936 return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07; 4937 } 4938 4939 static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp, 4940 int amic) 4941 { 4942 u16 pwr_level_reg = 0; 4943 4944 switch (amic) { 4945 case 1: 4946 case 2: 4947 pwr_level_reg = WCD934X_ANA_AMIC1; 4948 break; 4949 4950 case 3: 4951 case 4: 4952 pwr_level_reg = WCD934X_ANA_AMIC3; 4953 break; 4954 default: 4955 break; 4956 } 4957 4958 return pwr_level_reg; 4959 } 4960 4961 static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w, 4962 struct snd_kcontrol *kcontrol, int event) 4963 { 4964 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4965 unsigned int decimator; 4966 char *dec_adc_mux_name = NULL; 4967 char *widget_name; 4968 int ret = 0, amic_n; 4969 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg; 4970 u16 tx_gain_ctl_reg; 4971 char *dec; 4972 u8 hpf_coff_freq; 4973 4974 char *wname __free(kfree) = kstrndup(w->name, 15, GFP_KERNEL); 4975 if (!wname) 4976 return -ENOMEM; 4977 4978 widget_name = wname; 4979 dec_adc_mux_name = strsep(&widget_name, " "); 4980 if (!dec_adc_mux_name) { 4981 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 4982 __func__, w->name); 4983 return -EINVAL; 4984 } 4985 dec_adc_mux_name = widget_name; 4986 4987 dec = strpbrk(dec_adc_mux_name, "012345678"); 4988 if (!dec) { 4989 dev_err(comp->dev, "%s: decimator index not found\n", 4990 __func__); 4991 return -EINVAL; 4992 } 4993 4994 ret = kstrtouint(dec, 10, &decimator); 4995 if (ret < 0) { 4996 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 4997 __func__, wname); 4998 return -EINVAL; 4999 } 5000 5001 tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator; 5002 hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator; 5003 dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator; 5004 tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator; 5005 5006 switch (event) { 5007 case SND_SOC_DAPM_PRE_PMU: 5008 amic_n = wcd934x_codec_find_amic_input(comp, decimator); 5009 if (amic_n) 5010 pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp, 5011 amic_n); 5012 5013 if (!pwr_level_reg) 5014 break; 5015 5016 switch ((snd_soc_component_read(comp, pwr_level_reg) & 5017 WCD934X_AMIC_PWR_LVL_MASK) >> 5018 WCD934X_AMIC_PWR_LVL_SHIFT) { 5019 case WCD934X_AMIC_PWR_LEVEL_LP: 5020 snd_soc_component_update_bits(comp, dec_cfg_reg, 5021 WCD934X_DEC_PWR_LVL_MASK, 5022 WCD934X_DEC_PWR_LVL_LP); 5023 break; 5024 case WCD934X_AMIC_PWR_LEVEL_HP: 5025 snd_soc_component_update_bits(comp, dec_cfg_reg, 5026 WCD934X_DEC_PWR_LVL_MASK, 5027 WCD934X_DEC_PWR_LVL_HP); 5028 break; 5029 case WCD934X_AMIC_PWR_LEVEL_DEFAULT: 5030 case WCD934X_AMIC_PWR_LEVEL_HYBRID: 5031 default: 5032 snd_soc_component_update_bits(comp, dec_cfg_reg, 5033 WCD934X_DEC_PWR_LVL_MASK, 5034 WCD934X_DEC_PWR_LVL_DF); 5035 break; 5036 } 5037 break; 5038 case SND_SOC_DAPM_POST_PMU: 5039 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 5040 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 5041 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 5042 snd_soc_component_update_bits(comp, dec_cfg_reg, 5043 TX_HPF_CUT_OFF_FREQ_MASK, 5044 CF_MIN_3DB_150HZ << 5); 5045 snd_soc_component_update_bits(comp, hpf_gate_reg, 5046 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5047 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ); 5048 /* 5049 * Minimum 1 clk cycle delay is required as per 5050 * HW spec. 5051 */ 5052 usleep_range(1000, 1010); 5053 snd_soc_component_update_bits(comp, hpf_gate_reg, 5054 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5055 0); 5056 } 5057 /* apply gain after decimator is enabled */ 5058 snd_soc_component_write(comp, tx_gain_ctl_reg, 5059 snd_soc_component_read(comp, 5060 tx_gain_ctl_reg)); 5061 break; 5062 case SND_SOC_DAPM_PRE_PMD: 5063 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 5064 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 5065 5066 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 5067 snd_soc_component_update_bits(comp, dec_cfg_reg, 5068 TX_HPF_CUT_OFF_FREQ_MASK, 5069 hpf_coff_freq << 5); 5070 snd_soc_component_update_bits(comp, hpf_gate_reg, 5071 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5072 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ); 5073 /* 5074 * Minimum 1 clk cycle delay is required as per 5075 * HW spec. 5076 */ 5077 usleep_range(1000, 1010); 5078 snd_soc_component_update_bits(comp, hpf_gate_reg, 5079 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5080 0); 5081 } 5082 break; 5083 case SND_SOC_DAPM_POST_PMD: 5084 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 5085 0x10, 0x00); 5086 snd_soc_component_update_bits(comp, dec_cfg_reg, 5087 WCD934X_DEC_PWR_LVL_MASK, 5088 WCD934X_DEC_PWR_LVL_DF); 5089 break; 5090 } 5091 5092 return ret; 5093 } 5094 5095 static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp, 5096 u16 amic_reg, bool set) 5097 { 5098 u8 mask = 0x20; 5099 u8 val; 5100 5101 if (amic_reg == WCD934X_ANA_AMIC1 || 5102 amic_reg == WCD934X_ANA_AMIC3) 5103 mask = 0x40; 5104 5105 val = set ? mask : 0x00; 5106 5107 switch (amic_reg) { 5108 case WCD934X_ANA_AMIC1: 5109 case WCD934X_ANA_AMIC2: 5110 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2, 5111 mask, val); 5112 break; 5113 case WCD934X_ANA_AMIC3: 5114 case WCD934X_ANA_AMIC4: 5115 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4, 5116 mask, val); 5117 break; 5118 default: 5119 break; 5120 } 5121 } 5122 5123 static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w, 5124 struct snd_kcontrol *kcontrol, int event) 5125 { 5126 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 5127 5128 switch (event) { 5129 case SND_SOC_DAPM_PRE_PMU: 5130 wcd934x_codec_set_tx_hold(comp, w->reg, true); 5131 break; 5132 default: 5133 break; 5134 } 5135 5136 return 0; 5137 } 5138 5139 static int wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 5140 struct snd_kcontrol *kcontrol, 5141 int event) 5142 { 5143 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 5144 int micb_num = w->shift; 5145 5146 switch (event) { 5147 case SND_SOC_DAPM_PRE_PMU: 5148 wcd934x_micbias_control(component, micb_num, MICB_ENABLE, true); 5149 break; 5150 case SND_SOC_DAPM_POST_PMU: 5151 /* 1 msec delay as per HW requirement */ 5152 usleep_range(1000, 1100); 5153 break; 5154 case SND_SOC_DAPM_POST_PMD: 5155 wcd934x_micbias_control(component, micb_num, MICB_DISABLE, true); 5156 break; 5157 } 5158 5159 return 0; 5160 } 5161 5162 static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = { 5163 /* Analog Outputs */ 5164 SND_SOC_DAPM_OUTPUT("EAR"), 5165 SND_SOC_DAPM_OUTPUT("HPHL"), 5166 SND_SOC_DAPM_OUTPUT("HPHR"), 5167 SND_SOC_DAPM_OUTPUT("LINEOUT1"), 5168 SND_SOC_DAPM_OUTPUT("LINEOUT2"), 5169 SND_SOC_DAPM_OUTPUT("SPK1 OUT"), 5170 SND_SOC_DAPM_OUTPUT("SPK2 OUT"), 5171 SND_SOC_DAPM_OUTPUT("ANC EAR"), 5172 SND_SOC_DAPM_OUTPUT("ANC HPHL"), 5173 SND_SOC_DAPM_OUTPUT("ANC HPHR"), 5174 SND_SOC_DAPM_OUTPUT("WDMA3_OUT"), 5175 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"), 5176 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"), 5177 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM, 5178 AIF1_PB, 0, wcd934x_codec_enable_slim, 5179 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5180 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM, 5181 AIF2_PB, 0, wcd934x_codec_enable_slim, 5182 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5183 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM, 5184 AIF3_PB, 0, wcd934x_codec_enable_slim, 5185 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5186 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM, 5187 AIF4_PB, 0, wcd934x_codec_enable_slim, 5188 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5189 5190 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0, 5191 &slim_rx_mux[WCD934X_RX0]), 5192 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0, 5193 &slim_rx_mux[WCD934X_RX1]), 5194 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0, 5195 &slim_rx_mux[WCD934X_RX2]), 5196 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0, 5197 &slim_rx_mux[WCD934X_RX3]), 5198 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0, 5199 &slim_rx_mux[WCD934X_RX4]), 5200 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0, 5201 &slim_rx_mux[WCD934X_RX5]), 5202 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0, 5203 &slim_rx_mux[WCD934X_RX6]), 5204 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0, 5205 &slim_rx_mux[WCD934X_RX7]), 5206 5207 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 5208 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5209 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5210 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5211 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 5212 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 5213 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0), 5214 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0), 5215 5216 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0, 5217 &rx_int0_2_mux, wcd934x_codec_enable_mix_path, 5218 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5219 SND_SOC_DAPM_POST_PMD), 5220 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0, 5221 &rx_int1_2_mux, wcd934x_codec_enable_mix_path, 5222 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5223 SND_SOC_DAPM_POST_PMD), 5224 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0, 5225 &rx_int2_2_mux, wcd934x_codec_enable_mix_path, 5226 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5227 SND_SOC_DAPM_POST_PMD), 5228 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0, 5229 &rx_int3_2_mux, wcd934x_codec_enable_mix_path, 5230 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5231 SND_SOC_DAPM_POST_PMD), 5232 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0, 5233 &rx_int4_2_mux, wcd934x_codec_enable_mix_path, 5234 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5235 SND_SOC_DAPM_POST_PMD), 5236 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0, 5237 &rx_int7_2_mux, wcd934x_codec_enable_mix_path, 5238 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5239 SND_SOC_DAPM_POST_PMD), 5240 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0, 5241 &rx_int8_2_mux, wcd934x_codec_enable_mix_path, 5242 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5243 SND_SOC_DAPM_POST_PMD), 5244 5245 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5246 &rx_int0_1_mix_inp0_mux), 5247 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5248 &rx_int0_1_mix_inp1_mux), 5249 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5250 &rx_int0_1_mix_inp2_mux), 5251 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5252 &rx_int1_1_mix_inp0_mux), 5253 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5254 &rx_int1_1_mix_inp1_mux), 5255 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5256 &rx_int1_1_mix_inp2_mux), 5257 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5258 &rx_int2_1_mix_inp0_mux), 5259 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5260 &rx_int2_1_mix_inp1_mux), 5261 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5262 &rx_int2_1_mix_inp2_mux), 5263 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5264 &rx_int3_1_mix_inp0_mux), 5265 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5266 &rx_int3_1_mix_inp1_mux), 5267 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5268 &rx_int3_1_mix_inp2_mux), 5269 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5270 &rx_int4_1_mix_inp0_mux), 5271 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5272 &rx_int4_1_mix_inp1_mux), 5273 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5274 &rx_int4_1_mix_inp2_mux), 5275 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5276 &rx_int7_1_mix_inp0_mux), 5277 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5278 &rx_int7_1_mix_inp1_mux), 5279 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5280 &rx_int7_1_mix_inp2_mux), 5281 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5282 &rx_int8_1_mix_inp0_mux), 5283 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5284 &rx_int8_1_mix_inp1_mux), 5285 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5286 &rx_int8_1_mix_inp2_mux), 5287 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5288 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5289 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5290 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, 5291 rx_int1_asrc_switch, 5292 ARRAY_SIZE(rx_int1_asrc_switch)), 5293 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5294 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, 5295 rx_int2_asrc_switch, 5296 ARRAY_SIZE(rx_int2_asrc_switch)), 5297 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5298 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, 5299 rx_int3_asrc_switch, 5300 ARRAY_SIZE(rx_int3_asrc_switch)), 5301 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5302 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, 5303 rx_int4_asrc_switch, 5304 ARRAY_SIZE(rx_int4_asrc_switch)), 5305 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5306 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5307 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5308 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5309 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5310 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5311 SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5312 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5313 SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5314 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5315 SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5316 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5317 SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5318 5319 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5320 SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0, 5321 NULL, 0, NULL, 0), 5322 SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0, 5323 NULL, 0, NULL, 0), 5324 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4, 5325 0, &rx_int0_mix2_inp_mux, NULL, 5326 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5327 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4, 5328 0, &rx_int1_mix2_inp_mux, NULL, 5329 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5330 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4, 5331 0, &rx_int2_mix2_inp_mux, NULL, 5332 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5333 SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4, 5334 0, &rx_int3_mix2_inp_mux, NULL, 5335 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5336 SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4, 5337 0, &rx_int4_mix2_inp_mux, NULL, 5338 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5339 SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4, 5340 0, &rx_int7_mix2_inp_mux, NULL, 5341 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5342 5343 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux), 5344 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux), 5345 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux), 5346 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux), 5347 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux), 5348 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux), 5349 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux), 5350 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux), 5351 5352 SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 5353 0, 0, NULL, 0, wcd934x_codec_set_iir_gain, 5354 SND_SOC_DAPM_POST_PMU), 5355 SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 5356 1, 0, NULL, 0, wcd934x_codec_set_iir_gain, 5357 SND_SOC_DAPM_POST_PMU), 5358 SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL, 5359 4, 0, NULL, 0), 5360 SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL, 5361 4, 0, NULL, 0), 5362 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 5363 &rx_int0_dem_inp_mux), 5364 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 5365 &rx_int1_dem_inp_mux), 5366 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0, 5367 &rx_int2_dem_inp_mux), 5368 5369 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0, 5370 &rx_int0_1_interp_mux, 5371 wcd934x_codec_enable_main_path, 5372 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5373 SND_SOC_DAPM_POST_PMD), 5374 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0, 5375 &rx_int1_1_interp_mux, 5376 wcd934x_codec_enable_main_path, 5377 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5378 SND_SOC_DAPM_POST_PMD), 5379 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0, 5380 &rx_int2_1_interp_mux, 5381 wcd934x_codec_enable_main_path, 5382 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5383 SND_SOC_DAPM_POST_PMD), 5384 SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0, 5385 &rx_int3_1_interp_mux, 5386 wcd934x_codec_enable_main_path, 5387 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5388 SND_SOC_DAPM_POST_PMD), 5389 SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0, 5390 &rx_int4_1_interp_mux, 5391 wcd934x_codec_enable_main_path, 5392 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5393 SND_SOC_DAPM_POST_PMD), 5394 SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0, 5395 &rx_int7_1_interp_mux, 5396 wcd934x_codec_enable_main_path, 5397 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5398 SND_SOC_DAPM_POST_PMD), 5399 SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0, 5400 &rx_int8_1_interp_mux, 5401 wcd934x_codec_enable_main_path, 5402 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5403 SND_SOC_DAPM_POST_PMD), 5404 5405 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0, 5406 &rx_int0_2_interp_mux), 5407 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0, 5408 &rx_int1_2_interp_mux), 5409 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0, 5410 &rx_int2_2_interp_mux), 5411 SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0, 5412 &rx_int3_2_interp_mux), 5413 SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0, 5414 &rx_int4_2_interp_mux), 5415 SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0, 5416 &rx_int7_2_interp_mux), 5417 SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0, 5418 &rx_int8_2_interp_mux), 5419 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM, 5420 0, 0, wcd934x_codec_ear_dac_event, 5421 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5422 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5423 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH, 5424 5, 0, wcd934x_codec_hphl_dac_event, 5425 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5426 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5427 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH, 5428 4, 0, wcd934x_codec_hphr_dac_event, 5429 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5430 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5431 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM, 5432 0, 0, wcd934x_codec_lineout_dac_event, 5433 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5434 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM, 5435 0, 0, wcd934x_codec_lineout_dac_event, 5436 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5437 SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0), 5438 SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0, 5439 wcd934x_codec_enable_hphl_pa, 5440 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5441 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5442 SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0, 5443 wcd934x_codec_enable_hphr_pa, 5444 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5445 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5446 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0, 5447 NULL, 0), 5448 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0, 5449 NULL, 0), 5450 SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL, 5451 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5452 SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1, 5453 0, 0, NULL, 0), 5454 SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL, 5455 0, 0, NULL, 0), 5456 SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1, 5457 0, 0, NULL, 0), 5458 SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL, 5459 0, 0, NULL, 0), 5460 SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0, 5461 wcd934x_codec_enable_interp_clk, 5462 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5463 SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0, 5464 wcd934x_codec_enable_interp_clk, 5465 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5466 SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0, 5467 wcd934x_codec_enable_interp_clk, 5468 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5469 SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0, 5470 wcd934x_codec_enable_interp_clk, 5471 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5472 SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0, 5473 wcd934x_codec_enable_interp_clk, 5474 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5475 SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0, 5476 wcd934x_codec_enable_interp_clk, 5477 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5478 SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0, 5479 wcd934x_codec_enable_interp_clk, 5480 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5481 SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL, 5482 0, 0, NULL, 0), 5483 SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL, 5484 0, 0, NULL, 0), 5485 SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL, 5486 0, 0, NULL, 0), 5487 SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL, 5488 0, 0, NULL, 0), 5489 SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL, 5490 0, 0, NULL, 0), 5491 SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL, 5492 0, 0, NULL, 0), 5493 SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL, 5494 0, 0, NULL, 0), 5495 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, 5496 wcd934x_codec_enable_mclk, 5497 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5498 5499 /* TX */ 5500 SND_SOC_DAPM_INPUT("AMIC1"), 5501 SND_SOC_DAPM_INPUT("AMIC2"), 5502 SND_SOC_DAPM_INPUT("AMIC3"), 5503 SND_SOC_DAPM_INPUT("AMIC4"), 5504 SND_SOC_DAPM_INPUT("AMIC5"), 5505 SND_SOC_DAPM_INPUT("DMIC0 Pin"), 5506 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 5507 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 5508 SND_SOC_DAPM_INPUT("DMIC3 Pin"), 5509 SND_SOC_DAPM_INPUT("DMIC4 Pin"), 5510 SND_SOC_DAPM_INPUT("DMIC5 Pin"), 5511 5512 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM, 5513 AIF1_CAP, 0, wcd934x_codec_enable_slim, 5514 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5515 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM, 5516 AIF2_CAP, 0, wcd934x_codec_enable_slim, 5517 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5518 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM, 5519 AIF3_CAP, 0, wcd934x_codec_enable_slim, 5520 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5521 5522 SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0), 5523 SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5524 SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5525 SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5526 SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0), 5527 SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0), 5528 SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0), 5529 SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0), 5530 SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0), 5531 SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0), 5532 SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0), 5533 SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0), 5534 SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0), 5535 5536 /* Digital Mic Inputs */ 5537 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0, 5538 wcd934x_codec_enable_dmic, 5539 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5540 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 5541 wcd934x_codec_enable_dmic, 5542 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5543 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, 5544 wcd934x_codec_enable_dmic, 5545 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5546 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, 5547 wcd934x_codec_enable_dmic, 5548 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5549 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, 5550 wcd934x_codec_enable_dmic, 5551 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5552 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0, 5553 wcd934x_codec_enable_dmic, 5554 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5555 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0), 5556 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1), 5557 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2), 5558 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3), 5559 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4), 5560 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5), 5561 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6), 5562 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7), 5563 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8), 5564 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0), 5565 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1), 5566 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2), 5567 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3), 5568 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4), 5569 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5), 5570 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6), 5571 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7), 5572 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8), 5573 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0, 5574 &tx_adc_mux0_mux, wcd934x_codec_enable_dec, 5575 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5576 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5577 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0, 5578 &tx_adc_mux1_mux, wcd934x_codec_enable_dec, 5579 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5580 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5581 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0, 5582 &tx_adc_mux2_mux, wcd934x_codec_enable_dec, 5583 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5584 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5585 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0, 5586 &tx_adc_mux3_mux, wcd934x_codec_enable_dec, 5587 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5588 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5589 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0, 5590 &tx_adc_mux4_mux, wcd934x_codec_enable_dec, 5591 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5592 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5593 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0, 5594 &tx_adc_mux5_mux, wcd934x_codec_enable_dec, 5595 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5596 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5597 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0, 5598 &tx_adc_mux6_mux, wcd934x_codec_enable_dec, 5599 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5600 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5601 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0, 5602 &tx_adc_mux7_mux, wcd934x_codec_enable_dec, 5603 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5604 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5605 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0, 5606 &tx_adc_mux8_mux, wcd934x_codec_enable_dec, 5607 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5608 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5609 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0, 5610 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5611 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0, 5612 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5613 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0, 5614 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5615 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0, 5616 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5617 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 5618 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5619 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5620 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 5621 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5622 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5623 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 5624 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5625 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5626 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 5627 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5628 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5629 5630 SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5), 5631 SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0, 5632 &cdc_if_tx0_mux), 5633 SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0, 5634 &cdc_if_tx1_mux), 5635 SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0, 5636 &cdc_if_tx2_mux), 5637 SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0, 5638 &cdc_if_tx3_mux), 5639 SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0, 5640 &cdc_if_tx4_mux), 5641 SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0, 5642 &cdc_if_tx5_mux), 5643 SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0, 5644 &cdc_if_tx6_mux), 5645 SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0, 5646 &cdc_if_tx7_mux), 5647 SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0, 5648 &cdc_if_tx8_mux), 5649 SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0, 5650 &cdc_if_tx9_mux), 5651 SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0, 5652 &cdc_if_tx10_mux), 5653 SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0, 5654 &cdc_if_tx11_mux), 5655 SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0, 5656 &cdc_if_tx11_inp1_mux), 5657 SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0, 5658 &cdc_if_tx13_mux), 5659 SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0, 5660 &cdc_if_tx13_inp1_mux), 5661 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0, 5662 aif1_slim_cap_mixer, 5663 ARRAY_SIZE(aif1_slim_cap_mixer)), 5664 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0, 5665 aif2_slim_cap_mixer, 5666 ARRAY_SIZE(aif2_slim_cap_mixer)), 5667 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0, 5668 aif3_slim_cap_mixer, 5669 ARRAY_SIZE(aif3_slim_cap_mixer)), 5670 }; 5671 5672 static const struct snd_soc_dapm_route wcd934x_audio_map[] = { 5673 /* RX0-RX7 */ 5674 WCD934X_SLIM_RX_AIF_PATH(0), 5675 WCD934X_SLIM_RX_AIF_PATH(1), 5676 WCD934X_SLIM_RX_AIF_PATH(2), 5677 WCD934X_SLIM_RX_AIF_PATH(3), 5678 WCD934X_SLIM_RX_AIF_PATH(4), 5679 WCD934X_SLIM_RX_AIF_PATH(5), 5680 WCD934X_SLIM_RX_AIF_PATH(6), 5681 WCD934X_SLIM_RX_AIF_PATH(7), 5682 5683 /* RX0 Ear out */ 5684 WCD934X_INTERPOLATOR_PATH(0), 5685 WCD934X_INTERPOLATOR_MIX2(0), 5686 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"}, 5687 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"}, 5688 {"RX INT0 DAC", NULL, "RX_BIAS"}, 5689 {"EAR PA", NULL, "RX INT0 DAC"}, 5690 {"EAR", NULL, "EAR PA"}, 5691 5692 /* RX1 Headphone left */ 5693 WCD934X_INTERPOLATOR_PATH(1), 5694 WCD934X_INTERPOLATOR_MIX2(1), 5695 {"RX INT1 MIX3", NULL, "RX INT1 MIX2"}, 5696 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"}, 5697 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"}, 5698 {"RX INT1 DAC", NULL, "RX_BIAS"}, 5699 {"HPHL PA", NULL, "RX INT1 DAC"}, 5700 {"HPHL", NULL, "HPHL PA"}, 5701 5702 /* RX2 Headphone right */ 5703 WCD934X_INTERPOLATOR_PATH(2), 5704 WCD934X_INTERPOLATOR_MIX2(2), 5705 {"RX INT2 MIX3", NULL, "RX INT2 MIX2"}, 5706 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"}, 5707 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"}, 5708 {"RX INT2 DAC", NULL, "RX_BIAS"}, 5709 {"HPHR PA", NULL, "RX INT2 DAC"}, 5710 {"HPHR", NULL, "HPHR PA"}, 5711 5712 /* RX3 HIFi LineOut1 */ 5713 WCD934X_INTERPOLATOR_PATH(3), 5714 WCD934X_INTERPOLATOR_MIX2(3), 5715 {"RX INT3 MIX3", NULL, "RX INT3 MIX2"}, 5716 {"RX INT3 DAC", NULL, "RX INT3 MIX3"}, 5717 {"RX INT3 DAC", NULL, "RX_BIAS"}, 5718 {"LINEOUT1 PA", NULL, "RX INT3 DAC"}, 5719 {"LINEOUT1", NULL, "LINEOUT1 PA"}, 5720 5721 /* RX4 HIFi LineOut2 */ 5722 WCD934X_INTERPOLATOR_PATH(4), 5723 WCD934X_INTERPOLATOR_MIX2(4), 5724 {"RX INT4 MIX3", NULL, "RX INT4 MIX2"}, 5725 {"RX INT4 DAC", NULL, "RX INT4 MIX3"}, 5726 {"RX INT4 DAC", NULL, "RX_BIAS"}, 5727 {"LINEOUT2 PA", NULL, "RX INT4 DAC"}, 5728 {"LINEOUT2", NULL, "LINEOUT2 PA"}, 5729 5730 /* RX7 Speaker Left Out PA */ 5731 WCD934X_INTERPOLATOR_PATH(7), 5732 WCD934X_INTERPOLATOR_MIX2(7), 5733 {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"}, 5734 {"RX INT7 CHAIN", NULL, "RX_BIAS"}, 5735 {"RX INT7 CHAIN", NULL, "SBOOST0"}, 5736 {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"}, 5737 {"SPK1 OUT", NULL, "RX INT7 CHAIN"}, 5738 5739 /* RX8 Speaker Right Out PA */ 5740 WCD934X_INTERPOLATOR_PATH(8), 5741 {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"}, 5742 {"RX INT8 CHAIN", NULL, "RX_BIAS"}, 5743 {"RX INT8 CHAIN", NULL, "SBOOST1"}, 5744 {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"}, 5745 {"SPK2 OUT", NULL, "RX INT8 CHAIN"}, 5746 5747 /* Tx */ 5748 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"}, 5749 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"}, 5750 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"}, 5751 5752 WCD934X_SLIM_TX_AIF_PATH(0), 5753 WCD934X_SLIM_TX_AIF_PATH(1), 5754 WCD934X_SLIM_TX_AIF_PATH(2), 5755 WCD934X_SLIM_TX_AIF_PATH(3), 5756 WCD934X_SLIM_TX_AIF_PATH(4), 5757 WCD934X_SLIM_TX_AIF_PATH(5), 5758 WCD934X_SLIM_TX_AIF_PATH(6), 5759 WCD934X_SLIM_TX_AIF_PATH(7), 5760 WCD934X_SLIM_TX_AIF_PATH(8), 5761 5762 WCD934X_ADC_MUX(0), 5763 WCD934X_ADC_MUX(1), 5764 WCD934X_ADC_MUX(2), 5765 WCD934X_ADC_MUX(3), 5766 WCD934X_ADC_MUX(4), 5767 WCD934X_ADC_MUX(5), 5768 WCD934X_ADC_MUX(6), 5769 WCD934X_ADC_MUX(7), 5770 WCD934X_ADC_MUX(8), 5771 5772 {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"}, 5773 {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"}, 5774 {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"}, 5775 {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"}, 5776 {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"}, 5777 {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"}, 5778 {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"}, 5779 {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"}, 5780 {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"}, 5781 5782 {"AMIC4_5 SEL", "AMIC4", "AMIC4"}, 5783 {"AMIC4_5 SEL", "AMIC5", "AMIC5"}, 5784 5785 { "DMIC0", NULL, "DMIC0 Pin" }, 5786 { "DMIC1", NULL, "DMIC1 Pin" }, 5787 { "DMIC2", NULL, "DMIC2 Pin" }, 5788 { "DMIC3", NULL, "DMIC3 Pin" }, 5789 { "DMIC4", NULL, "DMIC4 Pin" }, 5790 { "DMIC5", NULL, "DMIC5 Pin" }, 5791 5792 {"ADC1", NULL, "AMIC1"}, 5793 {"ADC2", NULL, "AMIC2"}, 5794 {"ADC3", NULL, "AMIC3"}, 5795 {"ADC4", NULL, "AMIC4_5 SEL"}, 5796 5797 WCD934X_IIR_INP_MUX(0), 5798 WCD934X_IIR_INP_MUX(1), 5799 5800 {"SRC0", NULL, "IIR0"}, 5801 {"SRC1", NULL, "IIR1"}, 5802 }; 5803 5804 static int wcd934x_codec_set_jack(struct snd_soc_component *comp, 5805 struct snd_soc_jack *jack, void *data) 5806 { 5807 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 5808 int ret = 0; 5809 5810 if (!wcd->mbhc) 5811 return -ENOTSUPP; 5812 5813 if (jack && !wcd->mbhc_started) { 5814 ret = wcd_mbhc_start(wcd->mbhc, &wcd->mbhc_cfg, jack); 5815 wcd->mbhc_started = true; 5816 } else if (wcd->mbhc_started) { 5817 wcd_mbhc_stop(wcd->mbhc); 5818 wcd->mbhc_started = false; 5819 } 5820 5821 return ret; 5822 } 5823 5824 static const struct snd_soc_component_driver wcd934x_component_drv = { 5825 .probe = wcd934x_comp_probe, 5826 .remove = wcd934x_comp_remove, 5827 .set_sysclk = wcd934x_comp_set_sysclk, 5828 .controls = wcd934x_snd_controls, 5829 .num_controls = ARRAY_SIZE(wcd934x_snd_controls), 5830 .dapm_widgets = wcd934x_dapm_widgets, 5831 .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets), 5832 .dapm_routes = wcd934x_audio_map, 5833 .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map), 5834 .set_jack = wcd934x_codec_set_jack, 5835 .endianness = 1, 5836 }; 5837 5838 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd) 5839 { 5840 struct device *dev = &wcd->sdev->dev; 5841 struct wcd_mbhc_config *cfg = &wcd->mbhc_cfg; 5842 struct device_node *ifc_dev_np; 5843 5844 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0); 5845 if (!ifc_dev_np) 5846 return dev_err_probe(dev, -EINVAL, "No Interface device found\n"); 5847 5848 wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np); 5849 of_node_put(ifc_dev_np); 5850 if (!wcd->sidev) 5851 return dev_err_probe(dev, -EINVAL, "Unable to get SLIM Interface device\n"); 5852 5853 slim_get_logical_addr(wcd->sidev); 5854 wcd->if_regmap = regmap_init_slimbus(wcd->sidev, 5855 &wcd934x_ifc_regmap_config); 5856 if (IS_ERR(wcd->if_regmap)) 5857 return dev_err_probe(dev, PTR_ERR(wcd->if_regmap), 5858 "Failed to allocate ifc register map\n"); 5859 5860 of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate", 5861 &wcd->dmic_sample_rate); 5862 5863 cfg->mbhc_micbias = MIC_BIAS_2; 5864 cfg->anc_micbias = MIC_BIAS_2; 5865 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 5866 cfg->num_btn = WCD934X_MBHC_MAX_BUTTONS; 5867 cfg->micb_mv = wcd->micb2_mv; 5868 cfg->linein_th = 5000; 5869 cfg->hs_thr = 1700; 5870 cfg->hph_thr = 50; 5871 5872 wcd_dt_parse_mbhc_data(dev, cfg); 5873 5874 5875 return 0; 5876 } 5877 5878 static int wcd934x_codec_probe(struct platform_device *pdev) 5879 { 5880 struct device *dev = &pdev->dev; 5881 struct wcd934x_ddata *data = dev_get_drvdata(dev->parent); 5882 struct wcd934x_codec *wcd; 5883 int ret, irq; 5884 5885 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL); 5886 if (!wcd) 5887 return -ENOMEM; 5888 5889 wcd->dev = dev; 5890 wcd->regmap = data->regmap; 5891 wcd->extclk = data->extclk; 5892 wcd->sdev = to_slim_device(data->dev); 5893 mutex_init(&wcd->sysclk_mutex); 5894 mutex_init(&wcd->micb_lock); 5895 5896 ret = wcd934x_codec_parse_data(wcd); 5897 if (ret) 5898 return ret; 5899 5900 /* set default rate 9P6MHz */ 5901 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG, 5902 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 5903 WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 5904 memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs)); 5905 memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs)); 5906 5907 irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS); 5908 if (irq < 0) 5909 return dev_err_probe(wcd->dev, irq, "Failed to get SLIM IRQ\n"); 5910 5911 ret = devm_request_threaded_irq(dev, irq, NULL, 5912 wcd934x_slim_irq_handler, 5913 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 5914 "slim", wcd); 5915 if (ret) 5916 return dev_err_probe(dev, ret, "Failed to request slimbus irq\n"); 5917 5918 wcd934x_register_mclk_output(wcd); 5919 platform_set_drvdata(pdev, wcd); 5920 5921 return devm_snd_soc_register_component(dev, &wcd934x_component_drv, 5922 wcd934x_slim_dais, 5923 ARRAY_SIZE(wcd934x_slim_dais)); 5924 } 5925 5926 static const struct platform_device_id wcd934x_driver_id[] = { 5927 { 5928 .name = "wcd934x-codec", 5929 }, 5930 {}, 5931 }; 5932 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id); 5933 5934 static struct platform_driver wcd934x_codec_driver = { 5935 .probe = &wcd934x_codec_probe, 5936 .id_table = wcd934x_driver_id, 5937 .driver = { 5938 .name = "wcd934x-codec", 5939 } 5940 }; 5941 5942 module_platform_driver(wcd934x_codec_driver); 5943 MODULE_DESCRIPTION("WCD934x codec driver"); 5944 MODULE_LICENSE("GPL v2"); 5945