1e2be04c7SGreg Kroah-Hartman /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ 2d4ab3470SDennis Dalessandro /* 3d4ab3470SDennis Dalessandro * 4d4ab3470SDennis Dalessandro * This file is provided under a dual BSD/GPLv2 license. When using or 5d4ab3470SDennis Dalessandro * redistributing this file, you may do so under either license. 6d4ab3470SDennis Dalessandro * 7d4ab3470SDennis Dalessandro * GPL LICENSE SUMMARY 8d4ab3470SDennis Dalessandro * 9*d2e9ace4SKaike Wan * Copyright(c) 2015 - 2018 Intel Corporation. 10d4ab3470SDennis Dalessandro * 11d4ab3470SDennis Dalessandro * This program is free software; you can redistribute it and/or modify 12d4ab3470SDennis Dalessandro * it under the terms of version 2 of the GNU General Public License as 13d4ab3470SDennis Dalessandro * published by the Free Software Foundation. 14d4ab3470SDennis Dalessandro * 15d4ab3470SDennis Dalessandro * This program is distributed in the hope that it will be useful, but 16d4ab3470SDennis Dalessandro * WITHOUT ANY WARRANTY; without even the implied warranty of 17d4ab3470SDennis Dalessandro * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18d4ab3470SDennis Dalessandro * General Public License for more details. 19d4ab3470SDennis Dalessandro * 20d4ab3470SDennis Dalessandro * BSD LICENSE 21d4ab3470SDennis Dalessandro * 22d4ab3470SDennis Dalessandro * Copyright(c) 2015 Intel Corporation. 23d4ab3470SDennis Dalessandro * 24d4ab3470SDennis Dalessandro * Redistribution and use in source and binary forms, with or without 25d4ab3470SDennis Dalessandro * modification, are permitted provided that the following conditions 26d4ab3470SDennis Dalessandro * are met: 27d4ab3470SDennis Dalessandro * 28d4ab3470SDennis Dalessandro * - Redistributions of source code must retain the above copyright 29d4ab3470SDennis Dalessandro * notice, this list of conditions and the following disclaimer. 30d4ab3470SDennis Dalessandro * - Redistributions in binary form must reproduce the above copyright 31d4ab3470SDennis Dalessandro * notice, this list of conditions and the following disclaimer in 32d4ab3470SDennis Dalessandro * the documentation and/or other materials provided with the 33d4ab3470SDennis Dalessandro * distribution. 34d4ab3470SDennis Dalessandro * - Neither the name of Intel Corporation nor the names of its 35d4ab3470SDennis Dalessandro * contributors may be used to endorse or promote products derived 36d4ab3470SDennis Dalessandro * from this software without specific prior written permission. 37d4ab3470SDennis Dalessandro * 38d4ab3470SDennis Dalessandro * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 39d4ab3470SDennis Dalessandro * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 40d4ab3470SDennis Dalessandro * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 41d4ab3470SDennis Dalessandro * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 42d4ab3470SDennis Dalessandro * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 43d4ab3470SDennis Dalessandro * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 44d4ab3470SDennis Dalessandro * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 45d4ab3470SDennis Dalessandro * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 46d4ab3470SDennis Dalessandro * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 47d4ab3470SDennis Dalessandro * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 48d4ab3470SDennis Dalessandro * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 49d4ab3470SDennis Dalessandro * 50d4ab3470SDennis Dalessandro */ 51d4ab3470SDennis Dalessandro 52d4ab3470SDennis Dalessandro /* 53d4ab3470SDennis Dalessandro * This file contains defines, structures, etc. that are used 54d4ab3470SDennis Dalessandro * to communicate between kernel and user code. 55d4ab3470SDennis Dalessandro */ 56d4ab3470SDennis Dalessandro 57d4ab3470SDennis Dalessandro #ifndef _LINUX__HFI1_USER_H 58d4ab3470SDennis Dalessandro #define _LINUX__HFI1_USER_H 59d4ab3470SDennis Dalessandro 60d4ab3470SDennis Dalessandro #include <linux/types.h> 61843debb8SLeon Romanovsky #include <rdma/rdma_user_ioctl.h> 62d4ab3470SDennis Dalessandro 63d4ab3470SDennis Dalessandro /* 64d4ab3470SDennis Dalessandro * This version number is given to the driver by the user code during 65d4ab3470SDennis Dalessandro * initialization in the spu_userversion field of hfi1_user_info, so 66d4ab3470SDennis Dalessandro * the driver can check for compatibility with user code. 67d4ab3470SDennis Dalessandro * 68d4ab3470SDennis Dalessandro * The major version changes when data structures change in an incompatible 69d4ab3470SDennis Dalessandro * way. The driver must be the same for initialization to succeed. 70d4ab3470SDennis Dalessandro */ 71380fb942SDennis Dalessandro #define HFI1_USER_SWMAJOR 6 72d4ab3470SDennis Dalessandro 73d4ab3470SDennis Dalessandro /* 74d4ab3470SDennis Dalessandro * Minor version differences are always compatible 75d4ab3470SDennis Dalessandro * a within a major version, however if user software is larger 76d4ab3470SDennis Dalessandro * than driver software, some new features and/or structure fields 77d4ab3470SDennis Dalessandro * may not be implemented; the user code must deal with this if it 78d4ab3470SDennis Dalessandro * cares, or it must abort after initialization reports the difference. 79d4ab3470SDennis Dalessandro */ 80e730139bSJakub Pawlak #define HFI1_USER_SWMINOR 3 81d4ab3470SDennis Dalessandro 82d4ab3470SDennis Dalessandro /* 838d970cf9SDennis Dalessandro * We will encode the major/minor inside a single 32bit version number. 848d970cf9SDennis Dalessandro */ 858d970cf9SDennis Dalessandro #define HFI1_SWMAJOR_SHIFT 16 868d970cf9SDennis Dalessandro 878d970cf9SDennis Dalessandro /* 88d4ab3470SDennis Dalessandro * Set of HW and driver capability/feature bits. 89d4ab3470SDennis Dalessandro * These bit values are used to configure enabled/disabled HW and 90d4ab3470SDennis Dalessandro * driver features. The same set of bits are communicated to user 91d4ab3470SDennis Dalessandro * space. 92d4ab3470SDennis Dalessandro */ 93d4ab3470SDennis Dalessandro #define HFI1_CAP_DMA_RTAIL (1UL << 0) /* Use DMA'ed RTail value */ 94d4ab3470SDennis Dalessandro #define HFI1_CAP_SDMA (1UL << 1) /* Enable SDMA support */ 95d4ab3470SDennis Dalessandro #define HFI1_CAP_SDMA_AHG (1UL << 2) /* Enable SDMA AHG support */ 96d4ab3470SDennis Dalessandro #define HFI1_CAP_EXTENDED_PSN (1UL << 3) /* Enable Extended PSN support */ 97d4ab3470SDennis Dalessandro #define HFI1_CAP_HDRSUPP (1UL << 4) /* Enable Header Suppression */ 98*d2e9ace4SKaike Wan #define HFI1_CAP_TID_RDMA (1UL << 5) /* Enable TID RDMA operations */ 99d4ab3470SDennis Dalessandro #define HFI1_CAP_USE_SDMA_HEAD (1UL << 6) /* DMA Hdr Q tail vs. use CSR */ 100d4ab3470SDennis Dalessandro #define HFI1_CAP_MULTI_PKT_EGR (1UL << 7) /* Enable multi-packet Egr buffs*/ 101d4ab3470SDennis Dalessandro #define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8) /* Don't drop on Hdr Q full */ 102d4ab3470SDennis Dalessandro #define HFI1_CAP_NODROP_EGR_FULL (1UL << 9) /* Don't drop on EGR buffs full */ 103462075a6SMitko Haralanov #define HFI1_CAP_TID_UNMAP (1UL << 10) /* Disable Expected TID caching */ 104d4ab3470SDennis Dalessandro #define HFI1_CAP_PRINT_UNIMPL (1UL << 11) /* Show for unimplemented feats */ 105d4ab3470SDennis Dalessandro #define HFI1_CAP_ALLOW_PERM_JKEY (1UL << 12) /* Allow use of permissive JKEY */ 106d4ab3470SDennis Dalessandro #define HFI1_CAP_NO_INTEGRITY (1UL << 13) /* Enable ctxt integrity checks */ 107d4ab3470SDennis Dalessandro #define HFI1_CAP_PKEY_CHECK (1UL << 14) /* Enable ctxt PKey checking */ 108d4ab3470SDennis Dalessandro #define HFI1_CAP_STATIC_RATE_CTRL (1UL << 15) /* Allow PBC.StaticRateControl */ 109*d2e9ace4SKaike Wan #define HFI1_CAP_OPFN (1UL << 16) /* Enable the OPFN protocol */ 110d4ab3470SDennis Dalessandro #define HFI1_CAP_SDMA_HEAD_CHECK (1UL << 17) /* SDMA head checking */ 111d4ab3470SDennis Dalessandro #define HFI1_CAP_EARLY_CREDIT_RETURN (1UL << 18) /* early credit return */ 112d4ab3470SDennis Dalessandro 113d4ab3470SDennis Dalessandro #define HFI1_RCVHDR_ENTSIZE_2 (1UL << 0) 114d4ab3470SDennis Dalessandro #define HFI1_RCVHDR_ENTSIZE_16 (1UL << 1) 115d4ab3470SDennis Dalessandro #define HFI1_RCVDHR_ENTSIZE_32 (1UL << 2) 116d4ab3470SDennis Dalessandro 117d4ab3470SDennis Dalessandro #define _HFI1_EVENT_FROZEN_BIT 0 118d4ab3470SDennis Dalessandro #define _HFI1_EVENT_LINKDOWN_BIT 1 119d4ab3470SDennis Dalessandro #define _HFI1_EVENT_LID_CHANGE_BIT 2 120d4ab3470SDennis Dalessandro #define _HFI1_EVENT_LMC_CHANGE_BIT 3 121d4ab3470SDennis Dalessandro #define _HFI1_EVENT_SL2VL_CHANGE_BIT 4 122955ad36dSMitko Haralanov #define _HFI1_EVENT_TID_MMU_NOTIFY_BIT 5 123955ad36dSMitko Haralanov #define _HFI1_MAX_EVENT_BIT _HFI1_EVENT_TID_MMU_NOTIFY_BIT 124d4ab3470SDennis Dalessandro 125d4ab3470SDennis Dalessandro #define HFI1_EVENT_FROZEN (1UL << _HFI1_EVENT_FROZEN_BIT) 1263bd4dce1SMitko Haralanov #define HFI1_EVENT_LINKDOWN (1UL << _HFI1_EVENT_LINKDOWN_BIT) 1273bd4dce1SMitko Haralanov #define HFI1_EVENT_LID_CHANGE (1UL << _HFI1_EVENT_LID_CHANGE_BIT) 1283bd4dce1SMitko Haralanov #define HFI1_EVENT_LMC_CHANGE (1UL << _HFI1_EVENT_LMC_CHANGE_BIT) 1293bd4dce1SMitko Haralanov #define HFI1_EVENT_SL2VL_CHANGE (1UL << _HFI1_EVENT_SL2VL_CHANGE_BIT) 130955ad36dSMitko Haralanov #define HFI1_EVENT_TID_MMU_NOTIFY (1UL << _HFI1_EVENT_TID_MMU_NOTIFY_BIT) 131d4ab3470SDennis Dalessandro 132d4ab3470SDennis Dalessandro /* 133d4ab3470SDennis Dalessandro * These are the status bits readable (in ASCII form, 64bit value) 134d4ab3470SDennis Dalessandro * from the "status" sysfs file. For binary compatibility, values 135d4ab3470SDennis Dalessandro * must remain as is; removed states can be reused for different 136d4ab3470SDennis Dalessandro * purposes. 137d4ab3470SDennis Dalessandro */ 138d4ab3470SDennis Dalessandro #define HFI1_STATUS_INITTED 0x1 /* basic initialization done */ 139d4ab3470SDennis Dalessandro /* Chip has been found and initialized */ 140d4ab3470SDennis Dalessandro #define HFI1_STATUS_CHIP_PRESENT 0x20 141d4ab3470SDennis Dalessandro /* IB link is at ACTIVE, usable for data traffic */ 142d4ab3470SDennis Dalessandro #define HFI1_STATUS_IB_READY 0x40 143d4ab3470SDennis Dalessandro /* link is configured, LID, MTU, etc. have been set */ 144d4ab3470SDennis Dalessandro #define HFI1_STATUS_IB_CONF 0x80 145d4ab3470SDennis Dalessandro /* A Fatal hardware error has occurred. */ 146d4ab3470SDennis Dalessandro #define HFI1_STATUS_HWERROR 0x200 147d4ab3470SDennis Dalessandro 148d4ab3470SDennis Dalessandro /* 149d4ab3470SDennis Dalessandro * Number of supported shared contexts. 150d4ab3470SDennis Dalessandro * This is the maximum number of software contexts that can share 151d4ab3470SDennis Dalessandro * a hardware send/receive context. 152d4ab3470SDennis Dalessandro */ 153d4ab3470SDennis Dalessandro #define HFI1_MAX_SHARED_CTXTS 8 154d4ab3470SDennis Dalessandro 155d4ab3470SDennis Dalessandro /* 156d4ab3470SDennis Dalessandro * Poll types 157d4ab3470SDennis Dalessandro */ 158d4ab3470SDennis Dalessandro #define HFI1_POLL_TYPE_ANYRCV 0x0 159d4ab3470SDennis Dalessandro #define HFI1_POLL_TYPE_URGENT 0x1 160d4ab3470SDennis Dalessandro 161d4ab3470SDennis Dalessandro enum hfi1_sdma_comp_state { 162d4ab3470SDennis Dalessandro FREE = 0, 163d4ab3470SDennis Dalessandro QUEUED, 164d4ab3470SDennis Dalessandro COMPLETE, 165d4ab3470SDennis Dalessandro ERROR 166d4ab3470SDennis Dalessandro }; 167d4ab3470SDennis Dalessandro 168d4ab3470SDennis Dalessandro /* 169d4ab3470SDennis Dalessandro * SDMA completion ring entry 170d4ab3470SDennis Dalessandro */ 171d4ab3470SDennis Dalessandro struct hfi1_sdma_comp_entry { 172d4ab3470SDennis Dalessandro __u32 status; 173d4ab3470SDennis Dalessandro __u32 errcode; 174d4ab3470SDennis Dalessandro }; 175d4ab3470SDennis Dalessandro 176d4ab3470SDennis Dalessandro /* 177d4ab3470SDennis Dalessandro * Device status and notifications from driver to user-space. 178d4ab3470SDennis Dalessandro */ 179d4ab3470SDennis Dalessandro struct hfi1_status { 18026b99066SJason Gunthorpe __aligned_u64 dev; /* device/hw status bits */ 18126b99066SJason Gunthorpe __aligned_u64 port; /* port state and status bits */ 182d4ab3470SDennis Dalessandro char freezemsg[0]; 183d4ab3470SDennis Dalessandro }; 184d4ab3470SDennis Dalessandro 185d4ab3470SDennis Dalessandro enum sdma_req_opcode { 186d4ab3470SDennis Dalessandro EXPECTED = 0, 187d4ab3470SDennis Dalessandro EAGER 188d4ab3470SDennis Dalessandro }; 189d4ab3470SDennis Dalessandro 190d4ab3470SDennis Dalessandro #define HFI1_SDMA_REQ_VERSION_MASK 0xF 191d4ab3470SDennis Dalessandro #define HFI1_SDMA_REQ_VERSION_SHIFT 0x0 192d4ab3470SDennis Dalessandro #define HFI1_SDMA_REQ_OPCODE_MASK 0xF 193d4ab3470SDennis Dalessandro #define HFI1_SDMA_REQ_OPCODE_SHIFT 0x4 194d4ab3470SDennis Dalessandro #define HFI1_SDMA_REQ_IOVCNT_MASK 0xFF 195d4ab3470SDennis Dalessandro #define HFI1_SDMA_REQ_IOVCNT_SHIFT 0x8 196d4ab3470SDennis Dalessandro 197d4ab3470SDennis Dalessandro struct sdma_req_info { 198d4ab3470SDennis Dalessandro /* 199d4ab3470SDennis Dalessandro * bits 0-3 - version (currently unused) 200d4ab3470SDennis Dalessandro * bits 4-7 - opcode (enum sdma_req_opcode) 201d4ab3470SDennis Dalessandro * bits 8-15 - io vector count 202d4ab3470SDennis Dalessandro */ 203d4ab3470SDennis Dalessandro __u16 ctrl; 204d4ab3470SDennis Dalessandro /* 205d4ab3470SDennis Dalessandro * Number of fragments contained in this request. 206d4ab3470SDennis Dalessandro * User-space has already computed how many 207d4ab3470SDennis Dalessandro * fragment-sized packet the user buffer will be 208d4ab3470SDennis Dalessandro * split into. 209d4ab3470SDennis Dalessandro */ 210d4ab3470SDennis Dalessandro __u16 npkts; 211d4ab3470SDennis Dalessandro /* 212d4ab3470SDennis Dalessandro * Size of each fragment the user buffer will be 213d4ab3470SDennis Dalessandro * split into. 214d4ab3470SDennis Dalessandro */ 215d4ab3470SDennis Dalessandro __u16 fragsize; 216d4ab3470SDennis Dalessandro /* 217d4ab3470SDennis Dalessandro * Index of the slot in the SDMA completion ring 218d4ab3470SDennis Dalessandro * this request should be using. User-space is 219d4ab3470SDennis Dalessandro * in charge of managing its own ring. 220d4ab3470SDennis Dalessandro */ 221d4ab3470SDennis Dalessandro __u16 comp_idx; 2225229f87eSJason Gunthorpe } __attribute__((__packed__)); 223d4ab3470SDennis Dalessandro 224d4ab3470SDennis Dalessandro /* 225d4ab3470SDennis Dalessandro * SW KDETH header. 226d4ab3470SDennis Dalessandro * swdata is SW defined portion. 227d4ab3470SDennis Dalessandro */ 228d4ab3470SDennis Dalessandro struct hfi1_kdeth_header { 229d4ab3470SDennis Dalessandro __le32 ver_tid_offset; 230d4ab3470SDennis Dalessandro __le16 jkey; 231d4ab3470SDennis Dalessandro __le16 hcrc; 232d4ab3470SDennis Dalessandro __le32 swdata[7]; 2335229f87eSJason Gunthorpe } __attribute__((__packed__)); 234d4ab3470SDennis Dalessandro 235d4ab3470SDennis Dalessandro /* 236d4ab3470SDennis Dalessandro * Structure describing the headers that User space uses. The 237d4ab3470SDennis Dalessandro * structure above is a subset of this one. 238d4ab3470SDennis Dalessandro */ 239d4ab3470SDennis Dalessandro struct hfi1_pkt_header { 240d4ab3470SDennis Dalessandro __le16 pbc[4]; 241d4ab3470SDennis Dalessandro __be16 lrh[4]; 242d4ab3470SDennis Dalessandro __be32 bth[3]; 243d4ab3470SDennis Dalessandro struct hfi1_kdeth_header kdeth; 2445229f87eSJason Gunthorpe } __attribute__((__packed__)); 245d4ab3470SDennis Dalessandro 246d4ab3470SDennis Dalessandro 247d4ab3470SDennis Dalessandro /* 248d4ab3470SDennis Dalessandro * The list of usermode accessible registers. 249d4ab3470SDennis Dalessandro */ 250d4ab3470SDennis Dalessandro enum hfi1_ureg { 251d4ab3470SDennis Dalessandro /* (RO) DMA RcvHdr to be used next. */ 252d4ab3470SDennis Dalessandro ur_rcvhdrtail = 0, 253d4ab3470SDennis Dalessandro /* (RW) RcvHdr entry to be processed next by host. */ 254d4ab3470SDennis Dalessandro ur_rcvhdrhead = 1, 255d4ab3470SDennis Dalessandro /* (RO) Index of next Eager index to use. */ 256d4ab3470SDennis Dalessandro ur_rcvegrindextail = 2, 257d4ab3470SDennis Dalessandro /* (RW) Eager TID to be processed next */ 258d4ab3470SDennis Dalessandro ur_rcvegrindexhead = 3, 259d4ab3470SDennis Dalessandro /* (RO) Receive Eager Offset Tail */ 260d4ab3470SDennis Dalessandro ur_rcvegroffsettail = 4, 261d4ab3470SDennis Dalessandro /* For internal use only; max register number. */ 262d4ab3470SDennis Dalessandro ur_maxreg, 263d4ab3470SDennis Dalessandro /* (RW) Receive TID flow table */ 264d4ab3470SDennis Dalessandro ur_rcvtidflowtable = 256 265d4ab3470SDennis Dalessandro }; 266d4ab3470SDennis Dalessandro 267d4ab3470SDennis Dalessandro #endif /* _LINIUX__HFI1_USER_H */ 268