1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _UAPI_I915_DRM_H_ 28 #define _UAPI_I915_DRM_H_ 29 30 #include "drm.h" 31 32 #if defined(__cplusplus) 33 extern "C" { 34 #endif 35 36 /* Please note that modifications to all structs defined here are 37 * subject to backwards-compatibility constraints. 38 */ 39 40 /** 41 * DOC: uevents generated by i915 on its device node 42 * 43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 44 * event from the GPU L3 cache. Additional information supplied is ROW, 45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 46 * track of these events, and if a specific cache-line seems to have a 47 * persistent error, remap it with the L3 remapping tool supplied in 48 * intel-gpu-tools. The value supplied with the event is always 1. 49 * 50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via 51 * hangcheck. The error detection event is a good indicator of when things 52 * began to go badly. The value supplied with the event is a 1 upon error 53 * detection, and a 0 upon reset completion, signifying no more error 54 * exists. NOTE: Disabling hangcheck or reset via module parameter will 55 * cause the related events to not be seen. 56 * 57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 58 * GPU. The value supplied with the event is always 1. NOTE: Disable 59 * reset via module parameter will cause this event to not be seen. 60 */ 61 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 62 #define I915_ERROR_UEVENT "ERROR" 63 #define I915_RESET_UEVENT "RESET" 64 65 /** 66 * struct i915_user_extension - Base class for defining a chain of extensions 67 * 68 * Many interfaces need to grow over time. In most cases we can simply 69 * extend the struct and have userspace pass in more data. Another option, 70 * as demonstrated by Vulkan's approach to providing extensions for forward 71 * and backward compatibility, is to use a list of optional structs to 72 * provide those extra details. 73 * 74 * The key advantage to using an extension chain is that it allows us to 75 * redefine the interface more easily than an ever growing struct of 76 * increasing complexity, and for large parts of that interface to be 77 * entirely optional. The downside is more pointer chasing; chasing across 78 * the __user boundary with pointers encapsulated inside u64. 79 * 80 * Example chaining: 81 * 82 * .. code-block:: C 83 * 84 * struct i915_user_extension ext3 { 85 * .next_extension = 0, // end 86 * .name = ..., 87 * }; 88 * struct i915_user_extension ext2 { 89 * .next_extension = (uintptr_t)&ext3, 90 * .name = ..., 91 * }; 92 * struct i915_user_extension ext1 { 93 * .next_extension = (uintptr_t)&ext2, 94 * .name = ..., 95 * }; 96 * 97 * Typically the struct i915_user_extension would be embedded in some uAPI 98 * struct, and in this case we would feed it the head of the chain(i.e ext1), 99 * which would then apply all of the above extensions. 100 * 101 */ 102 struct i915_user_extension { 103 /** 104 * @next_extension: 105 * 106 * Pointer to the next struct i915_user_extension, or zero if the end. 107 */ 108 __u64 next_extension; 109 /** 110 * @name: Name of the extension. 111 * 112 * Note that the name here is just some integer. 113 * 114 * Also note that the name space for this is not global for the whole 115 * driver, but rather its scope/meaning is limited to the specific piece 116 * of uAPI which has embedded the struct i915_user_extension. 117 */ 118 __u32 name; 119 /** 120 * @flags: MBZ 121 * 122 * All undefined bits must be zero. 123 */ 124 __u32 flags; 125 /** 126 * @rsvd: MBZ 127 * 128 * Reserved for future use; must be zero. 129 */ 130 __u32 rsvd[4]; 131 }; 132 133 /* 134 * MOCS indexes used for GPU surfaces, defining the cacheability of the 135 * surface data and the coherency for this data wrt. CPU vs. GPU accesses. 136 */ 137 enum i915_mocs_table_index { 138 /* 139 * Not cached anywhere, coherency between CPU and GPU accesses is 140 * guaranteed. 141 */ 142 I915_MOCS_UNCACHED, 143 /* 144 * Cacheability and coherency controlled by the kernel automatically 145 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current 146 * usage of the surface (used for display scanout or not). 147 */ 148 I915_MOCS_PTE, 149 /* 150 * Cached in all GPU caches available on the platform. 151 * Coherency between CPU and GPU accesses to the surface is not 152 * guaranteed without extra synchronization. 153 */ 154 I915_MOCS_CACHED, 155 }; 156 157 /** 158 * enum drm_i915_gem_engine_class - uapi engine type enumeration 159 * 160 * Different engines serve different roles, and there may be more than one 161 * engine serving each role. This enum provides a classification of the role 162 * of the engine, which may be used when requesting operations to be performed 163 * on a certain subset of engines, or for providing information about that 164 * group. 165 */ 166 enum drm_i915_gem_engine_class { 167 /** 168 * @I915_ENGINE_CLASS_RENDER: 169 * 170 * Render engines support instructions used for 3D, Compute (GPGPU), 171 * and programmable media workloads. These instructions fetch data and 172 * dispatch individual work items to threads that operate in parallel. 173 * The threads run small programs (called "kernels" or "shaders") on 174 * the GPU's execution units (EUs). 175 */ 176 I915_ENGINE_CLASS_RENDER = 0, 177 178 /** 179 * @I915_ENGINE_CLASS_COPY: 180 * 181 * Copy engines (also referred to as "blitters") support instructions 182 * that move blocks of data from one location in memory to another, 183 * or that fill a specified location of memory with fixed data. 184 * Copy engines can perform pre-defined logical or bitwise operations 185 * on the source, destination, or pattern data. 186 */ 187 I915_ENGINE_CLASS_COPY = 1, 188 189 /** 190 * @I915_ENGINE_CLASS_VIDEO: 191 * 192 * Video engines (also referred to as "bit stream decode" (BSD) or 193 * "vdbox") support instructions that perform fixed-function media 194 * decode and encode. 195 */ 196 I915_ENGINE_CLASS_VIDEO = 2, 197 198 /** 199 * @I915_ENGINE_CLASS_VIDEO_ENHANCE: 200 * 201 * Video enhancement engines (also referred to as "vebox") support 202 * instructions related to image enhancement. 203 */ 204 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, 205 206 /** 207 * @I915_ENGINE_CLASS_COMPUTE: 208 * 209 * Compute engines support a subset of the instructions available 210 * on render engines: compute engines support Compute (GPGPU) and 211 * programmable media workloads, but do not support the 3D pipeline. 212 */ 213 I915_ENGINE_CLASS_COMPUTE = 4, 214 215 /* Values in this enum should be kept compact. */ 216 217 /** 218 * @I915_ENGINE_CLASS_INVALID: 219 * 220 * Placeholder value to represent an invalid engine class assignment. 221 */ 222 I915_ENGINE_CLASS_INVALID = -1 223 }; 224 225 /** 226 * struct i915_engine_class_instance - Engine class/instance identifier 227 * 228 * There may be more than one engine fulfilling any role within the system. 229 * Each engine of a class is given a unique instance number and therefore 230 * any engine can be specified by its class:instance tuplet. APIs that allow 231 * access to any engine in the system will use struct i915_engine_class_instance 232 * for this identification. 233 */ 234 struct i915_engine_class_instance { 235 /** 236 * @engine_class: 237 * 238 * Engine class from enum drm_i915_gem_engine_class 239 */ 240 __u16 engine_class; 241 #define I915_ENGINE_CLASS_INVALID_NONE -1 242 #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2 243 244 /** 245 * @engine_instance: 246 * 247 * Engine instance. 248 */ 249 __u16 engine_instance; 250 }; 251 252 /** 253 * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915 254 * 255 */ 256 257 enum drm_i915_pmu_engine_sample { 258 I915_SAMPLE_BUSY = 0, 259 I915_SAMPLE_WAIT = 1, 260 I915_SAMPLE_SEMA = 2 261 }; 262 263 #define I915_PMU_SAMPLE_BITS (4) 264 #define I915_PMU_SAMPLE_MASK (0xf) 265 #define I915_PMU_SAMPLE_INSTANCE_BITS (8) 266 #define I915_PMU_CLASS_SHIFT \ 267 (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) 268 269 #define __I915_PMU_ENGINE(class, instance, sample) \ 270 ((class) << I915_PMU_CLASS_SHIFT | \ 271 (instance) << I915_PMU_SAMPLE_BITS | \ 272 (sample)) 273 274 #define I915_PMU_ENGINE_BUSY(class, instance) \ 275 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) 276 277 #define I915_PMU_ENGINE_WAIT(class, instance) \ 278 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) 279 280 #define I915_PMU_ENGINE_SEMA(class, instance) \ 281 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) 282 283 /* 284 * Top 4 bits of every non-engine counter are GT id. 285 */ 286 #define __I915_PMU_GT_SHIFT (60) 287 288 #define ___I915_PMU_OTHER(gt, x) \ 289 (((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \ 290 ((__u64)(gt) << __I915_PMU_GT_SHIFT)) 291 292 #define __I915_PMU_OTHER(x) ___I915_PMU_OTHER(0, x) 293 294 #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) 295 #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) 296 #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) 297 #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) 298 #define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4) 299 300 #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY 301 302 #define __I915_PMU_ACTUAL_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 0) 303 #define __I915_PMU_REQUESTED_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 1) 304 #define __I915_PMU_INTERRUPTS(gt) ___I915_PMU_OTHER(gt, 2) 305 #define __I915_PMU_RC6_RESIDENCY(gt) ___I915_PMU_OTHER(gt, 3) 306 #define __I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt) ___I915_PMU_OTHER(gt, 4) 307 308 /* Each region is a minimum of 16k, and there are at most 255 of them. 309 */ 310 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 311 * of chars for next/prev indices */ 312 #define I915_LOG_MIN_TEX_REGION_SIZE 14 313 314 typedef struct _drm_i915_init { 315 enum { 316 I915_INIT_DMA = 0x01, 317 I915_CLEANUP_DMA = 0x02, 318 I915_RESUME_DMA = 0x03 319 } func; 320 unsigned int mmio_offset; 321 int sarea_priv_offset; 322 unsigned int ring_start; 323 unsigned int ring_end; 324 unsigned int ring_size; 325 unsigned int front_offset; 326 unsigned int back_offset; 327 unsigned int depth_offset; 328 unsigned int w; 329 unsigned int h; 330 unsigned int pitch; 331 unsigned int pitch_bits; 332 unsigned int back_pitch; 333 unsigned int depth_pitch; 334 unsigned int cpp; 335 unsigned int chipset; 336 } drm_i915_init_t; 337 338 typedef struct _drm_i915_sarea { 339 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 340 int last_upload; /* last time texture was uploaded */ 341 int last_enqueue; /* last time a buffer was enqueued */ 342 int last_dispatch; /* age of the most recently dispatched buffer */ 343 int ctxOwner; /* last context to upload state */ 344 int texAge; 345 int pf_enabled; /* is pageflipping allowed? */ 346 int pf_active; 347 int pf_current_page; /* which buffer is being displayed? */ 348 int perf_boxes; /* performance boxes to be displayed */ 349 int width, height; /* screen size in pixels */ 350 351 drm_handle_t front_handle; 352 int front_offset; 353 int front_size; 354 355 drm_handle_t back_handle; 356 int back_offset; 357 int back_size; 358 359 drm_handle_t depth_handle; 360 int depth_offset; 361 int depth_size; 362 363 drm_handle_t tex_handle; 364 int tex_offset; 365 int tex_size; 366 int log_tex_granularity; 367 int pitch; 368 int rotation; /* 0, 90, 180 or 270 */ 369 int rotated_offset; 370 int rotated_size; 371 int rotated_pitch; 372 int virtualX, virtualY; 373 374 unsigned int front_tiled; 375 unsigned int back_tiled; 376 unsigned int depth_tiled; 377 unsigned int rotated_tiled; 378 unsigned int rotated2_tiled; 379 380 int pipeA_x; 381 int pipeA_y; 382 int pipeA_w; 383 int pipeA_h; 384 int pipeB_x; 385 int pipeB_y; 386 int pipeB_w; 387 int pipeB_h; 388 389 /* fill out some space for old userspace triple buffer */ 390 drm_handle_t unused_handle; 391 __u32 unused1, unused2, unused3; 392 393 /* buffer object handles for static buffers. May change 394 * over the lifetime of the client. 395 */ 396 __u32 front_bo_handle; 397 __u32 back_bo_handle; 398 __u32 unused_bo_handle; 399 __u32 depth_bo_handle; 400 401 } drm_i915_sarea_t; 402 403 /* due to userspace building against these headers we need some compat here */ 404 #define planeA_x pipeA_x 405 #define planeA_y pipeA_y 406 #define planeA_w pipeA_w 407 #define planeA_h pipeA_h 408 #define planeB_x pipeB_x 409 #define planeB_y pipeB_y 410 #define planeB_w pipeB_w 411 #define planeB_h pipeB_h 412 413 /* Flags for perf_boxes 414 */ 415 #define I915_BOX_RING_EMPTY 0x1 416 #define I915_BOX_FLIP 0x2 417 #define I915_BOX_WAIT 0x4 418 #define I915_BOX_TEXTURE_LOAD 0x8 419 #define I915_BOX_LOST_CONTEXT 0x10 420 421 /* 422 * i915 specific ioctls. 423 * 424 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 425 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 426 * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 427 */ 428 #define DRM_I915_INIT 0x00 429 #define DRM_I915_FLUSH 0x01 430 #define DRM_I915_FLIP 0x02 431 #define DRM_I915_BATCHBUFFER 0x03 432 #define DRM_I915_IRQ_EMIT 0x04 433 #define DRM_I915_IRQ_WAIT 0x05 434 #define DRM_I915_GETPARAM 0x06 435 #define DRM_I915_SETPARAM 0x07 436 #define DRM_I915_ALLOC 0x08 437 #define DRM_I915_FREE 0x09 438 #define DRM_I915_INIT_HEAP 0x0a 439 #define DRM_I915_CMDBUFFER 0x0b 440 #define DRM_I915_DESTROY_HEAP 0x0c 441 #define DRM_I915_SET_VBLANK_PIPE 0x0d 442 #define DRM_I915_GET_VBLANK_PIPE 0x0e 443 #define DRM_I915_VBLANK_SWAP 0x0f 444 #define DRM_I915_HWS_ADDR 0x11 445 #define DRM_I915_GEM_INIT 0x13 446 #define DRM_I915_GEM_EXECBUFFER 0x14 447 #define DRM_I915_GEM_PIN 0x15 448 #define DRM_I915_GEM_UNPIN 0x16 449 #define DRM_I915_GEM_BUSY 0x17 450 #define DRM_I915_GEM_THROTTLE 0x18 451 #define DRM_I915_GEM_ENTERVT 0x19 452 #define DRM_I915_GEM_LEAVEVT 0x1a 453 #define DRM_I915_GEM_CREATE 0x1b 454 #define DRM_I915_GEM_PREAD 0x1c 455 #define DRM_I915_GEM_PWRITE 0x1d 456 #define DRM_I915_GEM_MMAP 0x1e 457 #define DRM_I915_GEM_SET_DOMAIN 0x1f 458 #define DRM_I915_GEM_SW_FINISH 0x20 459 #define DRM_I915_GEM_SET_TILING 0x21 460 #define DRM_I915_GEM_GET_TILING 0x22 461 #define DRM_I915_GEM_GET_APERTURE 0x23 462 #define DRM_I915_GEM_MMAP_GTT 0x24 463 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 464 #define DRM_I915_GEM_MADVISE 0x26 465 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 466 #define DRM_I915_OVERLAY_ATTRS 0x28 467 #define DRM_I915_GEM_EXECBUFFER2 0x29 468 #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 469 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 470 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 471 #define DRM_I915_GEM_WAIT 0x2c 472 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 473 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 474 #define DRM_I915_GEM_SET_CACHING 0x2f 475 #define DRM_I915_GEM_GET_CACHING 0x30 476 #define DRM_I915_REG_READ 0x31 477 #define DRM_I915_GET_RESET_STATS 0x32 478 #define DRM_I915_GEM_USERPTR 0x33 479 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 480 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 481 #define DRM_I915_PERF_OPEN 0x36 482 #define DRM_I915_PERF_ADD_CONFIG 0x37 483 #define DRM_I915_PERF_REMOVE_CONFIG 0x38 484 #define DRM_I915_QUERY 0x39 485 #define DRM_I915_GEM_VM_CREATE 0x3a 486 #define DRM_I915_GEM_VM_DESTROY 0x3b 487 #define DRM_I915_GEM_CREATE_EXT 0x3c 488 /* Must be kept compact -- no holes */ 489 490 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 491 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 492 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 493 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 494 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 495 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 496 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 497 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 498 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 499 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 500 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 501 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 502 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 503 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 504 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 505 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 506 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 507 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 508 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 509 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 510 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 511 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 512 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 513 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 514 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 515 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 516 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 517 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 518 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 519 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 520 #define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext) 521 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 522 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 523 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 524 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 525 #define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset) 526 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 527 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 528 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 529 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 530 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 531 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 532 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 533 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 534 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 535 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 536 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 537 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 538 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 539 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext) 540 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 541 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 542 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 543 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 544 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 545 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 546 #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 547 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) 548 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) 549 #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) 550 #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control) 551 #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control) 552 553 /* Allow drivers to submit batchbuffers directly to hardware, relying 554 * on the security mechanisms provided by hardware. 555 */ 556 typedef struct drm_i915_batchbuffer { 557 int start; /* agp offset */ 558 int used; /* nr bytes in use */ 559 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 560 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 561 int num_cliprects; /* mulitpass with multiple cliprects? */ 562 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 563 } drm_i915_batchbuffer_t; 564 565 /* As above, but pass a pointer to userspace buffer which can be 566 * validated by the kernel prior to sending to hardware. 567 */ 568 typedef struct _drm_i915_cmdbuffer { 569 char __user *buf; /* pointer to userspace command buffer */ 570 int sz; /* nr bytes in buf */ 571 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 572 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 573 int num_cliprects; /* mulitpass with multiple cliprects? */ 574 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 575 } drm_i915_cmdbuffer_t; 576 577 /* Userspace can request & wait on irq's: 578 */ 579 typedef struct drm_i915_irq_emit { 580 int __user *irq_seq; 581 } drm_i915_irq_emit_t; 582 583 typedef struct drm_i915_irq_wait { 584 int irq_seq; 585 } drm_i915_irq_wait_t; 586 587 /* 588 * Different modes of per-process Graphics Translation Table, 589 * see I915_PARAM_HAS_ALIASING_PPGTT 590 */ 591 #define I915_GEM_PPGTT_NONE 0 592 #define I915_GEM_PPGTT_ALIASING 1 593 #define I915_GEM_PPGTT_FULL 2 594 595 /* Ioctl to query kernel params: 596 */ 597 #define I915_PARAM_IRQ_ACTIVE 1 598 #define I915_PARAM_ALLOW_BATCHBUFFER 2 599 #define I915_PARAM_LAST_DISPATCH 3 600 #define I915_PARAM_CHIPSET_ID 4 601 #define I915_PARAM_HAS_GEM 5 602 #define I915_PARAM_NUM_FENCES_AVAIL 6 603 #define I915_PARAM_HAS_OVERLAY 7 604 #define I915_PARAM_HAS_PAGEFLIPPING 8 605 #define I915_PARAM_HAS_EXECBUF2 9 606 #define I915_PARAM_HAS_BSD 10 607 #define I915_PARAM_HAS_BLT 11 608 #define I915_PARAM_HAS_RELAXED_FENCING 12 609 #define I915_PARAM_HAS_COHERENT_RINGS 13 610 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 611 #define I915_PARAM_HAS_RELAXED_DELTA 15 612 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 613 #define I915_PARAM_HAS_LLC 17 614 #define I915_PARAM_HAS_ALIASING_PPGTT 18 615 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 616 #define I915_PARAM_HAS_SEMAPHORES 20 617 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 618 #define I915_PARAM_HAS_VEBOX 22 619 #define I915_PARAM_HAS_SECURE_BATCHES 23 620 #define I915_PARAM_HAS_PINNED_BATCHES 24 621 #define I915_PARAM_HAS_EXEC_NO_RELOC 25 622 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 623 #define I915_PARAM_HAS_WT 27 624 #define I915_PARAM_CMD_PARSER_VERSION 28 625 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 626 #define I915_PARAM_MMAP_VERSION 30 627 #define I915_PARAM_HAS_BSD2 31 628 #define I915_PARAM_REVISION 32 629 #define I915_PARAM_SUBSLICE_TOTAL 33 630 #define I915_PARAM_EU_TOTAL 34 631 #define I915_PARAM_HAS_GPU_RESET 35 632 #define I915_PARAM_HAS_RESOURCE_STREAMER 36 633 #define I915_PARAM_HAS_EXEC_SOFTPIN 37 634 #define I915_PARAM_HAS_POOLED_EU 38 635 #define I915_PARAM_MIN_EU_IN_POOL 39 636 #define I915_PARAM_MMAP_GTT_VERSION 40 637 638 /* 639 * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution 640 * priorities and the driver will attempt to execute batches in priority order. 641 * The param returns a capability bitmask, nonzero implies that the scheduler 642 * is enabled, with different features present according to the mask. 643 * 644 * The initial priority for each batch is supplied by the context and is 645 * controlled via I915_CONTEXT_PARAM_PRIORITY. 646 */ 647 #define I915_PARAM_HAS_SCHEDULER 41 648 #define I915_SCHEDULER_CAP_ENABLED (1ul << 0) 649 #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) 650 #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) 651 #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) 652 #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) 653 /* 654 * Indicates the 2k user priority levels are statically mapped into 3 buckets as 655 * follows: 656 * 657 * -1k to -1 Low priority 658 * 0 Normal priority 659 * 1 to 1k Highest priority 660 */ 661 #define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5) 662 663 /* 664 * Query the status of HuC load. 665 * 666 * The query can fail in the following scenarios with the listed error codes: 667 * -ENODEV if HuC is not present on this platform, 668 * -EOPNOTSUPP if HuC firmware usage is disabled, 669 * -ENOPKG if HuC firmware fetch failed, 670 * -ENOEXEC if HuC firmware is invalid or mismatched, 671 * -ENOMEM if i915 failed to prepare the FW objects for transfer to the uC, 672 * -EIO if the FW transfer or the FW authentication failed. 673 * 674 * If the IOCTL is successful, the returned parameter will be set to one of the 675 * following values: 676 * * 0 if HuC firmware load is not complete, 677 * * 1 if HuC firmware is loaded and fully authenticated, 678 * * 2 if HuC firmware is loaded and authenticated for clear media only 679 */ 680 #define I915_PARAM_HUC_STATUS 42 681 682 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of 683 * synchronisation with implicit fencing on individual objects. 684 * See EXEC_OBJECT_ASYNC. 685 */ 686 #define I915_PARAM_HAS_EXEC_ASYNC 43 687 688 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support - 689 * both being able to pass in a sync_file fd to wait upon before executing, 690 * and being able to return a new sync_file fd that is signaled when the 691 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT. 692 */ 693 #define I915_PARAM_HAS_EXEC_FENCE 44 694 695 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture 696 * user-specified buffers for post-mortem debugging of GPU hangs. See 697 * EXEC_OBJECT_CAPTURE. 698 */ 699 #define I915_PARAM_HAS_EXEC_CAPTURE 45 700 701 #define I915_PARAM_SLICE_MASK 46 702 703 /* Assuming it's uniform for each slice, this queries the mask of subslices 704 * per-slice for this system. 705 */ 706 #define I915_PARAM_SUBSLICE_MASK 47 707 708 /* 709 * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer 710 * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST. 711 */ 712 #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 713 714 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of 715 * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY. 716 */ 717 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 718 719 /* 720 * Query whether every context (both per-file default and user created) is 721 * isolated (insofar as HW supports). If this parameter is not true, then 722 * freshly created contexts may inherit values from an existing context, 723 * rather than default HW values. If true, it also ensures (insofar as HW 724 * supports) that all state set by this context will not leak to any other 725 * context. 726 * 727 * As not every engine across every gen support contexts, the returned 728 * value reports the support of context isolation for individual engines by 729 * returning a bitmask of each engine class set to true if that class supports 730 * isolation. 731 */ 732 #define I915_PARAM_HAS_CONTEXT_ISOLATION 50 733 734 /* Frequency of the command streamer timestamps given by the *_TIMESTAMP 735 * registers. This used to be fixed per platform but from CNL onwards, this 736 * might vary depending on the parts. 737 */ 738 #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 739 740 /* 741 * Once upon a time we supposed that writes through the GGTT would be 742 * immediately in physical memory (once flushed out of the CPU path). However, 743 * on a few different processors and chipsets, this is not necessarily the case 744 * as the writes appear to be buffered internally. Thus a read of the backing 745 * storage (physical memory) via a different path (with different physical tags 746 * to the indirect write via the GGTT) will see stale values from before 747 * the GGTT write. Inside the kernel, we can for the most part keep track of 748 * the different read/write domains in use (e.g. set-domain), but the assumption 749 * of coherency is baked into the ABI, hence reporting its true state in this 750 * parameter. 751 * 752 * Reports true when writes via mmap_gtt are immediately visible following an 753 * lfence to flush the WCB. 754 * 755 * Reports false when writes via mmap_gtt are indeterminately delayed in an in 756 * internal buffer and are _not_ immediately visible to third parties accessing 757 * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC 758 * communications channel when reporting false is strongly disadvised. 759 */ 760 #define I915_PARAM_MMAP_GTT_COHERENT 52 761 762 /* 763 * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel 764 * execution through use of explicit fence support. 765 * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT. 766 */ 767 #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53 768 769 /* 770 * Revision of the i915-perf uAPI. The value returned helps determine what 771 * i915-perf features are available. See drm_i915_perf_property_id. 772 */ 773 #define I915_PARAM_PERF_REVISION 54 774 775 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of 776 * timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See 777 * I915_EXEC_USE_EXTENSIONS. 778 */ 779 #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55 780 781 /* Query if the kernel supports the I915_USERPTR_PROBE flag. */ 782 #define I915_PARAM_HAS_USERPTR_PROBE 56 783 784 /* 785 * Frequency of the timestamps in OA reports. This used to be the same as the CS 786 * timestamp frequency, but differs on some platforms. 787 */ 788 #define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57 789 790 /* 791 * Query the status of PXP support in i915. 792 * 793 * The query can fail in the following scenarios with the listed error codes: 794 * -ENODEV = PXP support is not available on the GPU device or in the 795 * kernel due to missing component drivers or kernel configs. 796 * 797 * If the IOCTL is successful, the returned parameter will be set to one of 798 * the following values: 799 * 1 = PXP feature is supported and is ready for use. 800 * 2 = PXP feature is supported but should be ready soon (pending 801 * initialization of non-i915 system dependencies). 802 * 803 * NOTE: When param is supported (positive return values), user space should 804 * still refer to the GEM PXP context-creation UAPI header specs to be 805 * aware of possible failure due to system state machine at the time. 806 */ 807 #define I915_PARAM_PXP_STATUS 58 808 809 /* 810 * Query if kernel allows marking a context to send a Freq hint to SLPC. This 811 * will enable use of the strategies allowed by the SLPC algorithm. 812 */ 813 #define I915_PARAM_HAS_CONTEXT_FREQ_HINT 59 814 815 /* Must be kept compact -- no holes and well documented */ 816 817 /** 818 * struct drm_i915_getparam - Driver parameter query structure. 819 */ 820 struct drm_i915_getparam { 821 /** @param: Driver parameter to query. */ 822 __s32 param; 823 824 /** 825 * @value: Address of memory where queried value should be put. 826 * 827 * WARNING: Using pointers instead of fixed-size u64 means we need to write 828 * compat32 code. Don't repeat this mistake. 829 */ 830 int __user *value; 831 }; 832 833 /** 834 * typedef drm_i915_getparam_t - Driver parameter query structure. 835 * See struct drm_i915_getparam. 836 */ 837 typedef struct drm_i915_getparam drm_i915_getparam_t; 838 839 /* Ioctl to set kernel params: 840 */ 841 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 842 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 843 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 844 #define I915_SETPARAM_NUM_USED_FENCES 4 845 /* Must be kept compact -- no holes */ 846 847 typedef struct drm_i915_setparam { 848 int param; 849 int value; 850 } drm_i915_setparam_t; 851 852 /* A memory manager for regions of shared memory: 853 */ 854 #define I915_MEM_REGION_AGP 1 855 856 typedef struct drm_i915_mem_alloc { 857 int region; 858 int alignment; 859 int size; 860 int __user *region_offset; /* offset from start of fb or agp */ 861 } drm_i915_mem_alloc_t; 862 863 typedef struct drm_i915_mem_free { 864 int region; 865 int region_offset; 866 } drm_i915_mem_free_t; 867 868 typedef struct drm_i915_mem_init_heap { 869 int region; 870 int size; 871 int start; 872 } drm_i915_mem_init_heap_t; 873 874 /* Allow memory manager to be torn down and re-initialized (eg on 875 * rotate): 876 */ 877 typedef struct drm_i915_mem_destroy_heap { 878 int region; 879 } drm_i915_mem_destroy_heap_t; 880 881 /* Allow X server to configure which pipes to monitor for vblank signals 882 */ 883 #define DRM_I915_VBLANK_PIPE_A 1 884 #define DRM_I915_VBLANK_PIPE_B 2 885 886 typedef struct drm_i915_vblank_pipe { 887 int pipe; 888 } drm_i915_vblank_pipe_t; 889 890 /* Schedule buffer swap at given vertical blank: 891 */ 892 typedef struct drm_i915_vblank_swap { 893 drm_drawable_t drawable; 894 enum drm_vblank_seq_type seqtype; 895 unsigned int sequence; 896 } drm_i915_vblank_swap_t; 897 898 typedef struct drm_i915_hws_addr { 899 __u64 addr; 900 } drm_i915_hws_addr_t; 901 902 struct drm_i915_gem_init { 903 /** 904 * Beginning offset in the GTT to be managed by the DRM memory 905 * manager. 906 */ 907 __u64 gtt_start; 908 /** 909 * Ending offset in the GTT to be managed by the DRM memory 910 * manager. 911 */ 912 __u64 gtt_end; 913 }; 914 915 struct drm_i915_gem_create { 916 /** 917 * Requested size for the object. 918 * 919 * The (page-aligned) allocated size for the object will be returned. 920 */ 921 __u64 size; 922 /** 923 * Returned handle for the object. 924 * 925 * Object handles are nonzero. 926 */ 927 __u32 handle; 928 __u32 pad; 929 }; 930 931 struct drm_i915_gem_pread { 932 /** Handle for the object being read. */ 933 __u32 handle; 934 __u32 pad; 935 /** Offset into the object to read from */ 936 __u64 offset; 937 /** Length of data to read */ 938 __u64 size; 939 /** 940 * Pointer to write the data into. 941 * 942 * This is a fixed-size type for 32/64 compatibility. 943 */ 944 __u64 data_ptr; 945 }; 946 947 struct drm_i915_gem_pwrite { 948 /** Handle for the object being written to. */ 949 __u32 handle; 950 __u32 pad; 951 /** Offset into the object to write to */ 952 __u64 offset; 953 /** Length of data to write */ 954 __u64 size; 955 /** 956 * Pointer to read the data from. 957 * 958 * This is a fixed-size type for 32/64 compatibility. 959 */ 960 __u64 data_ptr; 961 }; 962 963 struct drm_i915_gem_mmap { 964 /** Handle for the object being mapped. */ 965 __u32 handle; 966 __u32 pad; 967 /** Offset in the object to map. */ 968 __u64 offset; 969 /** 970 * Length of data to map. 971 * 972 * The value will be page-aligned. 973 */ 974 __u64 size; 975 /** 976 * Returned pointer the data was mapped at. 977 * 978 * This is a fixed-size type for 32/64 compatibility. 979 */ 980 __u64 addr_ptr; 981 982 /** 983 * Flags for extended behaviour. 984 * 985 * Added in version 2. 986 */ 987 __u64 flags; 988 #define I915_MMAP_WC 0x1 989 }; 990 991 struct drm_i915_gem_mmap_gtt { 992 /** Handle for the object being mapped. */ 993 __u32 handle; 994 __u32 pad; 995 /** 996 * Fake offset to use for subsequent mmap call 997 * 998 * This is a fixed-size type for 32/64 compatibility. 999 */ 1000 __u64 offset; 1001 }; 1002 1003 /** 1004 * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object. 1005 * 1006 * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl, 1007 * and is used to retrieve the fake offset to mmap an object specified by &handle. 1008 * 1009 * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+. 1010 * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave 1011 * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`. 1012 */ 1013 struct drm_i915_gem_mmap_offset { 1014 /** @handle: Handle for the object being mapped. */ 1015 __u32 handle; 1016 /** @pad: Must be zero */ 1017 __u32 pad; 1018 /** 1019 * @offset: The fake offset to use for subsequent mmap call 1020 * 1021 * This is a fixed-size type for 32/64 compatibility. 1022 */ 1023 __u64 offset; 1024 1025 /** 1026 * @flags: Flags for extended behaviour. 1027 * 1028 * It is mandatory that one of the `MMAP_OFFSET` types 1029 * should be included: 1030 * 1031 * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined) 1032 * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching. 1033 * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching. 1034 * - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching. 1035 * 1036 * On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid 1037 * type. On devices without local memory, this caching mode is invalid. 1038 * 1039 * As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will 1040 * be used, depending on the object placement on creation. WB will be used 1041 * when the object can only exist in system memory, WC otherwise. 1042 */ 1043 __u64 flags; 1044 1045 #define I915_MMAP_OFFSET_GTT 0 1046 #define I915_MMAP_OFFSET_WC 1 1047 #define I915_MMAP_OFFSET_WB 2 1048 #define I915_MMAP_OFFSET_UC 3 1049 #define I915_MMAP_OFFSET_FIXED 4 1050 1051 /** 1052 * @extensions: Zero-terminated chain of extensions. 1053 * 1054 * No current extensions defined; mbz. 1055 */ 1056 __u64 extensions; 1057 }; 1058 1059 /** 1060 * struct drm_i915_gem_set_domain - Adjust the objects write or read domain, in 1061 * preparation for accessing the pages via some CPU domain. 1062 * 1063 * Specifying a new write or read domain will flush the object out of the 1064 * previous domain(if required), before then updating the objects domain 1065 * tracking with the new domain. 1066 * 1067 * Note this might involve waiting for the object first if it is still active on 1068 * the GPU. 1069 * 1070 * Supported values for @read_domains and @write_domain: 1071 * 1072 * - I915_GEM_DOMAIN_WC: Uncached write-combined domain 1073 * - I915_GEM_DOMAIN_CPU: CPU cache domain 1074 * - I915_GEM_DOMAIN_GTT: Mappable aperture domain 1075 * 1076 * All other domains are rejected. 1077 * 1078 * Note that for discrete, starting from DG1, this is no longer supported, and 1079 * is instead rejected. On such platforms the CPU domain is effectively static, 1080 * where we also only support a single &drm_i915_gem_mmap_offset cache mode, 1081 * which can't be set explicitly and instead depends on the object placements, 1082 * as per the below. 1083 * 1084 * Implicit caching rules, starting from DG1: 1085 * 1086 * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) 1087 * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and 1088 * mapped as write-combined only. 1089 * 1090 * - Everything else is always allocated and mapped as write-back, with the 1091 * guarantee that everything is also coherent with the GPU. 1092 * 1093 * Note that this is likely to change in the future again, where we might need 1094 * more flexibility on future devices, so making this all explicit as part of a 1095 * new &drm_i915_gem_create_ext extension is probable. 1096 */ 1097 struct drm_i915_gem_set_domain { 1098 /** @handle: Handle for the object. */ 1099 __u32 handle; 1100 1101 /** @read_domains: New read domains. */ 1102 __u32 read_domains; 1103 1104 /** 1105 * @write_domain: New write domain. 1106 * 1107 * Note that having something in the write domain implies it's in the 1108 * read domain, and only that read domain. 1109 */ 1110 __u32 write_domain; 1111 }; 1112 1113 struct drm_i915_gem_sw_finish { 1114 /** Handle for the object */ 1115 __u32 handle; 1116 }; 1117 1118 struct drm_i915_gem_relocation_entry { 1119 /** 1120 * Handle of the buffer being pointed to by this relocation entry. 1121 * 1122 * It's appealing to make this be an index into the mm_validate_entry 1123 * list to refer to the buffer, but this allows the driver to create 1124 * a relocation list for state buffers and not re-write it per 1125 * exec using the buffer. 1126 */ 1127 __u32 target_handle; 1128 1129 /** 1130 * Value to be added to the offset of the target buffer to make up 1131 * the relocation entry. 1132 */ 1133 __u32 delta; 1134 1135 /** Offset in the buffer the relocation entry will be written into */ 1136 __u64 offset; 1137 1138 /** 1139 * Offset value of the target buffer that the relocation entry was last 1140 * written as. 1141 * 1142 * If the buffer has the same offset as last time, we can skip syncing 1143 * and writing the relocation. This value is written back out by 1144 * the execbuffer ioctl when the relocation is written. 1145 */ 1146 __u64 presumed_offset; 1147 1148 /** 1149 * Target memory domains read by this operation. 1150 */ 1151 __u32 read_domains; 1152 1153 /** 1154 * Target memory domains written by this operation. 1155 * 1156 * Note that only one domain may be written by the whole 1157 * execbuffer operation, so that where there are conflicts, 1158 * the application will get -EINVAL back. 1159 */ 1160 __u32 write_domain; 1161 }; 1162 1163 /** @{ 1164 * Intel memory domains 1165 * 1166 * Most of these just align with the various caches in 1167 * the system and are used to flush and invalidate as 1168 * objects end up cached in different domains. 1169 */ 1170 /** CPU cache */ 1171 #define I915_GEM_DOMAIN_CPU 0x00000001 1172 /** Render cache, used by 2D and 3D drawing */ 1173 #define I915_GEM_DOMAIN_RENDER 0x00000002 1174 /** Sampler cache, used by texture engine */ 1175 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 1176 /** Command queue, used to load batch buffers */ 1177 #define I915_GEM_DOMAIN_COMMAND 0x00000008 1178 /** Instruction cache, used by shader programs */ 1179 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 1180 /** Vertex address cache */ 1181 #define I915_GEM_DOMAIN_VERTEX 0x00000020 1182 /** GTT domain - aperture and scanout */ 1183 #define I915_GEM_DOMAIN_GTT 0x00000040 1184 /** WC domain - uncached access */ 1185 #define I915_GEM_DOMAIN_WC 0x00000080 1186 /** @} */ 1187 1188 struct drm_i915_gem_exec_object { 1189 /** 1190 * User's handle for a buffer to be bound into the GTT for this 1191 * operation. 1192 */ 1193 __u32 handle; 1194 1195 /** Number of relocations to be performed on this buffer */ 1196 __u32 relocation_count; 1197 /** 1198 * Pointer to array of struct drm_i915_gem_relocation_entry containing 1199 * the relocations to be performed in this buffer. 1200 */ 1201 __u64 relocs_ptr; 1202 1203 /** Required alignment in graphics aperture */ 1204 __u64 alignment; 1205 1206 /** 1207 * Returned value of the updated offset of the object, for future 1208 * presumed_offset writes. 1209 */ 1210 __u64 offset; 1211 }; 1212 1213 /* DRM_IOCTL_I915_GEM_EXECBUFFER was removed in Linux 5.13 */ 1214 struct drm_i915_gem_execbuffer { 1215 /** 1216 * List of buffers to be validated with their relocations to be 1217 * performend on them. 1218 * 1219 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 1220 * 1221 * These buffers must be listed in an order such that all relocations 1222 * a buffer is performing refer to buffers that have already appeared 1223 * in the validate list. 1224 */ 1225 __u64 buffers_ptr; 1226 __u32 buffer_count; 1227 1228 /** Offset in the batchbuffer to start execution from. */ 1229 __u32 batch_start_offset; 1230 /** Bytes used in batchbuffer from batch_start_offset */ 1231 __u32 batch_len; 1232 __u32 DR1; 1233 __u32 DR4; 1234 __u32 num_cliprects; 1235 /** This is a struct drm_clip_rect *cliprects */ 1236 __u64 cliprects_ptr; 1237 }; 1238 1239 struct drm_i915_gem_exec_object2 { 1240 /** 1241 * User's handle for a buffer to be bound into the GTT for this 1242 * operation. 1243 */ 1244 __u32 handle; 1245 1246 /** Number of relocations to be performed on this buffer */ 1247 __u32 relocation_count; 1248 /** 1249 * Pointer to array of struct drm_i915_gem_relocation_entry containing 1250 * the relocations to be performed in this buffer. 1251 */ 1252 __u64 relocs_ptr; 1253 1254 /** Required alignment in graphics aperture */ 1255 __u64 alignment; 1256 1257 /** 1258 * When the EXEC_OBJECT_PINNED flag is specified this is populated by 1259 * the user with the GTT offset at which this object will be pinned. 1260 * 1261 * When the I915_EXEC_NO_RELOC flag is specified this must contain the 1262 * presumed_offset of the object. 1263 * 1264 * During execbuffer2 the kernel populates it with the value of the 1265 * current GTT offset of the object, for future presumed_offset writes. 1266 * 1267 * See struct drm_i915_gem_create_ext for the rules when dealing with 1268 * alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with 1269 * minimum page sizes, like DG2. 1270 */ 1271 __u64 offset; 1272 1273 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 1274 #define EXEC_OBJECT_NEEDS_GTT (1<<1) 1275 #define EXEC_OBJECT_WRITE (1<<2) 1276 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 1277 #define EXEC_OBJECT_PINNED (1<<4) 1278 #define EXEC_OBJECT_PAD_TO_SIZE (1<<5) 1279 /* The kernel implicitly tracks GPU activity on all GEM objects, and 1280 * synchronises operations with outstanding rendering. This includes 1281 * rendering on other devices if exported via dma-buf. However, sometimes 1282 * this tracking is too coarse and the user knows better. For example, 1283 * if the object is split into non-overlapping ranges shared between different 1284 * clients or engines (i.e. suballocating objects), the implicit tracking 1285 * by kernel assumes that each operation affects the whole object rather 1286 * than an individual range, causing needless synchronisation between clients. 1287 * The kernel will also forgo any CPU cache flushes prior to rendering from 1288 * the object as the client is expected to be also handling such domain 1289 * tracking. 1290 * 1291 * The kernel maintains the implicit tracking in order to manage resources 1292 * used by the GPU - this flag only disables the synchronisation prior to 1293 * rendering with this object in this execbuf. 1294 * 1295 * Opting out of implicit synhronisation requires the user to do its own 1296 * explicit tracking to avoid rendering corruption. See, for example, 1297 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. 1298 */ 1299 #define EXEC_OBJECT_ASYNC (1<<6) 1300 /* Request that the contents of this execobject be copied into the error 1301 * state upon a GPU hang involving this batch for post-mortem debugging. 1302 * These buffers are recorded in no particular order as "user" in 1303 * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see 1304 * if the kernel supports this flag. 1305 */ 1306 #define EXEC_OBJECT_CAPTURE (1<<7) 1307 /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ 1308 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1) 1309 __u64 flags; 1310 1311 union { 1312 __u64 rsvd1; 1313 __u64 pad_to_size; 1314 }; 1315 __u64 rsvd2; 1316 }; 1317 1318 /** 1319 * struct drm_i915_gem_exec_fence - An input or output fence for the execbuf 1320 * ioctl. 1321 * 1322 * The request will wait for input fence to signal before submission. 1323 * 1324 * The returned output fence will be signaled after the completion of the 1325 * request. 1326 */ 1327 struct drm_i915_gem_exec_fence { 1328 /** @handle: User's handle for a drm_syncobj to wait on or signal. */ 1329 __u32 handle; 1330 1331 /** 1332 * @flags: Supported flags are: 1333 * 1334 * I915_EXEC_FENCE_WAIT: 1335 * Wait for the input fence before request submission. 1336 * 1337 * I915_EXEC_FENCE_SIGNAL: 1338 * Return request completion fence as output 1339 */ 1340 __u32 flags; 1341 #define I915_EXEC_FENCE_WAIT (1<<0) 1342 #define I915_EXEC_FENCE_SIGNAL (1<<1) 1343 #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)) 1344 }; 1345 1346 /** 1347 * struct drm_i915_gem_execbuffer_ext_timeline_fences - Timeline fences 1348 * for execbuf ioctl. 1349 * 1350 * This structure describes an array of drm_syncobj and associated points for 1351 * timeline variants of drm_syncobj. It is invalid to append this structure to 1352 * the execbuf if I915_EXEC_FENCE_ARRAY is set. 1353 */ 1354 struct drm_i915_gem_execbuffer_ext_timeline_fences { 1355 #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0 1356 /** @base: Extension link. See struct i915_user_extension. */ 1357 struct i915_user_extension base; 1358 1359 /** 1360 * @fence_count: Number of elements in the @handles_ptr & @value_ptr 1361 * arrays. 1362 */ 1363 __u64 fence_count; 1364 1365 /** 1366 * @handles_ptr: Pointer to an array of struct drm_i915_gem_exec_fence 1367 * of length @fence_count. 1368 */ 1369 __u64 handles_ptr; 1370 1371 /** 1372 * @values_ptr: Pointer to an array of u64 values of length 1373 * @fence_count. 1374 * Values must be 0 for a binary drm_syncobj. A Value of 0 for a 1375 * timeline drm_syncobj is invalid as it turns a drm_syncobj into a 1376 * binary one. 1377 */ 1378 __u64 values_ptr; 1379 }; 1380 1381 /** 1382 * struct drm_i915_gem_execbuffer2 - Structure for DRM_I915_GEM_EXECBUFFER2 1383 * ioctl. 1384 */ 1385 struct drm_i915_gem_execbuffer2 { 1386 /** @buffers_ptr: Pointer to a list of gem_exec_object2 structs */ 1387 __u64 buffers_ptr; 1388 1389 /** @buffer_count: Number of elements in @buffers_ptr array */ 1390 __u32 buffer_count; 1391 1392 /** 1393 * @batch_start_offset: Offset in the batchbuffer to start execution 1394 * from. 1395 */ 1396 __u32 batch_start_offset; 1397 1398 /** 1399 * @batch_len: Length in bytes of the batch buffer, starting from the 1400 * @batch_start_offset. If 0, length is assumed to be the batch buffer 1401 * object size. 1402 */ 1403 __u32 batch_len; 1404 1405 /** @DR1: deprecated */ 1406 __u32 DR1; 1407 1408 /** @DR4: deprecated */ 1409 __u32 DR4; 1410 1411 /** @num_cliprects: See @cliprects_ptr */ 1412 __u32 num_cliprects; 1413 1414 /** 1415 * @cliprects_ptr: Kernel clipping was a DRI1 misfeature. 1416 * 1417 * It is invalid to use this field if I915_EXEC_FENCE_ARRAY or 1418 * I915_EXEC_USE_EXTENSIONS flags are not set. 1419 * 1420 * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array 1421 * of &drm_i915_gem_exec_fence and @num_cliprects is the length of the 1422 * array. 1423 * 1424 * If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a 1425 * single &i915_user_extension and num_cliprects is 0. 1426 */ 1427 __u64 cliprects_ptr; 1428 1429 /** @flags: Execbuf flags */ 1430 __u64 flags; 1431 #define I915_EXEC_RING_MASK (0x3f) 1432 #define I915_EXEC_DEFAULT (0<<0) 1433 #define I915_EXEC_RENDER (1<<0) 1434 #define I915_EXEC_BSD (2<<0) 1435 #define I915_EXEC_BLT (3<<0) 1436 #define I915_EXEC_VEBOX (4<<0) 1437 1438 /* Used for switching the constants addressing mode on gen4+ RENDER ring. 1439 * Gen6+ only supports relative addressing to dynamic state (default) and 1440 * absolute addressing. 1441 * 1442 * These flags are ignored for the BSD and BLT rings. 1443 */ 1444 #define I915_EXEC_CONSTANTS_MASK (3<<6) 1445 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 1446 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 1447 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 1448 1449 /** Resets the SO write offset registers for transform feedback on gen7. */ 1450 #define I915_EXEC_GEN7_SOL_RESET (1<<8) 1451 1452 /** Request a privileged ("secure") batch buffer. Note only available for 1453 * DRM_ROOT_ONLY | DRM_MASTER processes. 1454 */ 1455 #define I915_EXEC_SECURE (1<<9) 1456 1457 /** Inform the kernel that the batch is and will always be pinned. This 1458 * negates the requirement for a workaround to be performed to avoid 1459 * an incoherent CS (such as can be found on 830/845). If this flag is 1460 * not passed, the kernel will endeavour to make sure the batch is 1461 * coherent with the CS before execution. If this flag is passed, 1462 * userspace assumes the responsibility for ensuring the same. 1463 */ 1464 #define I915_EXEC_IS_PINNED (1<<10) 1465 1466 /** Provide a hint to the kernel that the command stream and auxiliary 1467 * state buffers already holds the correct presumed addresses and so the 1468 * relocation process may be skipped if no buffers need to be moved in 1469 * preparation for the execbuffer. 1470 */ 1471 #define I915_EXEC_NO_RELOC (1<<11) 1472 1473 /** Use the reloc.handle as an index into the exec object array rather 1474 * than as the per-file handle. 1475 */ 1476 #define I915_EXEC_HANDLE_LUT (1<<12) 1477 1478 /** Used for switching BSD rings on the platforms with two BSD rings */ 1479 #define I915_EXEC_BSD_SHIFT (13) 1480 #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 1481 /* default ping-pong mode */ 1482 #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 1483 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 1484 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 1485 1486 /** Tell the kernel that the batchbuffer is processed by 1487 * the resource streamer. 1488 */ 1489 #define I915_EXEC_RESOURCE_STREAMER (1<<15) 1490 1491 /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent 1492 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing 1493 * the batch. 1494 * 1495 * Returns -EINVAL if the sync_file fd cannot be found. 1496 */ 1497 #define I915_EXEC_FENCE_IN (1<<16) 1498 1499 /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd 1500 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given 1501 * to the caller, and it should be close() after use. (The fd is a regular 1502 * file descriptor and will be cleaned up on process termination. It holds 1503 * a reference to the request, but nothing else.) 1504 * 1505 * The sync_file fd can be combined with other sync_file and passed either 1506 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip 1507 * will only occur after this request completes), or to other devices. 1508 * 1509 * Using I915_EXEC_FENCE_OUT requires use of 1510 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written 1511 * back to userspace. Failure to do so will cause the out-fence to always 1512 * be reported as zero, and the real fence fd to be leaked. 1513 */ 1514 #define I915_EXEC_FENCE_OUT (1<<17) 1515 1516 /* 1517 * Traditionally the execbuf ioctl has only considered the final element in 1518 * the execobject[] to be the executable batch. Often though, the client 1519 * will known the batch object prior to construction and being able to place 1520 * it into the execobject[] array first can simplify the relocation tracking. 1521 * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the 1522 * execobject[] as the * batch instead (the default is to use the last 1523 * element). 1524 */ 1525 #define I915_EXEC_BATCH_FIRST (1<<18) 1526 1527 /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr 1528 * define an array of i915_gem_exec_fence structures which specify a set of 1529 * dma fences to wait upon or signal. 1530 */ 1531 #define I915_EXEC_FENCE_ARRAY (1<<19) 1532 1533 /* 1534 * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent 1535 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing 1536 * the batch. 1537 * 1538 * Returns -EINVAL if the sync_file fd cannot be found. 1539 */ 1540 #define I915_EXEC_FENCE_SUBMIT (1 << 20) 1541 1542 /* 1543 * Setting I915_EXEC_USE_EXTENSIONS implies that 1544 * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked 1545 * list of i915_user_extension. Each i915_user_extension node is the base of a 1546 * larger structure. The list of supported structures are listed in the 1547 * drm_i915_gem_execbuffer_ext enum. 1548 */ 1549 #define I915_EXEC_USE_EXTENSIONS (1 << 21) 1550 #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)) 1551 1552 /** @rsvd1: Context id */ 1553 __u64 rsvd1; 1554 1555 /** 1556 * @rsvd2: in and out sync_file file descriptors. 1557 * 1558 * When I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the 1559 * lower 32 bits of this field will have the in sync_file fd (input). 1560 * 1561 * When I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this 1562 * field will have the out sync_file fd (output). 1563 */ 1564 __u64 rsvd2; 1565 }; 1566 1567 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 1568 #define i915_execbuffer2_set_context_id(eb2, context) \ 1569 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 1570 #define i915_execbuffer2_get_context_id(eb2) \ 1571 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 1572 1573 struct drm_i915_gem_pin { 1574 /** Handle of the buffer to be pinned. */ 1575 __u32 handle; 1576 __u32 pad; 1577 1578 /** alignment required within the aperture */ 1579 __u64 alignment; 1580 1581 /** Returned GTT offset of the buffer. */ 1582 __u64 offset; 1583 }; 1584 1585 struct drm_i915_gem_unpin { 1586 /** Handle of the buffer to be unpinned. */ 1587 __u32 handle; 1588 __u32 pad; 1589 }; 1590 1591 struct drm_i915_gem_busy { 1592 /** Handle of the buffer to check for busy */ 1593 __u32 handle; 1594 1595 /** Return busy status 1596 * 1597 * A return of 0 implies that the object is idle (after 1598 * having flushed any pending activity), and a non-zero return that 1599 * the object is still in-flight on the GPU. (The GPU has not yet 1600 * signaled completion for all pending requests that reference the 1601 * object.) An object is guaranteed to become idle eventually (so 1602 * long as no new GPU commands are executed upon it). Due to the 1603 * asynchronous nature of the hardware, an object reported 1604 * as busy may become idle before the ioctl is completed. 1605 * 1606 * Furthermore, if the object is busy, which engine is busy is only 1607 * provided as a guide and only indirectly by reporting its class 1608 * (there may be more than one engine in each class). There are race 1609 * conditions which prevent the report of which engines are busy from 1610 * being always accurate. However, the converse is not true. If the 1611 * object is idle, the result of the ioctl, that all engines are idle, 1612 * is accurate. 1613 * 1614 * The returned dword is split into two fields to indicate both 1615 * the engine classes on which the object is being read, and the 1616 * engine class on which it is currently being written (if any). 1617 * 1618 * The low word (bits 0:15) indicate if the object is being written 1619 * to by any engine (there can only be one, as the GEM implicit 1620 * synchronisation rules force writes to be serialised). Only the 1621 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as 1622 * 1 not 0 etc) for the last write is reported. 1623 * 1624 * The high word (bits 16:31) are a bitmask of which engines classes 1625 * are currently reading from the object. Multiple engines may be 1626 * reading from the object simultaneously. 1627 * 1628 * The value of each engine class is the same as specified in the 1629 * I915_CONTEXT_PARAM_ENGINES context parameter and via perf, i.e. 1630 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc. 1631 * Some hardware may have parallel execution engines, e.g. multiple 1632 * media engines, which are mapped to the same class identifier and so 1633 * are not separately reported for busyness. 1634 * 1635 * Caveat emptor: 1636 * Only the boolean result of this query is reliable; that is whether 1637 * the object is idle or busy. The report of which engines are busy 1638 * should be only used as a heuristic. 1639 */ 1640 __u32 busy; 1641 }; 1642 1643 /** 1644 * struct drm_i915_gem_caching - Set or get the caching for given object 1645 * handle. 1646 * 1647 * Allow userspace to control the GTT caching bits for a given object when the 1648 * object is later mapped through the ppGTT(or GGTT on older platforms lacking 1649 * ppGTT support, or if the object is used for scanout). Note that this might 1650 * require unbinding the object from the GTT first, if its current caching value 1651 * doesn't match. 1652 * 1653 * Note that this all changes on discrete platforms, starting from DG1, the 1654 * set/get caching is no longer supported, and is now rejected. Instead the CPU 1655 * caching attributes(WB vs WC) will become an immutable creation time property 1656 * for the object, along with the GTT caching level. For now we don't expose any 1657 * new uAPI for this, instead on DG1 this is all implicit, although this largely 1658 * shouldn't matter since DG1 is coherent by default(without any way of 1659 * controlling it). 1660 * 1661 * Implicit caching rules, starting from DG1: 1662 * 1663 * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) 1664 * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and 1665 * mapped as write-combined only. 1666 * 1667 * - Everything else is always allocated and mapped as write-back, with the 1668 * guarantee that everything is also coherent with the GPU. 1669 * 1670 * Note that this is likely to change in the future again, where we might need 1671 * more flexibility on future devices, so making this all explicit as part of a 1672 * new &drm_i915_gem_create_ext extension is probable. 1673 * 1674 * Side note: Part of the reason for this is that changing the at-allocation-time CPU 1675 * caching attributes for the pages might be required(and is expensive) if we 1676 * need to then CPU map the pages later with different caching attributes. This 1677 * inconsistent caching behaviour, while supported on x86, is not universally 1678 * supported on other architectures. So for simplicity we opt for setting 1679 * everything at creation time, whilst also making it immutable, on discrete 1680 * platforms. 1681 */ 1682 struct drm_i915_gem_caching { 1683 /** 1684 * @handle: Handle of the buffer to set/get the caching level. 1685 */ 1686 __u32 handle; 1687 1688 /** 1689 * @caching: The GTT caching level to apply or possible return value. 1690 * 1691 * The supported @caching values: 1692 * 1693 * I915_CACHING_NONE: 1694 * 1695 * GPU access is not coherent with CPU caches. Default for machines 1696 * without an LLC. This means manual flushing might be needed, if we 1697 * want GPU access to be coherent. 1698 * 1699 * I915_CACHING_CACHED: 1700 * 1701 * GPU access is coherent with CPU caches and furthermore the data is 1702 * cached in last-level caches shared between CPU cores and the GPU GT. 1703 * 1704 * I915_CACHING_DISPLAY: 1705 * 1706 * Special GPU caching mode which is coherent with the scanout engines. 1707 * Transparently falls back to I915_CACHING_NONE on platforms where no 1708 * special cache mode (like write-through or gfdt flushing) is 1709 * available. The kernel automatically sets this mode when using a 1710 * buffer as a scanout target. Userspace can manually set this mode to 1711 * avoid a costly stall and clflush in the hotpath of drawing the first 1712 * frame. 1713 */ 1714 #define I915_CACHING_NONE 0 1715 #define I915_CACHING_CACHED 1 1716 #define I915_CACHING_DISPLAY 2 1717 __u32 caching; 1718 }; 1719 1720 #define I915_TILING_NONE 0 1721 #define I915_TILING_X 1 1722 #define I915_TILING_Y 2 1723 /* 1724 * Do not add new tiling types here. The I915_TILING_* values are for 1725 * de-tiling fence registers that no longer exist on modern platforms. Although 1726 * the hardware may support new types of tiling in general (e.g., Tile4), we 1727 * do not need to add them to the uapi that is specific to now-defunct ioctls. 1728 */ 1729 #define I915_TILING_LAST I915_TILING_Y 1730 1731 #define I915_BIT_6_SWIZZLE_NONE 0 1732 #define I915_BIT_6_SWIZZLE_9 1 1733 #define I915_BIT_6_SWIZZLE_9_10 2 1734 #define I915_BIT_6_SWIZZLE_9_11 3 1735 #define I915_BIT_6_SWIZZLE_9_10_11 4 1736 /* Not seen by userland */ 1737 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 1738 /* Seen by userland. */ 1739 #define I915_BIT_6_SWIZZLE_9_17 6 1740 #define I915_BIT_6_SWIZZLE_9_10_17 7 1741 1742 struct drm_i915_gem_set_tiling { 1743 /** Handle of the buffer to have its tiling state updated */ 1744 __u32 handle; 1745 1746 /** 1747 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1748 * I915_TILING_Y). 1749 * 1750 * This value is to be set on request, and will be updated by the 1751 * kernel on successful return with the actual chosen tiling layout. 1752 * 1753 * The tiling mode may be demoted to I915_TILING_NONE when the system 1754 * has bit 6 swizzling that can't be managed correctly by GEM. 1755 * 1756 * Buffer contents become undefined when changing tiling_mode. 1757 */ 1758 __u32 tiling_mode; 1759 1760 /** 1761 * Stride in bytes for the object when in I915_TILING_X or 1762 * I915_TILING_Y. 1763 */ 1764 __u32 stride; 1765 1766 /** 1767 * Returned address bit 6 swizzling required for CPU access through 1768 * mmap mapping. 1769 */ 1770 __u32 swizzle_mode; 1771 }; 1772 1773 struct drm_i915_gem_get_tiling { 1774 /** Handle of the buffer to get tiling state for. */ 1775 __u32 handle; 1776 1777 /** 1778 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1779 * I915_TILING_Y). 1780 */ 1781 __u32 tiling_mode; 1782 1783 /** 1784 * Returned address bit 6 swizzling required for CPU access through 1785 * mmap mapping. 1786 */ 1787 __u32 swizzle_mode; 1788 1789 /** 1790 * Returned address bit 6 swizzling required for CPU access through 1791 * mmap mapping whilst bound. 1792 */ 1793 __u32 phys_swizzle_mode; 1794 }; 1795 1796 struct drm_i915_gem_get_aperture { 1797 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 1798 __u64 aper_size; 1799 1800 /** 1801 * Available space in the aperture used by i915_gem_execbuffer, in 1802 * bytes 1803 */ 1804 __u64 aper_available_size; 1805 }; 1806 1807 struct drm_i915_get_pipe_from_crtc_id { 1808 /** ID of CRTC being requested **/ 1809 __u32 crtc_id; 1810 1811 /** pipe of requested CRTC **/ 1812 __u32 pipe; 1813 }; 1814 1815 #define I915_MADV_WILLNEED 0 1816 #define I915_MADV_DONTNEED 1 1817 #define __I915_MADV_PURGED 2 /* internal state */ 1818 1819 struct drm_i915_gem_madvise { 1820 /** Handle of the buffer to change the backing store advice */ 1821 __u32 handle; 1822 1823 /* Advice: either the buffer will be needed again in the near future, 1824 * or won't be and could be discarded under memory pressure. 1825 */ 1826 __u32 madv; 1827 1828 /** Whether the backing store still exists. */ 1829 __u32 retained; 1830 }; 1831 1832 /* flags */ 1833 #define I915_OVERLAY_TYPE_MASK 0xff 1834 #define I915_OVERLAY_YUV_PLANAR 0x01 1835 #define I915_OVERLAY_YUV_PACKED 0x02 1836 #define I915_OVERLAY_RGB 0x03 1837 1838 #define I915_OVERLAY_DEPTH_MASK 0xff00 1839 #define I915_OVERLAY_RGB24 0x1000 1840 #define I915_OVERLAY_RGB16 0x2000 1841 #define I915_OVERLAY_RGB15 0x3000 1842 #define I915_OVERLAY_YUV422 0x0100 1843 #define I915_OVERLAY_YUV411 0x0200 1844 #define I915_OVERLAY_YUV420 0x0300 1845 #define I915_OVERLAY_YUV410 0x0400 1846 1847 #define I915_OVERLAY_SWAP_MASK 0xff0000 1848 #define I915_OVERLAY_NO_SWAP 0x000000 1849 #define I915_OVERLAY_UV_SWAP 0x010000 1850 #define I915_OVERLAY_Y_SWAP 0x020000 1851 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 1852 1853 #define I915_OVERLAY_FLAGS_MASK 0xff000000 1854 #define I915_OVERLAY_ENABLE 0x01000000 1855 1856 struct drm_intel_overlay_put_image { 1857 /* various flags and src format description */ 1858 __u32 flags; 1859 /* source picture description */ 1860 __u32 bo_handle; 1861 /* stride values and offsets are in bytes, buffer relative */ 1862 __u16 stride_Y; /* stride for packed formats */ 1863 __u16 stride_UV; 1864 __u32 offset_Y; /* offset for packet formats */ 1865 __u32 offset_U; 1866 __u32 offset_V; 1867 /* in pixels */ 1868 __u16 src_width; 1869 __u16 src_height; 1870 /* to compensate the scaling factors for partially covered surfaces */ 1871 __u16 src_scan_width; 1872 __u16 src_scan_height; 1873 /* output crtc description */ 1874 __u32 crtc_id; 1875 __u16 dst_x; 1876 __u16 dst_y; 1877 __u16 dst_width; 1878 __u16 dst_height; 1879 }; 1880 1881 /* flags */ 1882 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 1883 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 1884 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) 1885 struct drm_intel_overlay_attrs { 1886 __u32 flags; 1887 __u32 color_key; 1888 __s32 brightness; 1889 __u32 contrast; 1890 __u32 saturation; 1891 __u32 gamma0; 1892 __u32 gamma1; 1893 __u32 gamma2; 1894 __u32 gamma3; 1895 __u32 gamma4; 1896 __u32 gamma5; 1897 }; 1898 1899 /* 1900 * Intel sprite handling 1901 * 1902 * Color keying works with a min/mask/max tuple. Both source and destination 1903 * color keying is allowed. 1904 * 1905 * Source keying: 1906 * Sprite pixels within the min & max values, masked against the color channels 1907 * specified in the mask field, will be transparent. All other pixels will 1908 * be displayed on top of the primary plane. For RGB surfaces, only the min 1909 * and mask fields will be used; ranged compares are not allowed. 1910 * 1911 * Destination keying: 1912 * Primary plane pixels that match the min value, masked against the color 1913 * channels specified in the mask field, will be replaced by corresponding 1914 * pixels from the sprite plane. 1915 * 1916 * Note that source & destination keying are exclusive; only one can be 1917 * active on a given plane. 1918 */ 1919 1920 #define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set 1921 * flags==0 to disable colorkeying. 1922 */ 1923 #define I915_SET_COLORKEY_DESTINATION (1<<1) 1924 #define I915_SET_COLORKEY_SOURCE (1<<2) 1925 struct drm_intel_sprite_colorkey { 1926 __u32 plane_id; 1927 __u32 min_value; 1928 __u32 channel_mask; 1929 __u32 max_value; 1930 __u32 flags; 1931 }; 1932 1933 struct drm_i915_gem_wait { 1934 /** Handle of BO we shall wait on */ 1935 __u32 bo_handle; 1936 __u32 flags; 1937 /** Number of nanoseconds to wait, Returns time remaining. */ 1938 __s64 timeout_ns; 1939 }; 1940 1941 struct drm_i915_gem_context_create { 1942 __u32 ctx_id; /* output: id of new context*/ 1943 __u32 pad; 1944 }; 1945 1946 /** 1947 * struct drm_i915_gem_context_create_ext - Structure for creating contexts. 1948 */ 1949 struct drm_i915_gem_context_create_ext { 1950 /** @ctx_id: Id of the created context (output) */ 1951 __u32 ctx_id; 1952 1953 /** 1954 * @flags: Supported flags are: 1955 * 1956 * I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS: 1957 * 1958 * Extensions may be appended to this structure and driver must check 1959 * for those. See @extensions. 1960 * 1961 * I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE 1962 * 1963 * Created context will have single timeline. 1964 */ 1965 __u32 flags; 1966 #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0) 1967 #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1) 1968 #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \ 1969 (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)) 1970 1971 /** 1972 * @extensions: Zero-terminated chain of extensions. 1973 * 1974 * I915_CONTEXT_CREATE_EXT_SETPARAM: 1975 * Context parameter to set or query during context creation. 1976 * See struct drm_i915_gem_context_create_ext_setparam. 1977 * 1978 * I915_CONTEXT_CREATE_EXT_CLONE: 1979 * This extension has been removed. On the off chance someone somewhere 1980 * has attempted to use it, never re-use this extension number. 1981 */ 1982 __u64 extensions; 1983 #define I915_CONTEXT_CREATE_EXT_SETPARAM 0 1984 #define I915_CONTEXT_CREATE_EXT_CLONE 1 1985 }; 1986 1987 /** 1988 * struct drm_i915_gem_context_param - Context parameter to set or query. 1989 */ 1990 struct drm_i915_gem_context_param { 1991 /** @ctx_id: Context id */ 1992 __u32 ctx_id; 1993 1994 /** @size: Size of the parameter @value */ 1995 __u32 size; 1996 1997 /** @param: Parameter to set or query */ 1998 __u64 param; 1999 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 2000 /* I915_CONTEXT_PARAM_NO_ZEROMAP has been removed. On the off chance 2001 * someone somewhere has attempted to use it, never re-use this context 2002 * param number. 2003 */ 2004 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 2005 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 2006 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 2007 #define I915_CONTEXT_PARAM_BANNABLE 0x5 2008 #define I915_CONTEXT_PARAM_PRIORITY 0x6 2009 #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ 2010 #define I915_CONTEXT_DEFAULT_PRIORITY 0 2011 #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ 2012 /* 2013 * When using the following param, value should be a pointer to 2014 * drm_i915_gem_context_param_sseu. 2015 */ 2016 #define I915_CONTEXT_PARAM_SSEU 0x7 2017 2018 /* 2019 * Not all clients may want to attempt automatic recover of a context after 2020 * a hang (for example, some clients may only submit very small incremental 2021 * batches relying on known logical state of previous batches which will never 2022 * recover correctly and each attempt will hang), and so would prefer that 2023 * the context is forever banned instead. 2024 * 2025 * If set to false (0), after a reset, subsequent (and in flight) rendering 2026 * from this context is discarded, and the client will need to create a new 2027 * context to use instead. 2028 * 2029 * If set to true (1), the kernel will automatically attempt to recover the 2030 * context by skipping the hanging batch and executing the next batch starting 2031 * from the default context state (discarding the incomplete logical context 2032 * state lost due to the reset). 2033 * 2034 * On creation, all new contexts are marked as recoverable. 2035 */ 2036 #define I915_CONTEXT_PARAM_RECOVERABLE 0x8 2037 2038 /* 2039 * The id of the associated virtual memory address space (ppGTT) of 2040 * this context. Can be retrieved and passed to another context 2041 * (on the same fd) for both to use the same ppGTT and so share 2042 * address layouts, and avoid reloading the page tables on context 2043 * switches between themselves. 2044 * 2045 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY. 2046 */ 2047 #define I915_CONTEXT_PARAM_VM 0x9 2048 2049 /* 2050 * I915_CONTEXT_PARAM_ENGINES: 2051 * 2052 * Bind this context to operate on this subset of available engines. Henceforth, 2053 * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as 2054 * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0] 2055 * and upwards. Slots 0...N are filled in using the specified (class, instance). 2056 * Use 2057 * engine_class: I915_ENGINE_CLASS_INVALID, 2058 * engine_instance: I915_ENGINE_CLASS_INVALID_NONE 2059 * to specify a gap in the array that can be filled in later, e.g. by a 2060 * virtual engine used for load balancing. 2061 * 2062 * Setting the number of engines bound to the context to 0, by passing a zero 2063 * sized argument, will revert back to default settings. 2064 * 2065 * See struct i915_context_param_engines. 2066 * 2067 * Extensions: 2068 * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE) 2069 * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND) 2070 * i915_context_engines_parallel_submit (I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT) 2071 */ 2072 #define I915_CONTEXT_PARAM_ENGINES 0xa 2073 2074 /* 2075 * I915_CONTEXT_PARAM_PERSISTENCE: 2076 * 2077 * Allow the context and active rendering to survive the process until 2078 * completion. Persistence allows fire-and-forget clients to queue up a 2079 * bunch of work, hand the output over to a display server and then quit. 2080 * If the context is marked as not persistent, upon closing (either via 2081 * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure 2082 * or process termination), the context and any outstanding requests will be 2083 * cancelled (and exported fences for cancelled requests marked as -EIO). 2084 * 2085 * By default, new contexts allow persistence. 2086 */ 2087 #define I915_CONTEXT_PARAM_PERSISTENCE 0xb 2088 2089 /* This API has been removed. On the off chance someone somewhere has 2090 * attempted to use it, never re-use this context param number. 2091 */ 2092 #define I915_CONTEXT_PARAM_RINGSIZE 0xc 2093 2094 /* 2095 * I915_CONTEXT_PARAM_PROTECTED_CONTENT: 2096 * 2097 * Mark that the context makes use of protected content, which will result 2098 * in the context being invalidated when the protected content session is. 2099 * Given that the protected content session is killed on suspend, the device 2100 * is kept awake for the lifetime of a protected context, so the user should 2101 * make sure to dispose of them once done. 2102 * This flag can only be set at context creation time and, when set to true, 2103 * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE 2104 * to false. This flag can't be set to true in conjunction with setting the 2105 * I915_CONTEXT_PARAM_BANNABLE flag to false. Creation example: 2106 * 2107 * .. code-block:: C 2108 * 2109 * struct drm_i915_gem_context_create_ext_setparam p_protected = { 2110 * .base = { 2111 * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, 2112 * }, 2113 * .param = { 2114 * .param = I915_CONTEXT_PARAM_PROTECTED_CONTENT, 2115 * .value = 1, 2116 * } 2117 * }; 2118 * struct drm_i915_gem_context_create_ext_setparam p_norecover = { 2119 * .base = { 2120 * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, 2121 * .next_extension = to_user_pointer(&p_protected), 2122 * }, 2123 * .param = { 2124 * .param = I915_CONTEXT_PARAM_RECOVERABLE, 2125 * .value = 0, 2126 * } 2127 * }; 2128 * struct drm_i915_gem_context_create_ext create = { 2129 * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, 2130 * .extensions = to_user_pointer(&p_norecover); 2131 * }; 2132 * 2133 * ctx_id = gem_context_create_ext(drm_fd, &create); 2134 * 2135 * In addition to the normal failure cases, setting this flag during context 2136 * creation can result in the following errors: 2137 * 2138 * -ENODEV: feature not available 2139 * -EPERM: trying to mark a recoverable or not bannable context as protected 2140 * -ENXIO: A dependency such as a component driver or firmware is not yet 2141 * loaded so user space may need to attempt again. Depending on the 2142 * device, this error may be reported if protected context creation is 2143 * attempted very early after kernel start because the internal timeout 2144 * waiting for such dependencies is not guaranteed to be larger than 2145 * required (numbers differ depending on system and kernel config): 2146 * - ADL/RPL: dependencies may take up to 3 seconds from kernel start 2147 * while context creation internal timeout is 250 milisecs 2148 * - MTL: dependencies may take up to 8 seconds from kernel start 2149 * while context creation internal timeout is 250 milisecs 2150 * NOTE: such dependencies happen once, so a subsequent call to create a 2151 * protected context after a prior successful call will not experience 2152 * such timeouts and will not return -ENXIO (unless the driver is reloaded, 2153 * or, depending on the device, resumes from a suspended state). 2154 * -EIO: The firmware did not succeed in creating the protected context. 2155 */ 2156 #define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd 2157 2158 /* 2159 * I915_CONTEXT_PARAM_LOW_LATENCY: 2160 * 2161 * Mark this context as a low latency workload which requires aggressive GT 2162 * frequency scaling. Use I915_PARAM_HAS_CONTEXT_FREQ_HINT to check if the kernel 2163 * supports this per context flag. 2164 */ 2165 #define I915_CONTEXT_PARAM_LOW_LATENCY 0xe 2166 /* Must be kept compact -- no holes and well documented */ 2167 2168 /** @value: Context parameter value to be set or queried */ 2169 __u64 value; 2170 }; 2171 2172 /* 2173 * Context SSEU programming 2174 * 2175 * It may be necessary for either functional or performance reason to configure 2176 * a context to run with a reduced number of SSEU (where SSEU stands for Slice/ 2177 * Sub-slice/EU). 2178 * 2179 * This is done by configuring SSEU configuration using the below 2180 * @struct drm_i915_gem_context_param_sseu for every supported engine which 2181 * userspace intends to use. 2182 * 2183 * Not all GPUs or engines support this functionality in which case an error 2184 * code -ENODEV will be returned. 2185 * 2186 * Also, flexibility of possible SSEU configuration permutations varies between 2187 * GPU generations and software imposed limitations. Requesting such a 2188 * combination will return an error code of -EINVAL. 2189 * 2190 * NOTE: When perf/OA is active the context's SSEU configuration is ignored in 2191 * favour of a single global setting. 2192 */ 2193 struct drm_i915_gem_context_param_sseu { 2194 /* 2195 * Engine class & instance to be configured or queried. 2196 */ 2197 struct i915_engine_class_instance engine; 2198 2199 /* 2200 * Unknown flags must be cleared to zero. 2201 */ 2202 __u32 flags; 2203 #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0) 2204 2205 /* 2206 * Mask of slices to enable for the context. Valid values are a subset 2207 * of the bitmask value returned for I915_PARAM_SLICE_MASK. 2208 */ 2209 __u64 slice_mask; 2210 2211 /* 2212 * Mask of subslices to enable for the context. Valid values are a 2213 * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK. 2214 */ 2215 __u64 subslice_mask; 2216 2217 /* 2218 * Minimum/Maximum number of EUs to enable per subslice for the 2219 * context. min_eus_per_subslice must be inferior or equal to 2220 * max_eus_per_subslice. 2221 */ 2222 __u16 min_eus_per_subslice; 2223 __u16 max_eus_per_subslice; 2224 2225 /* 2226 * Unused for now. Must be cleared to zero. 2227 */ 2228 __u32 rsvd; 2229 }; 2230 2231 /** 2232 * DOC: Virtual Engine uAPI 2233 * 2234 * Virtual engine is a concept where userspace is able to configure a set of 2235 * physical engines, submit a batch buffer, and let the driver execute it on any 2236 * engine from the set as it sees fit. 2237 * 2238 * This is primarily useful on parts which have multiple instances of a same 2239 * class engine, like for example GT3+ Skylake parts with their two VCS engines. 2240 * 2241 * For instance userspace can enumerate all engines of a certain class using the 2242 * previously described `Engine Discovery uAPI`_. After that userspace can 2243 * create a GEM context with a placeholder slot for the virtual engine (using 2244 * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class 2245 * and instance respectively) and finally using the 2246 * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in 2247 * the same reserved slot. 2248 * 2249 * Example of creating a virtual engine and submitting a batch buffer to it: 2250 * 2251 * .. code-block:: C 2252 * 2253 * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { 2254 * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, 2255 * .engine_index = 0, // Place this virtual engine into engine map slot 0 2256 * .num_siblings = 2, 2257 * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, 2258 * { I915_ENGINE_CLASS_VIDEO, 1 }, }, 2259 * }; 2260 * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { 2261 * .engines = { { I915_ENGINE_CLASS_INVALID, 2262 * I915_ENGINE_CLASS_INVALID_NONE } }, 2263 * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension 2264 * }; 2265 * struct drm_i915_gem_context_create_ext_setparam p_engines = { 2266 * .base = { 2267 * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, 2268 * }, 2269 * .param = { 2270 * .param = I915_CONTEXT_PARAM_ENGINES, 2271 * .value = to_user_pointer(&engines), 2272 * .size = sizeof(engines), 2273 * }, 2274 * }; 2275 * struct drm_i915_gem_context_create_ext create = { 2276 * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, 2277 * .extensions = to_user_pointer(&p_engines); 2278 * }; 2279 * 2280 * ctx_id = gem_context_create_ext(drm_fd, &create); 2281 * 2282 * // Now we have created a GEM context with its engine map containing a 2283 * // single virtual engine. Submissions to this slot can go either to 2284 * // vcs0 or vcs1, depending on the load balancing algorithm used inside 2285 * // the driver. The load balancing is dynamic from one batch buffer to 2286 * // another and transparent to userspace. 2287 * 2288 * ... 2289 * execbuf.rsvd1 = ctx_id; 2290 * execbuf.flags = 0; // Submits to index 0 which is the virtual engine 2291 * gem_execbuf(drm_fd, &execbuf); 2292 */ 2293 2294 /* 2295 * i915_context_engines_load_balance: 2296 * 2297 * Enable load balancing across this set of engines. 2298 * 2299 * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when 2300 * used will proxy the execbuffer request onto one of the set of engines 2301 * in such a way as to distribute the load evenly across the set. 2302 * 2303 * The set of engines must be compatible (e.g. the same HW class) as they 2304 * will share the same logical GPU context and ring. 2305 * 2306 * To intermix rendering with the virtual engine and direct rendering onto 2307 * the backing engines (bypassing the load balancing proxy), the context must 2308 * be defined to use a single timeline for all engines. 2309 */ 2310 struct i915_context_engines_load_balance { 2311 struct i915_user_extension base; 2312 2313 __u16 engine_index; 2314 __u16 num_siblings; 2315 __u32 flags; /* all undefined flags must be zero */ 2316 2317 __u64 mbz64; /* reserved for future use; must be zero */ 2318 2319 struct i915_engine_class_instance engines[]; 2320 } __attribute__((packed)); 2321 2322 #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \ 2323 struct i915_user_extension base; \ 2324 __u16 engine_index; \ 2325 __u16 num_siblings; \ 2326 __u32 flags; \ 2327 __u64 mbz64; \ 2328 struct i915_engine_class_instance engines[N__]; \ 2329 } __attribute__((packed)) name__ 2330 2331 /* 2332 * i915_context_engines_bond: 2333 * 2334 * Constructed bonded pairs for execution within a virtual engine. 2335 * 2336 * All engines are equal, but some are more equal than others. Given 2337 * the distribution of resources in the HW, it may be preferable to run 2338 * a request on a given subset of engines in parallel to a request on a 2339 * specific engine. We enable this selection of engines within a virtual 2340 * engine by specifying bonding pairs, for any given master engine we will 2341 * only execute on one of the corresponding siblings within the virtual engine. 2342 * 2343 * To execute a request in parallel on the master engine and a sibling requires 2344 * coordination with a I915_EXEC_FENCE_SUBMIT. 2345 */ 2346 struct i915_context_engines_bond { 2347 struct i915_user_extension base; 2348 2349 struct i915_engine_class_instance master; 2350 2351 __u16 virtual_index; /* index of virtual engine in ctx->engines[] */ 2352 __u16 num_bonds; 2353 2354 __u64 flags; /* all undefined flags must be zero */ 2355 __u64 mbz64[4]; /* reserved for future use; must be zero */ 2356 2357 struct i915_engine_class_instance engines[]; 2358 } __attribute__((packed)); 2359 2360 #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \ 2361 struct i915_user_extension base; \ 2362 struct i915_engine_class_instance master; \ 2363 __u16 virtual_index; \ 2364 __u16 num_bonds; \ 2365 __u64 flags; \ 2366 __u64 mbz64[4]; \ 2367 struct i915_engine_class_instance engines[N__]; \ 2368 } __attribute__((packed)) name__ 2369 2370 /** 2371 * struct i915_context_engines_parallel_submit - Configure engine for 2372 * parallel submission. 2373 * 2374 * Setup a slot in the context engine map to allow multiple BBs to be submitted 2375 * in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU 2376 * in parallel. Multiple hardware contexts are created internally in the i915 to 2377 * run these BBs. Once a slot is configured for N BBs only N BBs can be 2378 * submitted in each execbuf IOCTL and this is implicit behavior e.g. The user 2379 * doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how 2380 * many BBs there are based on the slot's configuration. The N BBs are the last 2381 * N buffer objects or first N if I915_EXEC_BATCH_FIRST is set. 2382 * 2383 * The default placement behavior is to create implicit bonds between each 2384 * context if each context maps to more than 1 physical engine (e.g. context is 2385 * a virtual engine). Also we only allow contexts of same engine class and these 2386 * contexts must be in logically contiguous order. Examples of the placement 2387 * behavior are described below. Lastly, the default is to not allow BBs to be 2388 * preempted mid-batch. Rather insert coordinated preemption points on all 2389 * hardware contexts between each set of BBs. Flags could be added in the future 2390 * to change both of these default behaviors. 2391 * 2392 * Returns -EINVAL if hardware context placement configuration is invalid or if 2393 * the placement configuration isn't supported on the platform / submission 2394 * interface. 2395 * Returns -ENODEV if extension isn't supported on the platform / submission 2396 * interface. 2397 * 2398 * .. code-block:: none 2399 * 2400 * Examples syntax: 2401 * CS[X] = generic engine of same class, logical instance X 2402 * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE 2403 * 2404 * Example 1 pseudo code: 2405 * set_engines(INVALID) 2406 * set_parallel(engine_index=0, width=2, num_siblings=1, 2407 * engines=CS[0],CS[1]) 2408 * 2409 * Results in the following valid placement: 2410 * CS[0], CS[1] 2411 * 2412 * Example 2 pseudo code: 2413 * set_engines(INVALID) 2414 * set_parallel(engine_index=0, width=2, num_siblings=2, 2415 * engines=CS[0],CS[2],CS[1],CS[3]) 2416 * 2417 * Results in the following valid placements: 2418 * CS[0], CS[1] 2419 * CS[2], CS[3] 2420 * 2421 * This can be thought of as two virtual engines, each containing two 2422 * engines thereby making a 2D array. However, there are bonds tying the 2423 * entries together and placing restrictions on how they can be scheduled. 2424 * Specifically, the scheduler can choose only vertical columns from the 2D 2425 * array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the 2426 * scheduler wants to submit to CS[0], it must also choose CS[1] and vice 2427 * versa. Same for CS[2] requires also using CS[3]. 2428 * VE[0] = CS[0], CS[2] 2429 * VE[1] = CS[1], CS[3] 2430 * 2431 * Example 3 pseudo code: 2432 * set_engines(INVALID) 2433 * set_parallel(engine_index=0, width=2, num_siblings=2, 2434 * engines=CS[0],CS[1],CS[1],CS[3]) 2435 * 2436 * Results in the following valid and invalid placements: 2437 * CS[0], CS[1] 2438 * CS[1], CS[3] - Not logically contiguous, return -EINVAL 2439 */ 2440 struct i915_context_engines_parallel_submit { 2441 /** 2442 * @base: base user extension. 2443 */ 2444 struct i915_user_extension base; 2445 2446 /** 2447 * @engine_index: slot for parallel engine 2448 */ 2449 __u16 engine_index; 2450 2451 /** 2452 * @width: number of contexts per parallel engine or in other words the 2453 * number of batches in each submission 2454 */ 2455 __u16 width; 2456 2457 /** 2458 * @num_siblings: number of siblings per context or in other words the 2459 * number of possible placements for each submission 2460 */ 2461 __u16 num_siblings; 2462 2463 /** 2464 * @mbz16: reserved for future use; must be zero 2465 */ 2466 __u16 mbz16; 2467 2468 /** 2469 * @flags: all undefined flags must be zero, currently not defined flags 2470 */ 2471 __u64 flags; 2472 2473 /** 2474 * @mbz64: reserved for future use; must be zero 2475 */ 2476 __u64 mbz64[3]; 2477 2478 /** 2479 * @engines: 2-d array of engine instances to configure parallel engine 2480 * 2481 * length = width (i) * num_siblings (j) 2482 * index = j + i * num_siblings 2483 */ 2484 struct i915_engine_class_instance engines[]; 2485 2486 } __packed; 2487 2488 #define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__, N__) struct { \ 2489 struct i915_user_extension base; \ 2490 __u16 engine_index; \ 2491 __u16 width; \ 2492 __u16 num_siblings; \ 2493 __u16 mbz16; \ 2494 __u64 flags; \ 2495 __u64 mbz64[3]; \ 2496 struct i915_engine_class_instance engines[N__]; \ 2497 } __attribute__((packed)) name__ 2498 2499 /** 2500 * DOC: Context Engine Map uAPI 2501 * 2502 * Context engine map is a new way of addressing engines when submitting batch- 2503 * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` 2504 * inside the flags field of `struct drm_i915_gem_execbuffer2`. 2505 * 2506 * To use it created GEM contexts need to be configured with a list of engines 2507 * the user is intending to submit to. This is accomplished using the 2508 * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct 2509 * i915_context_param_engines`. 2510 * 2511 * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the 2512 * configured map. 2513 * 2514 * Example of creating such context and submitting against it: 2515 * 2516 * .. code-block:: C 2517 * 2518 * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { 2519 * .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, 2520 * { I915_ENGINE_CLASS_COPY, 0 } } 2521 * }; 2522 * struct drm_i915_gem_context_create_ext_setparam p_engines = { 2523 * .base = { 2524 * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, 2525 * }, 2526 * .param = { 2527 * .param = I915_CONTEXT_PARAM_ENGINES, 2528 * .value = to_user_pointer(&engines), 2529 * .size = sizeof(engines), 2530 * }, 2531 * }; 2532 * struct drm_i915_gem_context_create_ext create = { 2533 * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, 2534 * .extensions = to_user_pointer(&p_engines); 2535 * }; 2536 * 2537 * ctx_id = gem_context_create_ext(drm_fd, &create); 2538 * 2539 * // We have now created a GEM context with two engines in the map: 2540 * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines 2541 * // will not be accessible from this context. 2542 * 2543 * ... 2544 * execbuf.rsvd1 = ctx_id; 2545 * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context 2546 * gem_execbuf(drm_fd, &execbuf); 2547 * 2548 * ... 2549 * execbuf.rsvd1 = ctx_id; 2550 * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context 2551 * gem_execbuf(drm_fd, &execbuf); 2552 */ 2553 2554 struct i915_context_param_engines { 2555 __u64 extensions; /* linked chain of extension blocks, 0 terminates */ 2556 #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ 2557 #define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */ 2558 #define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */ 2559 struct i915_engine_class_instance engines[]; 2560 } __attribute__((packed)); 2561 2562 #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \ 2563 __u64 extensions; \ 2564 struct i915_engine_class_instance engines[N__]; \ 2565 } __attribute__((packed)) name__ 2566 2567 /** 2568 * struct drm_i915_gem_context_create_ext_setparam - Context parameter 2569 * to set or query during context creation. 2570 */ 2571 struct drm_i915_gem_context_create_ext_setparam { 2572 /** @base: Extension link. See struct i915_user_extension. */ 2573 struct i915_user_extension base; 2574 2575 /** 2576 * @param: Context parameter to set or query. 2577 * See struct drm_i915_gem_context_param. 2578 */ 2579 struct drm_i915_gem_context_param param; 2580 }; 2581 2582 struct drm_i915_gem_context_destroy { 2583 __u32 ctx_id; 2584 __u32 pad; 2585 }; 2586 2587 /** 2588 * struct drm_i915_gem_vm_control - Structure to create or destroy VM. 2589 * 2590 * DRM_I915_GEM_VM_CREATE - 2591 * 2592 * Create a new virtual memory address space (ppGTT) for use within a context 2593 * on the same file. Extensions can be provided to configure exactly how the 2594 * address space is setup upon creation. 2595 * 2596 * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is 2597 * returned in the outparam @id. 2598 * 2599 * An extension chain maybe provided, starting with @extensions, and terminated 2600 * by the @next_extension being 0. Currently, no extensions are defined. 2601 * 2602 * DRM_I915_GEM_VM_DESTROY - 2603 * 2604 * Destroys a previously created VM id, specified in @vm_id. 2605 * 2606 * No extensions or flags are allowed currently, and so must be zero. 2607 */ 2608 struct drm_i915_gem_vm_control { 2609 /** @extensions: Zero-terminated chain of extensions. */ 2610 __u64 extensions; 2611 2612 /** @flags: reserved for future usage, currently MBZ */ 2613 __u32 flags; 2614 2615 /** @vm_id: Id of the VM created or to be destroyed */ 2616 __u32 vm_id; 2617 }; 2618 2619 struct drm_i915_reg_read { 2620 /* 2621 * Register offset. 2622 * For 64bit wide registers where the upper 32bits don't immediately 2623 * follow the lower 32bits, the offset of the lower 32bits must 2624 * be specified 2625 */ 2626 __u64 offset; 2627 #define I915_REG_READ_8B_WA (1ul << 0) 2628 2629 __u64 val; /* Return value */ 2630 }; 2631 2632 /* Known registers: 2633 * 2634 * Render engine timestamp - 0x2358 + 64bit - gen7+ 2635 * - Note this register returns an invalid value if using the default 2636 * single instruction 8byte read, in order to workaround that pass 2637 * flag I915_REG_READ_8B_WA in offset field. 2638 * 2639 */ 2640 2641 struct drm_i915_reset_stats { 2642 __u32 ctx_id; 2643 __u32 flags; 2644 2645 /* All resets since boot/module reload, for all contexts */ 2646 __u32 reset_count; 2647 2648 /* Number of batches lost when active in GPU, for this context */ 2649 __u32 batch_active; 2650 2651 /* Number of batches lost pending for execution, for this context */ 2652 __u32 batch_pending; 2653 2654 __u32 pad; 2655 }; 2656 2657 /** 2658 * struct drm_i915_gem_userptr - Create GEM object from user allocated memory. 2659 * 2660 * Userptr objects have several restrictions on what ioctls can be used with the 2661 * object handle. 2662 */ 2663 struct drm_i915_gem_userptr { 2664 /** 2665 * @user_ptr: The pointer to the allocated memory. 2666 * 2667 * Needs to be aligned to PAGE_SIZE. 2668 */ 2669 __u64 user_ptr; 2670 2671 /** 2672 * @user_size: 2673 * 2674 * The size in bytes for the allocated memory. This will also become the 2675 * object size. 2676 * 2677 * Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE, 2678 * or larger. 2679 */ 2680 __u64 user_size; 2681 2682 /** 2683 * @flags: 2684 * 2685 * Supported flags: 2686 * 2687 * I915_USERPTR_READ_ONLY: 2688 * 2689 * Mark the object as readonly, this also means GPU access can only be 2690 * readonly. This is only supported on HW which supports readonly access 2691 * through the GTT. If the HW can't support readonly access, an error is 2692 * returned. 2693 * 2694 * I915_USERPTR_PROBE: 2695 * 2696 * Probe the provided @user_ptr range and validate that the @user_ptr is 2697 * indeed pointing to normal memory and that the range is also valid. 2698 * For example if some garbage address is given to the kernel, then this 2699 * should complain. 2700 * 2701 * Returns -EFAULT if the probe failed. 2702 * 2703 * Note that this doesn't populate the backing pages, and also doesn't 2704 * guarantee that the object will remain valid when the object is 2705 * eventually used. 2706 * 2707 * The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE 2708 * returns a non-zero value. 2709 * 2710 * I915_USERPTR_UNSYNCHRONIZED: 2711 * 2712 * NOT USED. Setting this flag will result in an error. 2713 */ 2714 __u32 flags; 2715 #define I915_USERPTR_READ_ONLY 0x1 2716 #define I915_USERPTR_PROBE 0x2 2717 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 2718 /** 2719 * @handle: Returned handle for the object. 2720 * 2721 * Object handles are nonzero. 2722 */ 2723 __u32 handle; 2724 }; 2725 2726 enum drm_i915_oa_format { 2727 I915_OA_FORMAT_A13 = 1, /* HSW only */ 2728 I915_OA_FORMAT_A29, /* HSW only */ 2729 I915_OA_FORMAT_A13_B8_C8, /* HSW only */ 2730 I915_OA_FORMAT_B4_C8, /* HSW only */ 2731 I915_OA_FORMAT_A45_B8_C8, /* HSW only */ 2732 I915_OA_FORMAT_B4_C8_A16, /* HSW only */ 2733 I915_OA_FORMAT_C4_B8, /* HSW+ */ 2734 2735 /* Gen8+ */ 2736 I915_OA_FORMAT_A12, 2737 I915_OA_FORMAT_A12_B8_C8, 2738 I915_OA_FORMAT_A32u40_A4u32_B8_C8, 2739 2740 /* DG2 */ 2741 I915_OAR_FORMAT_A32u40_A4u32_B8_C8, 2742 I915_OA_FORMAT_A24u40_A14u32_B8_C8, 2743 2744 /* MTL OAM */ 2745 I915_OAM_FORMAT_MPEC8u64_B8_C8, 2746 I915_OAM_FORMAT_MPEC8u32_B8_C8, 2747 2748 I915_OA_FORMAT_MAX /* non-ABI */ 2749 }; 2750 2751 enum drm_i915_perf_property_id { 2752 /** 2753 * Open the stream for a specific context handle (as used with 2754 * execbuffer2). A stream opened for a specific context this way 2755 * won't typically require root privileges. 2756 * 2757 * This property is available in perf revision 1. 2758 */ 2759 DRM_I915_PERF_PROP_CTX_HANDLE = 1, 2760 2761 /** 2762 * A value of 1 requests the inclusion of raw OA unit reports as 2763 * part of stream samples. 2764 * 2765 * This property is available in perf revision 1. 2766 */ 2767 DRM_I915_PERF_PROP_SAMPLE_OA, 2768 2769 /** 2770 * The value specifies which set of OA unit metrics should be 2771 * configured, defining the contents of any OA unit reports. 2772 * 2773 * This property is available in perf revision 1. 2774 */ 2775 DRM_I915_PERF_PROP_OA_METRICS_SET, 2776 2777 /** 2778 * The value specifies the size and layout of OA unit reports. 2779 * 2780 * This property is available in perf revision 1. 2781 */ 2782 DRM_I915_PERF_PROP_OA_FORMAT, 2783 2784 /** 2785 * Specifying this property implicitly requests periodic OA unit 2786 * sampling and (at least on Haswell) the sampling frequency is derived 2787 * from this exponent as follows: 2788 * 2789 * 80ns * 2^(period_exponent + 1) 2790 * 2791 * This property is available in perf revision 1. 2792 */ 2793 DRM_I915_PERF_PROP_OA_EXPONENT, 2794 2795 /** 2796 * Specifying this property is only valid when specify a context to 2797 * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property 2798 * will hold preemption of the particular context we want to gather 2799 * performance data about. The execbuf2 submissions must include a 2800 * drm_i915_gem_execbuffer_ext_perf parameter for this to apply. 2801 * 2802 * This property is available in perf revision 3. 2803 */ 2804 DRM_I915_PERF_PROP_HOLD_PREEMPTION, 2805 2806 /** 2807 * Specifying this pins all contexts to the specified SSEU power 2808 * configuration for the duration of the recording. 2809 * 2810 * This parameter's value is a pointer to a struct 2811 * drm_i915_gem_context_param_sseu. 2812 * 2813 * This property is available in perf revision 4. 2814 */ 2815 DRM_I915_PERF_PROP_GLOBAL_SSEU, 2816 2817 /** 2818 * This optional parameter specifies the timer interval in nanoseconds 2819 * at which the i915 driver will check the OA buffer for available data. 2820 * Minimum allowed value is 100 microseconds. A default value is used by 2821 * the driver if this parameter is not specified. Note that larger timer 2822 * values will reduce cpu consumption during OA perf captures. However, 2823 * excessively large values would potentially result in OA buffer 2824 * overwrites as captures reach end of the OA buffer. 2825 * 2826 * This property is available in perf revision 5. 2827 */ 2828 DRM_I915_PERF_PROP_POLL_OA_PERIOD, 2829 2830 /** 2831 * Multiple engines may be mapped to the same OA unit. The OA unit is 2832 * identified by class:instance of any engine mapped to it. 2833 * 2834 * This parameter specifies the engine class and must be passed along 2835 * with DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE. 2836 * 2837 * This property is available in perf revision 6. 2838 */ 2839 DRM_I915_PERF_PROP_OA_ENGINE_CLASS, 2840 2841 /** 2842 * This parameter specifies the engine instance and must be passed along 2843 * with DRM_I915_PERF_PROP_OA_ENGINE_CLASS. 2844 * 2845 * This property is available in perf revision 6. 2846 */ 2847 DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE, 2848 2849 DRM_I915_PERF_PROP_MAX /* non-ABI */ 2850 }; 2851 2852 struct drm_i915_perf_open_param { 2853 __u32 flags; 2854 #define I915_PERF_FLAG_FD_CLOEXEC (1<<0) 2855 #define I915_PERF_FLAG_FD_NONBLOCK (1<<1) 2856 #define I915_PERF_FLAG_DISABLED (1<<2) 2857 2858 /** The number of u64 (id, value) pairs */ 2859 __u32 num_properties; 2860 2861 /** 2862 * Pointer to array of u64 (id, value) pairs configuring the stream 2863 * to open. 2864 */ 2865 __u64 properties_ptr; 2866 }; 2867 2868 /* 2869 * Enable data capture for a stream that was either opened in a disabled state 2870 * via I915_PERF_FLAG_DISABLED or was later disabled via 2871 * I915_PERF_IOCTL_DISABLE. 2872 * 2873 * It is intended to be cheaper to disable and enable a stream than it may be 2874 * to close and re-open a stream with the same configuration. 2875 * 2876 * It's undefined whether any pending data for the stream will be lost. 2877 * 2878 * This ioctl is available in perf revision 1. 2879 */ 2880 #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 2881 2882 /* 2883 * Disable data capture for a stream. 2884 * 2885 * It is an error to try and read a stream that is disabled. 2886 * 2887 * This ioctl is available in perf revision 1. 2888 */ 2889 #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 2890 2891 /* 2892 * Change metrics_set captured by a stream. 2893 * 2894 * If the stream is bound to a specific context, the configuration change 2895 * will performed inline with that context such that it takes effect before 2896 * the next execbuf submission. 2897 * 2898 * Returns the previously bound metrics set id, or a negative error code. 2899 * 2900 * This ioctl is available in perf revision 2. 2901 */ 2902 #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2) 2903 2904 /* 2905 * Common to all i915 perf records 2906 */ 2907 struct drm_i915_perf_record_header { 2908 __u32 type; 2909 __u16 pad; 2910 __u16 size; 2911 }; 2912 2913 enum drm_i915_perf_record_type { 2914 2915 /** 2916 * Samples are the work horse record type whose contents are extensible 2917 * and defined when opening an i915 perf stream based on the given 2918 * properties. 2919 * 2920 * Boolean properties following the naming convention 2921 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in 2922 * every sample. 2923 * 2924 * The order of these sample properties given by userspace has no 2925 * affect on the ordering of data within a sample. The order is 2926 * documented here. 2927 * 2928 * struct { 2929 * struct drm_i915_perf_record_header header; 2930 * 2931 * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA 2932 * }; 2933 */ 2934 DRM_I915_PERF_RECORD_SAMPLE = 1, 2935 2936 /* 2937 * Indicates that one or more OA reports were not written by the 2938 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT 2939 * command collides with periodic sampling - which would be more likely 2940 * at higher sampling frequencies. 2941 */ 2942 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 2943 2944 /** 2945 * An error occurred that resulted in all pending OA reports being lost. 2946 */ 2947 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 2948 2949 DRM_I915_PERF_RECORD_MAX /* non-ABI */ 2950 }; 2951 2952 /** 2953 * struct drm_i915_perf_oa_config 2954 * 2955 * Structure to upload perf dynamic configuration into the kernel. 2956 */ 2957 struct drm_i915_perf_oa_config { 2958 /** 2959 * @uuid: 2960 * 2961 * String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" 2962 */ 2963 char uuid[36]; 2964 2965 /** 2966 * @n_mux_regs: 2967 * 2968 * Number of mux regs in &mux_regs_ptr. 2969 */ 2970 __u32 n_mux_regs; 2971 2972 /** 2973 * @n_boolean_regs: 2974 * 2975 * Number of boolean regs in &boolean_regs_ptr. 2976 */ 2977 __u32 n_boolean_regs; 2978 2979 /** 2980 * @n_flex_regs: 2981 * 2982 * Number of flex regs in &flex_regs_ptr. 2983 */ 2984 __u32 n_flex_regs; 2985 2986 /** 2987 * @mux_regs_ptr: 2988 * 2989 * Pointer to tuples of u32 values (register address, value) for mux 2990 * registers. Expected length of buffer is (2 * sizeof(u32) * 2991 * &n_mux_regs). 2992 */ 2993 __u64 mux_regs_ptr; 2994 2995 /** 2996 * @boolean_regs_ptr: 2997 * 2998 * Pointer to tuples of u32 values (register address, value) for mux 2999 * registers. Expected length of buffer is (2 * sizeof(u32) * 3000 * &n_boolean_regs). 3001 */ 3002 __u64 boolean_regs_ptr; 3003 3004 /** 3005 * @flex_regs_ptr: 3006 * 3007 * Pointer to tuples of u32 values (register address, value) for mux 3008 * registers. Expected length of buffer is (2 * sizeof(u32) * 3009 * &n_flex_regs). 3010 */ 3011 __u64 flex_regs_ptr; 3012 }; 3013 3014 /** 3015 * struct drm_i915_query_item - An individual query for the kernel to process. 3016 * 3017 * The behaviour is determined by the @query_id. Note that exactly what 3018 * @data_ptr is also depends on the specific @query_id. 3019 */ 3020 struct drm_i915_query_item { 3021 /** 3022 * @query_id: 3023 * 3024 * The id for this query. Currently accepted query IDs are: 3025 * - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info) 3026 * - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info) 3027 * - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config) 3028 * - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions) 3029 * - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`) 3030 * - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info) 3031 * - %DRM_I915_QUERY_GUC_SUBMISSION_VERSION (see struct drm_i915_query_guc_submission_version) 3032 */ 3033 __u64 query_id; 3034 #define DRM_I915_QUERY_TOPOLOGY_INFO 1 3035 #define DRM_I915_QUERY_ENGINE_INFO 2 3036 #define DRM_I915_QUERY_PERF_CONFIG 3 3037 #define DRM_I915_QUERY_MEMORY_REGIONS 4 3038 #define DRM_I915_QUERY_HWCONFIG_BLOB 5 3039 #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6 3040 #define DRM_I915_QUERY_GUC_SUBMISSION_VERSION 7 3041 /* Must be kept compact -- no holes and well documented */ 3042 3043 /** 3044 * @length: 3045 * 3046 * When set to zero by userspace, this is filled with the size of the 3047 * data to be written at the @data_ptr pointer. The kernel sets this 3048 * value to a negative value to signal an error on a particular query 3049 * item. 3050 */ 3051 __s32 length; 3052 3053 /** 3054 * @flags: 3055 * 3056 * When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0. 3057 * 3058 * When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the 3059 * following: 3060 * 3061 * - %DRM_I915_QUERY_PERF_CONFIG_LIST 3062 * - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 3063 * - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID 3064 * 3065 * When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain 3066 * a struct i915_engine_class_instance that references a render engine. 3067 */ 3068 __u32 flags; 3069 #define DRM_I915_QUERY_PERF_CONFIG_LIST 1 3070 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2 3071 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3 3072 3073 /** 3074 * @data_ptr: 3075 * 3076 * Data will be written at the location pointed by @data_ptr when the 3077 * value of @length matches the length of the data to be written by the 3078 * kernel. 3079 */ 3080 __u64 data_ptr; 3081 }; 3082 3083 /** 3084 * struct drm_i915_query - Supply an array of struct drm_i915_query_item for the 3085 * kernel to fill out. 3086 * 3087 * Note that this is generally a two step process for each struct 3088 * drm_i915_query_item in the array: 3089 * 3090 * 1. Call the DRM_IOCTL_I915_QUERY, giving it our array of struct 3091 * drm_i915_query_item, with &drm_i915_query_item.length set to zero. The 3092 * kernel will then fill in the size, in bytes, which tells userspace how 3093 * memory it needs to allocate for the blob(say for an array of properties). 3094 * 3095 * 2. Next we call DRM_IOCTL_I915_QUERY again, this time with the 3096 * &drm_i915_query_item.data_ptr equal to our newly allocated blob. Note that 3097 * the &drm_i915_query_item.length should still be the same as what the 3098 * kernel previously set. At this point the kernel can fill in the blob. 3099 * 3100 * Note that for some query items it can make sense for userspace to just pass 3101 * in a buffer/blob equal to or larger than the required size. In this case only 3102 * a single ioctl call is needed. For some smaller query items this can work 3103 * quite well. 3104 * 3105 */ 3106 struct drm_i915_query { 3107 /** @num_items: The number of elements in the @items_ptr array */ 3108 __u32 num_items; 3109 3110 /** 3111 * @flags: Unused for now. Must be cleared to zero. 3112 */ 3113 __u32 flags; 3114 3115 /** 3116 * @items_ptr: 3117 * 3118 * Pointer to an array of struct drm_i915_query_item. The number of 3119 * array elements is @num_items. 3120 */ 3121 __u64 items_ptr; 3122 }; 3123 3124 /** 3125 * struct drm_i915_query_topology_info 3126 * 3127 * Describes slice/subslice/EU information queried by 3128 * %DRM_I915_QUERY_TOPOLOGY_INFO 3129 */ 3130 struct drm_i915_query_topology_info { 3131 /** 3132 * @flags: 3133 * 3134 * Unused for now. Must be cleared to zero. 3135 */ 3136 __u16 flags; 3137 3138 /** 3139 * @max_slices: 3140 * 3141 * The number of bits used to express the slice mask. 3142 */ 3143 __u16 max_slices; 3144 3145 /** 3146 * @max_subslices: 3147 * 3148 * The number of bits used to express the subslice mask. 3149 */ 3150 __u16 max_subslices; 3151 3152 /** 3153 * @max_eus_per_subslice: 3154 * 3155 * The number of bits in the EU mask that correspond to a single 3156 * subslice's EUs. 3157 */ 3158 __u16 max_eus_per_subslice; 3159 3160 /** 3161 * @subslice_offset: 3162 * 3163 * Offset in data[] at which the subslice masks are stored. 3164 */ 3165 __u16 subslice_offset; 3166 3167 /** 3168 * @subslice_stride: 3169 * 3170 * Stride at which each of the subslice masks for each slice are 3171 * stored. 3172 */ 3173 __u16 subslice_stride; 3174 3175 /** 3176 * @eu_offset: 3177 * 3178 * Offset in data[] at which the EU masks are stored. 3179 */ 3180 __u16 eu_offset; 3181 3182 /** 3183 * @eu_stride: 3184 * 3185 * Stride at which each of the EU masks for each subslice are stored. 3186 */ 3187 __u16 eu_stride; 3188 3189 /** 3190 * @data: 3191 * 3192 * Contains 3 pieces of information : 3193 * 3194 * - The slice mask with one bit per slice telling whether a slice is 3195 * available. The availability of slice X can be queried with the 3196 * following formula : 3197 * 3198 * .. code:: c 3199 * 3200 * (data[X / 8] >> (X % 8)) & 1 3201 * 3202 * Starting with Xe_HP platforms, Intel hardware no longer has 3203 * traditional slices so i915 will always report a single slice 3204 * (hardcoded slicemask = 0x1) which contains all of the platform's 3205 * subslices. I.e., the mask here does not reflect any of the newer 3206 * hardware concepts such as "gslices" or "cslices" since userspace 3207 * is capable of inferring those from the subslice mask. 3208 * 3209 * - The subslice mask for each slice with one bit per subslice telling 3210 * whether a subslice is available. Starting with Gen12 we use the 3211 * term "subslice" to refer to what the hardware documentation 3212 * describes as a "dual-subslices." The availability of subslice Y 3213 * in slice X can be queried with the following formula : 3214 * 3215 * .. code:: c 3216 * 3217 * (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1 3218 * 3219 * - The EU mask for each subslice in each slice, with one bit per EU 3220 * telling whether an EU is available. The availability of EU Z in 3221 * subslice Y in slice X can be queried with the following formula : 3222 * 3223 * .. code:: c 3224 * 3225 * (data[eu_offset + 3226 * (X * max_subslices + Y) * eu_stride + 3227 * Z / 8 3228 * ] >> (Z % 8)) & 1 3229 */ 3230 __u8 data[]; 3231 }; 3232 3233 /** 3234 * DOC: Engine Discovery uAPI 3235 * 3236 * Engine discovery uAPI is a way of enumerating physical engines present in a 3237 * GPU associated with an open i915 DRM file descriptor. This supersedes the old 3238 * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like 3239 * `I915_PARAM_HAS_BLT`. 3240 * 3241 * The need for this interface came starting with Icelake and newer GPUs, which 3242 * started to establish a pattern of having multiple engines of a same class, 3243 * where not all instances were always completely functionally equivalent. 3244 * 3245 * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the 3246 * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id. 3247 * 3248 * Example for getting the list of engines: 3249 * 3250 * .. code-block:: C 3251 * 3252 * struct drm_i915_query_engine_info *info; 3253 * struct drm_i915_query_item item = { 3254 * .query_id = DRM_I915_QUERY_ENGINE_INFO; 3255 * }; 3256 * struct drm_i915_query query = { 3257 * .num_items = 1, 3258 * .items_ptr = (uintptr_t)&item, 3259 * }; 3260 * int err, i; 3261 * 3262 * // First query the size of the blob we need, this needs to be large 3263 * // enough to hold our array of engines. The kernel will fill out the 3264 * // item.length for us, which is the number of bytes we need. 3265 * // 3266 * // Alternatively a large buffer can be allocated straightaway enabling 3267 * // querying in one pass, in which case item.length should contain the 3268 * // length of the provided buffer. 3269 * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 3270 * if (err) ... 3271 * 3272 * info = calloc(1, item.length); 3273 * // Now that we allocated the required number of bytes, we call the ioctl 3274 * // again, this time with the data_ptr pointing to our newly allocated 3275 * // blob, which the kernel can then populate with info on all engines. 3276 * item.data_ptr = (uintptr_t)&info; 3277 * 3278 * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 3279 * if (err) ... 3280 * 3281 * // We can now access each engine in the array 3282 * for (i = 0; i < info->num_engines; i++) { 3283 * struct drm_i915_engine_info einfo = info->engines[i]; 3284 * u16 class = einfo.engine.class; 3285 * u16 instance = einfo.engine.instance; 3286 * .... 3287 * } 3288 * 3289 * free(info); 3290 * 3291 * Each of the enumerated engines, apart from being defined by its class and 3292 * instance (see `struct i915_engine_class_instance`), also can have flags and 3293 * capabilities defined as documented in i915_drm.h. 3294 * 3295 * For instance video engines which support HEVC encoding will have the 3296 * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set. 3297 * 3298 * Engine discovery only fully comes to its own when combined with the new way 3299 * of addressing engines when submitting batch buffers using contexts with 3300 * engine maps configured. 3301 */ 3302 3303 /** 3304 * struct drm_i915_engine_info 3305 * 3306 * Describes one engine and its capabilities as known to the driver. 3307 */ 3308 struct drm_i915_engine_info { 3309 /** @engine: Engine class and instance. */ 3310 struct i915_engine_class_instance engine; 3311 3312 /** @rsvd0: Reserved field. */ 3313 __u32 rsvd0; 3314 3315 /** @flags: Engine flags. */ 3316 __u64 flags; 3317 #define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0) 3318 3319 /** @capabilities: Capabilities of this engine. */ 3320 __u64 capabilities; 3321 #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) 3322 #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) 3323 3324 /** @logical_instance: Logical instance of engine */ 3325 __u16 logical_instance; 3326 3327 /** @rsvd1: Reserved fields. */ 3328 __u16 rsvd1[3]; 3329 /** @rsvd2: Reserved fields. */ 3330 __u64 rsvd2[3]; 3331 }; 3332 3333 /** 3334 * struct drm_i915_query_engine_info 3335 * 3336 * Engine info query enumerates all engines known to the driver by filling in 3337 * an array of struct drm_i915_engine_info structures. 3338 */ 3339 struct drm_i915_query_engine_info { 3340 /** @num_engines: Number of struct drm_i915_engine_info structs following. */ 3341 __u32 num_engines; 3342 3343 /** @rsvd: MBZ */ 3344 __u32 rsvd[3]; 3345 3346 /** @engines: Marker for drm_i915_engine_info structures. */ 3347 struct drm_i915_engine_info engines[]; 3348 }; 3349 3350 /** 3351 * struct drm_i915_query_perf_config 3352 * 3353 * Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and 3354 * %DRM_I915_QUERY_GEOMETRY_SUBSLICES. 3355 */ 3356 struct drm_i915_query_perf_config { 3357 union { 3358 /** 3359 * @n_configs: 3360 * 3361 * When &drm_i915_query_item.flags == 3362 * %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to 3363 * the number of configurations available. 3364 */ 3365 __u64 n_configs; 3366 3367 /** 3368 * @config: 3369 * 3370 * When &drm_i915_query_item.flags == 3371 * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the 3372 * value in this field as configuration identifier to decide 3373 * what data to write into config_ptr. 3374 */ 3375 __u64 config; 3376 3377 /** 3378 * @uuid: 3379 * 3380 * When &drm_i915_query_item.flags == 3381 * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the 3382 * value in this field as configuration identifier to decide 3383 * what data to write into config_ptr. 3384 * 3385 * String formatted like "%08x-%04x-%04x-%04x-%012x" 3386 */ 3387 char uuid[36]; 3388 }; 3389 3390 /** 3391 * @flags: 3392 * 3393 * Unused for now. Must be cleared to zero. 3394 */ 3395 __u32 flags; 3396 3397 /** 3398 * @data: 3399 * 3400 * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST, 3401 * i915 will write an array of __u64 of configuration identifiers. 3402 * 3403 * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA, 3404 * i915 will write a struct drm_i915_perf_oa_config. If the following 3405 * fields of struct drm_i915_perf_oa_config are not set to 0, i915 will 3406 * write into the associated pointers the values of submitted when the 3407 * configuration was created : 3408 * 3409 * - &drm_i915_perf_oa_config.n_mux_regs 3410 * - &drm_i915_perf_oa_config.n_boolean_regs 3411 * - &drm_i915_perf_oa_config.n_flex_regs 3412 */ 3413 __u8 data[]; 3414 }; 3415 3416 /** 3417 * enum drm_i915_gem_memory_class - Supported memory classes 3418 */ 3419 enum drm_i915_gem_memory_class { 3420 /** @I915_MEMORY_CLASS_SYSTEM: System memory */ 3421 I915_MEMORY_CLASS_SYSTEM = 0, 3422 /** @I915_MEMORY_CLASS_DEVICE: Device local-memory */ 3423 I915_MEMORY_CLASS_DEVICE, 3424 }; 3425 3426 /** 3427 * struct drm_i915_gem_memory_class_instance - Identify particular memory region 3428 */ 3429 struct drm_i915_gem_memory_class_instance { 3430 /** @memory_class: See enum drm_i915_gem_memory_class */ 3431 __u16 memory_class; 3432 3433 /** @memory_instance: Which instance */ 3434 __u16 memory_instance; 3435 }; 3436 3437 /** 3438 * struct drm_i915_memory_region_info - Describes one region as known to the 3439 * driver. 3440 * 3441 * Note this is using both struct drm_i915_query_item and struct drm_i915_query. 3442 * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS 3443 * at &drm_i915_query_item.query_id. 3444 */ 3445 struct drm_i915_memory_region_info { 3446 /** @region: The class:instance pair encoding */ 3447 struct drm_i915_gem_memory_class_instance region; 3448 3449 /** @rsvd0: MBZ */ 3450 __u32 rsvd0; 3451 3452 /** 3453 * @probed_size: Memory probed by the driver 3454 * 3455 * Note that it should not be possible to ever encounter a zero value 3456 * here, also note that no current region type will ever return -1 here. 3457 * Although for future region types, this might be a possibility. The 3458 * same applies to the other size fields. 3459 */ 3460 __u64 probed_size; 3461 3462 /** 3463 * @unallocated_size: Estimate of memory remaining 3464 * 3465 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. 3466 * Without this (or if this is an older kernel) the value here will 3467 * always equal the @probed_size. Note this is only currently tracked 3468 * for I915_MEMORY_CLASS_DEVICE regions (for other types the value here 3469 * will always equal the @probed_size). 3470 */ 3471 __u64 unallocated_size; 3472 3473 union { 3474 /** @rsvd1: MBZ */ 3475 __u64 rsvd1[8]; 3476 struct { 3477 /** 3478 * @probed_cpu_visible_size: Memory probed by the driver 3479 * that is CPU accessible. 3480 * 3481 * This will be always be <= @probed_size, and the 3482 * remainder (if there is any) will not be CPU 3483 * accessible. 3484 * 3485 * On systems without small BAR, the @probed_size will 3486 * always equal the @probed_cpu_visible_size, since all 3487 * of it will be CPU accessible. 3488 * 3489 * Note this is only tracked for 3490 * I915_MEMORY_CLASS_DEVICE regions (for other types the 3491 * value here will always equal the @probed_size). 3492 * 3493 * Note that if the value returned here is zero, then 3494 * this must be an old kernel which lacks the relevant 3495 * small-bar uAPI support (including 3496 * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on 3497 * such systems we should never actually end up with a 3498 * small BAR configuration, assuming we are able to load 3499 * the kernel module. Hence it should be safe to treat 3500 * this the same as when @probed_cpu_visible_size == 3501 * @probed_size. 3502 */ 3503 __u64 probed_cpu_visible_size; 3504 3505 /** 3506 * @unallocated_cpu_visible_size: Estimate of CPU 3507 * visible memory remaining. 3508 * 3509 * Note this is only tracked for 3510 * I915_MEMORY_CLASS_DEVICE regions (for other types the 3511 * value here will always equal the 3512 * @probed_cpu_visible_size). 3513 * 3514 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable 3515 * accounting. Without this the value here will always 3516 * equal the @probed_cpu_visible_size. Note this is only 3517 * currently tracked for I915_MEMORY_CLASS_DEVICE 3518 * regions (for other types the value here will also 3519 * always equal the @probed_cpu_visible_size). 3520 * 3521 * If this is an older kernel the value here will be 3522 * zero, see also @probed_cpu_visible_size. 3523 */ 3524 __u64 unallocated_cpu_visible_size; 3525 }; 3526 }; 3527 }; 3528 3529 /** 3530 * struct drm_i915_query_memory_regions 3531 * 3532 * The region info query enumerates all regions known to the driver by filling 3533 * in an array of struct drm_i915_memory_region_info structures. 3534 * 3535 * Example for getting the list of supported regions: 3536 * 3537 * .. code-block:: C 3538 * 3539 * struct drm_i915_query_memory_regions *info; 3540 * struct drm_i915_query_item item = { 3541 * .query_id = DRM_I915_QUERY_MEMORY_REGIONS; 3542 * }; 3543 * struct drm_i915_query query = { 3544 * .num_items = 1, 3545 * .items_ptr = (uintptr_t)&item, 3546 * }; 3547 * int err, i; 3548 * 3549 * // First query the size of the blob we need, this needs to be large 3550 * // enough to hold our array of regions. The kernel will fill out the 3551 * // item.length for us, which is the number of bytes we need. 3552 * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 3553 * if (err) ... 3554 * 3555 * info = calloc(1, item.length); 3556 * // Now that we allocated the required number of bytes, we call the ioctl 3557 * // again, this time with the data_ptr pointing to our newly allocated 3558 * // blob, which the kernel can then populate with the all the region info. 3559 * item.data_ptr = (uintptr_t)&info, 3560 * 3561 * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 3562 * if (err) ... 3563 * 3564 * // We can now access each region in the array 3565 * for (i = 0; i < info->num_regions; i++) { 3566 * struct drm_i915_memory_region_info mr = info->regions[i]; 3567 * u16 class = mr.region.class; 3568 * u16 instance = mr.region.instance; 3569 * 3570 * .... 3571 * } 3572 * 3573 * free(info); 3574 */ 3575 struct drm_i915_query_memory_regions { 3576 /** @num_regions: Number of supported regions */ 3577 __u32 num_regions; 3578 3579 /** @rsvd: MBZ */ 3580 __u32 rsvd[3]; 3581 3582 /** @regions: Info about each supported region */ 3583 struct drm_i915_memory_region_info regions[]; 3584 }; 3585 3586 /** 3587 * struct drm_i915_query_guc_submission_version - query GuC submission interface version 3588 */ 3589 struct drm_i915_query_guc_submission_version { 3590 /** @branch: Firmware branch version. */ 3591 __u32 branch; 3592 /** @major: Firmware major version. */ 3593 __u32 major; 3594 /** @minor: Firmware minor version. */ 3595 __u32 minor; 3596 /** @patch: Firmware patch version. */ 3597 __u32 patch; 3598 }; 3599 3600 /** 3601 * DOC: GuC HWCONFIG blob uAPI 3602 * 3603 * The GuC produces a blob with information about the current device. 3604 * i915 reads this blob from GuC and makes it available via this uAPI. 3605 * 3606 * The format and meaning of the blob content are documented in the 3607 * Programmer's Reference Manual. 3608 */ 3609 3610 /** 3611 * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added 3612 * extension support using struct i915_user_extension. 3613 * 3614 * Note that new buffer flags should be added here, at least for the stuff that 3615 * is immutable. Previously we would have two ioctls, one to create the object 3616 * with gem_create, and another to apply various parameters, however this 3617 * creates some ambiguity for the params which are considered immutable. Also in 3618 * general we're phasing out the various SET/GET ioctls. 3619 */ 3620 struct drm_i915_gem_create_ext { 3621 /** 3622 * @size: Requested size for the object. 3623 * 3624 * The (page-aligned) allocated size for the object will be returned. 3625 * 3626 * On platforms like DG2/ATS the kernel will always use 64K or larger 3627 * pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a 3628 * minimum of 64K GTT alignment for such objects. 3629 * 3630 * NOTE: Previously the ABI here required a minimum GTT alignment of 2M 3631 * on DG2/ATS, due to how the hardware implemented 64K GTT page support, 3632 * where we had the following complications: 3633 * 3634 * 1) The entire PDE (which covers a 2MB virtual address range), must 3635 * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same 3636 * PDE is forbidden by the hardware. 3637 * 3638 * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM 3639 * objects. 3640 * 3641 * However on actual production HW this was completely changed to now 3642 * allow setting a TLB hint at the PTE level (see PS64), which is a lot 3643 * more flexible than the above. With this the 2M restriction was 3644 * dropped where we now only require 64K. 3645 */ 3646 __u64 size; 3647 3648 /** 3649 * @handle: Returned handle for the object. 3650 * 3651 * Object handles are nonzero. 3652 */ 3653 __u32 handle; 3654 3655 /** 3656 * @flags: Optional flags. 3657 * 3658 * Supported values: 3659 * 3660 * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that 3661 * the object will need to be accessed via the CPU. 3662 * 3663 * Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only 3664 * strictly required on configurations where some subset of the device 3665 * memory is directly visible/mappable through the CPU (which we also 3666 * call small BAR), like on some DG2+ systems. Note that this is quite 3667 * undesirable, but due to various factors like the client CPU, BIOS etc 3668 * it's something we can expect to see in the wild. See 3669 * &drm_i915_memory_region_info.probed_cpu_visible_size for how to 3670 * determine if this system applies. 3671 * 3672 * Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to 3673 * ensure the kernel can always spill the allocation to system memory, 3674 * if the object can't be allocated in the mappable part of 3675 * I915_MEMORY_CLASS_DEVICE. 3676 * 3677 * Also note that since the kernel only supports flat-CCS on objects 3678 * that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore 3679 * don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with 3680 * flat-CCS. 3681 * 3682 * Without this hint, the kernel will assume that non-mappable 3683 * I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the 3684 * kernel can still migrate the object to the mappable part, as a last 3685 * resort, if userspace ever CPU faults this object, but this might be 3686 * expensive, and so ideally should be avoided. 3687 * 3688 * On older kernels which lack the relevant small-bar uAPI support (see 3689 * also &drm_i915_memory_region_info.probed_cpu_visible_size), 3690 * usage of the flag will result in an error, but it should NEVER be 3691 * possible to end up with a small BAR configuration, assuming we can 3692 * also successfully load the i915 kernel module. In such cases the 3693 * entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as 3694 * such there are zero restrictions on where the object can be placed. 3695 */ 3696 #define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0) 3697 __u32 flags; 3698 3699 /** 3700 * @extensions: The chain of extensions to apply to this object. 3701 * 3702 * This will be useful in the future when we need to support several 3703 * different extensions, and we need to apply more than one when 3704 * creating the object. See struct i915_user_extension. 3705 * 3706 * If we don't supply any extensions then we get the same old gem_create 3707 * behaviour. 3708 * 3709 * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see 3710 * struct drm_i915_gem_create_ext_memory_regions. 3711 * 3712 * For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see 3713 * struct drm_i915_gem_create_ext_protected_content. 3714 * 3715 * For I915_GEM_CREATE_EXT_SET_PAT usage see 3716 * struct drm_i915_gem_create_ext_set_pat. 3717 */ 3718 #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0 3719 #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1 3720 #define I915_GEM_CREATE_EXT_SET_PAT 2 3721 __u64 extensions; 3722 }; 3723 3724 /** 3725 * struct drm_i915_gem_create_ext_memory_regions - The 3726 * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension. 3727 * 3728 * Set the object with the desired set of placements/regions in priority 3729 * order. Each entry must be unique and supported by the device. 3730 * 3731 * This is provided as an array of struct drm_i915_gem_memory_class_instance, or 3732 * an equivalent layout of class:instance pair encodings. See struct 3733 * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to 3734 * query the supported regions for a device. 3735 * 3736 * As an example, on discrete devices, if we wish to set the placement as 3737 * device local-memory we can do something like: 3738 * 3739 * .. code-block:: C 3740 * 3741 * struct drm_i915_gem_memory_class_instance region_lmem = { 3742 * .memory_class = I915_MEMORY_CLASS_DEVICE, 3743 * .memory_instance = 0, 3744 * }; 3745 * struct drm_i915_gem_create_ext_memory_regions regions = { 3746 * .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, 3747 * .regions = (uintptr_t)®ion_lmem, 3748 * .num_regions = 1, 3749 * }; 3750 * struct drm_i915_gem_create_ext create_ext = { 3751 * .size = 16 * PAGE_SIZE, 3752 * .extensions = (uintptr_t)®ions, 3753 * }; 3754 * 3755 * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); 3756 * if (err) ... 3757 * 3758 * At which point we get the object handle in &drm_i915_gem_create_ext.handle, 3759 * along with the final object size in &drm_i915_gem_create_ext.size, which 3760 * should account for any rounding up, if required. 3761 * 3762 * Note that userspace has no means of knowing the current backing region 3763 * for objects where @num_regions is larger than one. The kernel will only 3764 * ensure that the priority order of the @regions array is honoured, either 3765 * when initially placing the object, or when moving memory around due to 3766 * memory pressure 3767 * 3768 * On Flat-CCS capable HW, compression is supported for the objects residing 3769 * in I915_MEMORY_CLASS_DEVICE. When such objects (compressed) have other 3770 * memory class in @regions and migrated (by i915, due to memory 3771 * constraints) to the non I915_MEMORY_CLASS_DEVICE region, then i915 needs to 3772 * decompress the content. But i915 doesn't have the required information to 3773 * decompress the userspace compressed objects. 3774 * 3775 * So i915 supports Flat-CCS, on the objects which can reside only on 3776 * I915_MEMORY_CLASS_DEVICE regions. 3777 */ 3778 struct drm_i915_gem_create_ext_memory_regions { 3779 /** @base: Extension link. See struct i915_user_extension. */ 3780 struct i915_user_extension base; 3781 3782 /** @pad: MBZ */ 3783 __u32 pad; 3784 /** @num_regions: Number of elements in the @regions array. */ 3785 __u32 num_regions; 3786 /** 3787 * @regions: The regions/placements array. 3788 * 3789 * An array of struct drm_i915_gem_memory_class_instance. 3790 */ 3791 __u64 regions; 3792 }; 3793 3794 /** 3795 * struct drm_i915_gem_create_ext_protected_content - The 3796 * I915_OBJECT_PARAM_PROTECTED_CONTENT extension. 3797 * 3798 * If this extension is provided, buffer contents are expected to be protected 3799 * by PXP encryption and require decryption for scan out and processing. This 3800 * is only possible on platforms that have PXP enabled, on all other scenarios 3801 * using this extension will cause the ioctl to fail and return -ENODEV. The 3802 * flags parameter is reserved for future expansion and must currently be set 3803 * to zero. 3804 * 3805 * The buffer contents are considered invalid after a PXP session teardown. 3806 * 3807 * The encryption is guaranteed to be processed correctly only if the object 3808 * is submitted with a context created using the 3809 * I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. This will also enable extra checks 3810 * at submission time on the validity of the objects involved. 3811 * 3812 * Below is an example on how to create a protected object: 3813 * 3814 * .. code-block:: C 3815 * 3816 * struct drm_i915_gem_create_ext_protected_content protected_ext = { 3817 * .base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT }, 3818 * .flags = 0, 3819 * }; 3820 * struct drm_i915_gem_create_ext create_ext = { 3821 * .size = PAGE_SIZE, 3822 * .extensions = (uintptr_t)&protected_ext, 3823 * }; 3824 * 3825 * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); 3826 * if (err) ... 3827 */ 3828 struct drm_i915_gem_create_ext_protected_content { 3829 /** @base: Extension link. See struct i915_user_extension. */ 3830 struct i915_user_extension base; 3831 /** @flags: reserved for future usage, currently MBZ */ 3832 __u32 flags; 3833 }; 3834 3835 /** 3836 * struct drm_i915_gem_create_ext_set_pat - The 3837 * I915_GEM_CREATE_EXT_SET_PAT extension. 3838 * 3839 * If this extension is provided, the specified caching policy (PAT index) is 3840 * applied to the buffer object. 3841 * 3842 * Below is an example on how to create an object with specific caching policy: 3843 * 3844 * .. code-block:: C 3845 * 3846 * struct drm_i915_gem_create_ext_set_pat set_pat_ext = { 3847 * .base = { .name = I915_GEM_CREATE_EXT_SET_PAT }, 3848 * .pat_index = 0, 3849 * }; 3850 * struct drm_i915_gem_create_ext create_ext = { 3851 * .size = PAGE_SIZE, 3852 * .extensions = (uintptr_t)&set_pat_ext, 3853 * }; 3854 * 3855 * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); 3856 * if (err) ... 3857 */ 3858 struct drm_i915_gem_create_ext_set_pat { 3859 /** @base: Extension link. See struct i915_user_extension. */ 3860 struct i915_user_extension base; 3861 /** 3862 * @pat_index: PAT index to be set 3863 * PAT index is a bit field in Page Table Entry to control caching 3864 * behaviors for GPU accesses. The definition of PAT index is 3865 * platform dependent and can be found in hardware specifications, 3866 */ 3867 __u32 pat_index; 3868 /** @rsvd: reserved for future use */ 3869 __u32 rsvd; 3870 }; 3871 3872 /* ID of the protected content session managed by i915 when PXP is active */ 3873 #define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf 3874 3875 #if defined(__cplusplus) 3876 } 3877 #endif 3878 3879 #endif /* _UAPI_I915_DRM_H_ */ 3880