1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
25f3cc447SSylwester Nawrocki /*
356bc911aSSylwester Nawrocki * Samsung S5P/Exynos4 SoC series camera interface driver header
45f3cc447SSylwester Nawrocki *
556bc911aSSylwester Nawrocki * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
656bc911aSSylwester Nawrocki * Sylwester Nawrocki <s.nawrocki@samsung.com>
75f3cc447SSylwester Nawrocki */
85f3cc447SSylwester Nawrocki
9df7e09a3SSylwester Nawrocki #ifndef S5P_FIMC_H_
10df7e09a3SSylwester Nawrocki #define S5P_FIMC_H_
115f3cc447SSylwester Nawrocki
12b9ee31e6SSylwester Nawrocki #include <media/media-entity.h>
13bc7584b0SSylwester Nawrocki #include <media/v4l2-dev.h>
1480f958f4SSylwester Nawrocki #include <media/v4l2-mediabus.h>
15b9ee31e6SSylwester Nawrocki
1656bc911aSSylwester Nawrocki /*
1702399e35SSylwester Nawrocki * Enumeration of data inputs to the camera subsystem.
1802399e35SSylwester Nawrocki */
1902399e35SSylwester Nawrocki enum fimc_input {
2002399e35SSylwester Nawrocki FIMC_INPUT_PARALLEL_0 = 1,
2102399e35SSylwester Nawrocki FIMC_INPUT_PARALLEL_1,
2202399e35SSylwester Nawrocki FIMC_INPUT_MIPI_CSI2_0 = 3,
2302399e35SSylwester Nawrocki FIMC_INPUT_MIPI_CSI2_1,
2402399e35SSylwester Nawrocki FIMC_INPUT_WRITEBACK_A = 5,
2502399e35SSylwester Nawrocki FIMC_INPUT_WRITEBACK_B,
2602399e35SSylwester Nawrocki FIMC_INPUT_WRITEBACK_ISP = 5,
2702399e35SSylwester Nawrocki };
2802399e35SSylwester Nawrocki
2902399e35SSylwester Nawrocki /*
3056bc911aSSylwester Nawrocki * Enumeration of the FIMC data bus types.
3156bc911aSSylwester Nawrocki */
3256bc911aSSylwester Nawrocki enum fimc_bus_type {
3356bc911aSSylwester Nawrocki /* Camera parallel bus */
3456bc911aSSylwester Nawrocki FIMC_BUS_TYPE_ITU_601 = 1,
3556bc911aSSylwester Nawrocki /* Camera parallel bus with embedded synchronization */
3656bc911aSSylwester Nawrocki FIMC_BUS_TYPE_ITU_656,
3756bc911aSSylwester Nawrocki /* Camera MIPI-CSI2 serial bus */
3856bc911aSSylwester Nawrocki FIMC_BUS_TYPE_MIPI_CSI2,
3956bc911aSSylwester Nawrocki /* FIFO link from LCD controller (WriteBack A) */
4056bc911aSSylwester Nawrocki FIMC_BUS_TYPE_LCD_WRITEBACK_A,
4156bc911aSSylwester Nawrocki /* FIFO link from LCD controller (WriteBack B) */
4256bc911aSSylwester Nawrocki FIMC_BUS_TYPE_LCD_WRITEBACK_B,
4356bc911aSSylwester Nawrocki /* FIFO link from FIMC-IS */
4456bc911aSSylwester Nawrocki FIMC_BUS_TYPE_ISP_WRITEBACK = FIMC_BUS_TYPE_LCD_WRITEBACK_B,
455f3cc447SSylwester Nawrocki };
465f3cc447SSylwester Nawrocki
472b13f7d4SSylwester Nawrocki #define fimc_input_is_parallel(x) ((x) == 1 || (x) == 2)
482b13f7d4SSylwester Nawrocki #define fimc_input_is_mipi_csi(x) ((x) == 3 || (x) == 4)
492b13f7d4SSylwester Nawrocki
50488f29d0SSylwester Nawrocki /*
51488f29d0SSylwester Nawrocki * The subdevices' group IDs.
52488f29d0SSylwester Nawrocki */
53488f29d0SSylwester Nawrocki #define GRP_ID_SENSOR (1 << 8)
54488f29d0SSylwester Nawrocki #define GRP_ID_FIMC_IS_SENSOR (1 << 9)
55488f29d0SSylwester Nawrocki #define GRP_ID_WRITEBACK (1 << 10)
56488f29d0SSylwester Nawrocki #define GRP_ID_CSIS (1 << 11)
57488f29d0SSylwester Nawrocki #define GRP_ID_FIMC (1 << 12)
58488f29d0SSylwester Nawrocki #define GRP_ID_FLITE (1 << 13)
59488f29d0SSylwester Nawrocki #define GRP_ID_FIMC_IS (1 << 14)
60488f29d0SSylwester Nawrocki
615f3cc447SSylwester Nawrocki /**
6256bc911aSSylwester Nawrocki * struct fimc_source_info - video source description required for the host
6356bc911aSSylwester Nawrocki * interface configuration
645f3cc447SSylwester Nawrocki *
6556bc911aSSylwester Nawrocki * @fimc_bus_type: FIMC camera input type
6656bc911aSSylwester Nawrocki * @sensor_bus_type: image sensor bus type, MIPI, ITU-R BT.601 etc.
6756bc911aSSylwester Nawrocki * @flags: the parallel sensor bus flags defining signals polarity (V4L2_MBUS_*)
685f3cc447SSylwester Nawrocki * @mux_id: FIMC camera interface multiplexer index (separate for MIPI and ITU)
695f3cc447SSylwester Nawrocki */
7056bc911aSSylwester Nawrocki struct fimc_source_info {
7156bc911aSSylwester Nawrocki enum fimc_bus_type fimc_bus_type;
7256bc911aSSylwester Nawrocki enum fimc_bus_type sensor_bus_type;
7356bc911aSSylwester Nawrocki u16 flags;
745f3cc447SSylwester Nawrocki u16 mux_id;
755f3cc447SSylwester Nawrocki };
76e1d72f4dSSylwester Nawrocki
77e1d72f4dSSylwester Nawrocki /*
78e1d72f4dSSylwester Nawrocki * v4l2_device notification id. This is only for internal use in the kernel.
79e1d72f4dSSylwester Nawrocki * Sensor subdevs should issue S5P_FIMC_TX_END_NOTIFY notification in single
80e1d72f4dSSylwester Nawrocki * frame capture mode when there is only one VSYNC pulse issued by the sensor
81e907bf3cSMauro Carvalho Chehab * at beginning of the frame transmission.
82e1d72f4dSSylwester Nawrocki */
83e1d72f4dSSylwester Nawrocki #define S5P_FIMC_TX_END_NOTIFY _IO('e', 0)
84e1d72f4dSSylwester Nawrocki
8580f958f4SSylwester Nawrocki #define FIMC_MAX_PLANES 3
8680f958f4SSylwester Nawrocki
8780f958f4SSylwester Nawrocki /**
8880f958f4SSylwester Nawrocki * struct fimc_fmt - color format data structure
8980f958f4SSylwester Nawrocki * @mbus_code: media bus pixel code, -1 if not applicable
9080f958f4SSylwester Nawrocki * @fourcc: fourcc code for this format, 0 if not applicable
9180f958f4SSylwester Nawrocki * @color: the driver's private color format id
9280f958f4SSylwester Nawrocki * @memplanes: number of physically non-contiguous data planes
9380f958f4SSylwester Nawrocki * @colplanes: number of physically contiguous data planes
941c26190aSSylwester Nawrocki * @colorspace: v4l2 colorspace (V4L2_COLORSPACE_*)
9580f958f4SSylwester Nawrocki * @depth: per plane driver's private 'number of bits per pixel'
9680f958f4SSylwester Nawrocki * @mdataplanes: bitmask indicating meta data plane(s), (1 << plane_no)
9780f958f4SSylwester Nawrocki * @flags: flags indicating which operation mode format applies to
9880f958f4SSylwester Nawrocki */
9980f958f4SSylwester Nawrocki struct fimc_fmt {
10027ffaeb0SBoris BREZILLON u32 mbus_code;
10180f958f4SSylwester Nawrocki u32 fourcc;
10280f958f4SSylwester Nawrocki u32 color;
10380f958f4SSylwester Nawrocki u16 memplanes;
10480f958f4SSylwester Nawrocki u16 colplanes;
1051c26190aSSylwester Nawrocki u8 colorspace;
10680f958f4SSylwester Nawrocki u8 depth[FIMC_MAX_PLANES];
10780f958f4SSylwester Nawrocki u16 mdataplanes;
10880f958f4SSylwester Nawrocki u16 flags;
10980f958f4SSylwester Nawrocki #define FMT_FLAGS_CAM (1 << 0)
11080f958f4SSylwester Nawrocki #define FMT_FLAGS_M2M_IN (1 << 1)
11180f958f4SSylwester Nawrocki #define FMT_FLAGS_M2M_OUT (1 << 2)
11280f958f4SSylwester Nawrocki #define FMT_FLAGS_M2M (1 << 1 | 1 << 2)
11380f958f4SSylwester Nawrocki #define FMT_HAS_ALPHA (1 << 3)
11480f958f4SSylwester Nawrocki #define FMT_FLAGS_COMPRESSED (1 << 4)
11580f958f4SSylwester Nawrocki #define FMT_FLAGS_WRITEBACK (1 << 5)
116e90ad659SSylwester Nawrocki #define FMT_FLAGS_RAW_BAYER (1 << 6)
117e90ad659SSylwester Nawrocki #define FMT_FLAGS_YUV (1 << 7)
11880f958f4SSylwester Nawrocki };
11980f958f4SSylwester Nawrocki
120403dfbecSSylwester Nawrocki struct exynos_media_pipeline;
1210f735f52SSylwester Nawrocki
122403dfbecSSylwester Nawrocki /*
123403dfbecSSylwester Nawrocki * Media pipeline operations to be called from within a video node, i.e. the
124403dfbecSSylwester Nawrocki * last entity within the pipeline. Implemented by related media device driver.
125403dfbecSSylwester Nawrocki */
126403dfbecSSylwester Nawrocki struct exynos_media_pipeline_ops {
127403dfbecSSylwester Nawrocki int (*prepare)(struct exynos_media_pipeline *p,
128403dfbecSSylwester Nawrocki struct media_entity *me);
129403dfbecSSylwester Nawrocki int (*unprepare)(struct exynos_media_pipeline *p);
130403dfbecSSylwester Nawrocki int (*open)(struct exynos_media_pipeline *p, struct media_entity *me,
131403dfbecSSylwester Nawrocki bool resume);
132403dfbecSSylwester Nawrocki int (*close)(struct exynos_media_pipeline *p);
133403dfbecSSylwester Nawrocki int (*set_stream)(struct exynos_media_pipeline *p, bool state);
1340f735f52SSylwester Nawrocki };
1350f735f52SSylwester Nawrocki
136bc7584b0SSylwester Nawrocki struct exynos_video_entity {
137bc7584b0SSylwester Nawrocki struct video_device vdev;
138403dfbecSSylwester Nawrocki struct exynos_media_pipeline *pipe;
139bc7584b0SSylwester Nawrocki };
140bc7584b0SSylwester Nawrocki
141403dfbecSSylwester Nawrocki struct exynos_media_pipeline {
142403dfbecSSylwester Nawrocki struct media_pipeline mp;
143403dfbecSSylwester Nawrocki const struct exynos_media_pipeline_ops *ops;
144b9ee31e6SSylwester Nawrocki };
145b9ee31e6SSylwester Nawrocki
vdev_to_exynos_video_entity(struct video_device * vdev)146403dfbecSSylwester Nawrocki static inline struct exynos_video_entity *vdev_to_exynos_video_entity(
147403dfbecSSylwester Nawrocki struct video_device *vdev)
148403dfbecSSylwester Nawrocki {
149403dfbecSSylwester Nawrocki return container_of(vdev, struct exynos_video_entity, vdev);
150403dfbecSSylwester Nawrocki }
151403dfbecSSylwester Nawrocki
152403dfbecSSylwester Nawrocki #define fimc_pipeline_call(ent, op, args...) \
1533090a191SSimon Shields ((!(ent) || !(ent)->pipe) ? -ENOENT : \
1543090a191SSimon Shields (((ent)->pipe->ops && (ent)->pipe->ops->op) ? \
155403dfbecSSylwester Nawrocki (ent)->pipe->ops->op(((ent)->pipe), ##args) : -ENOIOCTLCMD)) \
156b9ee31e6SSylwester Nawrocki
157df7e09a3SSylwester Nawrocki #endif /* S5P_FIMC_H_ */
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