1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates 4 * Copyright (c) 2023 Intel and affiliates 5 */ 6 7 #ifndef __DPLL_H__ 8 #define __DPLL_H__ 9 10 #include <uapi/linux/dpll.h> 11 #include <linux/device.h> 12 #include <linux/netlink.h> 13 #include <linux/netdevice.h> 14 #include <linux/rtnetlink.h> 15 16 struct dpll_device; 17 struct dpll_pin; 18 struct dpll_pin_esync; 19 20 struct dpll_device_ops { 21 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv, 22 enum dpll_mode *mode, struct netlink_ext_ack *extack); 23 int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv, 24 enum dpll_lock_status *status, 25 enum dpll_lock_status_error *status_error, 26 struct netlink_ext_ack *extack); 27 int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv, 28 s32 *temp, struct netlink_ext_ack *extack); 29 int (*clock_quality_level_get)(const struct dpll_device *dpll, 30 void *dpll_priv, 31 unsigned long *qls, 32 struct netlink_ext_ack *extack); 33 }; 34 35 struct dpll_pin_ops { 36 int (*frequency_set)(const struct dpll_pin *pin, void *pin_priv, 37 const struct dpll_device *dpll, void *dpll_priv, 38 const u64 frequency, 39 struct netlink_ext_ack *extack); 40 int (*frequency_get)(const struct dpll_pin *pin, void *pin_priv, 41 const struct dpll_device *dpll, void *dpll_priv, 42 u64 *frequency, struct netlink_ext_ack *extack); 43 int (*direction_set)(const struct dpll_pin *pin, void *pin_priv, 44 const struct dpll_device *dpll, void *dpll_priv, 45 const enum dpll_pin_direction direction, 46 struct netlink_ext_ack *extack); 47 int (*direction_get)(const struct dpll_pin *pin, void *pin_priv, 48 const struct dpll_device *dpll, void *dpll_priv, 49 enum dpll_pin_direction *direction, 50 struct netlink_ext_ack *extack); 51 int (*state_on_pin_get)(const struct dpll_pin *pin, void *pin_priv, 52 const struct dpll_pin *parent_pin, 53 void *parent_pin_priv, 54 enum dpll_pin_state *state, 55 struct netlink_ext_ack *extack); 56 int (*state_on_dpll_get)(const struct dpll_pin *pin, void *pin_priv, 57 const struct dpll_device *dpll, 58 void *dpll_priv, enum dpll_pin_state *state, 59 struct netlink_ext_ack *extack); 60 int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv, 61 const struct dpll_pin *parent_pin, 62 void *parent_pin_priv, 63 const enum dpll_pin_state state, 64 struct netlink_ext_ack *extack); 65 int (*state_on_dpll_set)(const struct dpll_pin *pin, void *pin_priv, 66 const struct dpll_device *dpll, 67 void *dpll_priv, 68 const enum dpll_pin_state state, 69 struct netlink_ext_ack *extack); 70 int (*prio_get)(const struct dpll_pin *pin, void *pin_priv, 71 const struct dpll_device *dpll, void *dpll_priv, 72 u32 *prio, struct netlink_ext_ack *extack); 73 int (*prio_set)(const struct dpll_pin *pin, void *pin_priv, 74 const struct dpll_device *dpll, void *dpll_priv, 75 const u32 prio, struct netlink_ext_ack *extack); 76 int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv, 77 const struct dpll_device *dpll, void *dpll_priv, 78 s64 *phase_offset, 79 struct netlink_ext_ack *extack); 80 int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv, 81 const struct dpll_device *dpll, void *dpll_priv, 82 s32 *phase_adjust, 83 struct netlink_ext_ack *extack); 84 int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv, 85 const struct dpll_device *dpll, void *dpll_priv, 86 const s32 phase_adjust, 87 struct netlink_ext_ack *extack); 88 int (*ffo_get)(const struct dpll_pin *pin, void *pin_priv, 89 const struct dpll_device *dpll, void *dpll_priv, 90 s64 *ffo, struct netlink_ext_ack *extack); 91 int (*esync_set)(const struct dpll_pin *pin, void *pin_priv, 92 const struct dpll_device *dpll, void *dpll_priv, 93 u64 freq, struct netlink_ext_ack *extack); 94 int (*esync_get)(const struct dpll_pin *pin, void *pin_priv, 95 const struct dpll_device *dpll, void *dpll_priv, 96 struct dpll_pin_esync *esync, 97 struct netlink_ext_ack *extack); 98 }; 99 100 struct dpll_pin_frequency { 101 u64 min; 102 u64 max; 103 }; 104 105 #define DPLL_PIN_FREQUENCY_RANGE(_min, _max) \ 106 { \ 107 .min = _min, \ 108 .max = _max, \ 109 } 110 111 #define DPLL_PIN_FREQUENCY(_val) DPLL_PIN_FREQUENCY_RANGE(_val, _val) 112 #define DPLL_PIN_FREQUENCY_1PPS \ 113 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_1_HZ) 114 #define DPLL_PIN_FREQUENCY_10MHZ \ 115 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_MHZ) 116 #define DPLL_PIN_FREQUENCY_IRIG_B \ 117 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_KHZ) 118 #define DPLL_PIN_FREQUENCY_DCF77 \ 119 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ) 120 121 struct dpll_pin_phase_adjust_range { 122 s32 min; 123 s32 max; 124 }; 125 126 struct dpll_pin_esync { 127 u64 freq; 128 const struct dpll_pin_frequency *range; 129 u8 range_num; 130 u8 pulse; 131 }; 132 133 struct dpll_pin_properties { 134 const char *board_label; 135 const char *panel_label; 136 const char *package_label; 137 enum dpll_pin_type type; 138 unsigned long capabilities; 139 u32 freq_supported_num; 140 struct dpll_pin_frequency *freq_supported; 141 struct dpll_pin_phase_adjust_range phase_range; 142 }; 143 144 #if IS_ENABLED(CONFIG_DPLL) 145 void dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin); 146 void dpll_netdev_pin_clear(struct net_device *dev); 147 148 size_t dpll_netdev_pin_handle_size(const struct net_device *dev); 149 int dpll_netdev_add_pin_handle(struct sk_buff *msg, 150 const struct net_device *dev); 151 #else 152 static inline void 153 dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin) { } 154 static inline void dpll_netdev_pin_clear(struct net_device *dev) { } 155 156 static inline size_t dpll_netdev_pin_handle_size(const struct net_device *dev) 157 { 158 return 0; 159 } 160 161 static inline int 162 dpll_netdev_add_pin_handle(struct sk_buff *msg, const struct net_device *dev) 163 { 164 return 0; 165 } 166 #endif 167 168 struct dpll_device * 169 dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module); 170 171 void dpll_device_put(struct dpll_device *dpll); 172 173 int dpll_device_register(struct dpll_device *dpll, enum dpll_type type, 174 const struct dpll_device_ops *ops, void *priv); 175 176 void dpll_device_unregister(struct dpll_device *dpll, 177 const struct dpll_device_ops *ops, void *priv); 178 179 struct dpll_pin * 180 dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module, 181 const struct dpll_pin_properties *prop); 182 183 int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin, 184 const struct dpll_pin_ops *ops, void *priv); 185 186 void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin, 187 const struct dpll_pin_ops *ops, void *priv); 188 189 void dpll_pin_put(struct dpll_pin *pin); 190 191 int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin, 192 const struct dpll_pin_ops *ops, void *priv); 193 194 void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin, 195 const struct dpll_pin_ops *ops, void *priv); 196 197 int dpll_device_change_ntf(struct dpll_device *dpll); 198 199 int dpll_pin_change_ntf(struct dpll_pin *pin); 200 201 #endif 202