1476650a6SJacky Huang /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2476650a6SJacky Huang /* 3476650a6SJacky Huang * Copyright (C) 2023 Nuvoton Technologies. 4476650a6SJacky Huang * Author: Chi-Fen Li <cfli0@nuvoton.com> 5476650a6SJacky Huang * 6476650a6SJacky Huang * Device Tree binding constants for MA35D1 reset controller. 7476650a6SJacky Huang */ 8476650a6SJacky Huang 9476650a6SJacky Huang #ifndef __DT_BINDINGS_RESET_MA35D1_H 10476650a6SJacky Huang #define __DT_BINDINGS_RESET_MA35D1_H 11476650a6SJacky Huang 12476650a6SJacky Huang #define MA35D1_RESET_CHIP 0 13476650a6SJacky Huang #define MA35D1_RESET_CA35CR0 1 14476650a6SJacky Huang #define MA35D1_RESET_CA35CR1 2 15476650a6SJacky Huang #define MA35D1_RESET_CM4 3 16476650a6SJacky Huang #define MA35D1_RESET_PDMA0 4 17476650a6SJacky Huang #define MA35D1_RESET_PDMA1 5 18476650a6SJacky Huang #define MA35D1_RESET_PDMA2 6 19476650a6SJacky Huang #define MA35D1_RESET_PDMA3 7 20476650a6SJacky Huang #define MA35D1_RESET_DISP 8 21476650a6SJacky Huang #define MA35D1_RESET_VCAP0 9 22476650a6SJacky Huang #define MA35D1_RESET_VCAP1 10 23476650a6SJacky Huang #define MA35D1_RESET_GFX 11 24476650a6SJacky Huang #define MA35D1_RESET_VDEC 12 25476650a6SJacky Huang #define MA35D1_RESET_WHC0 13 26476650a6SJacky Huang #define MA35D1_RESET_WHC1 14 27476650a6SJacky Huang #define MA35D1_RESET_GMAC0 15 28476650a6SJacky Huang #define MA35D1_RESET_GMAC1 16 29476650a6SJacky Huang #define MA35D1_RESET_HWSEM 17 30476650a6SJacky Huang #define MA35D1_RESET_EBI 18 31476650a6SJacky Huang #define MA35D1_RESET_HSUSBH0 19 32476650a6SJacky Huang #define MA35D1_RESET_HSUSBH1 20 33476650a6SJacky Huang #define MA35D1_RESET_HSUSBD 21 34476650a6SJacky Huang #define MA35D1_RESET_USBHL 22 35476650a6SJacky Huang #define MA35D1_RESET_SDH0 23 36476650a6SJacky Huang #define MA35D1_RESET_SDH1 24 37476650a6SJacky Huang #define MA35D1_RESET_NAND 25 38476650a6SJacky Huang #define MA35D1_RESET_GPIO 26 39476650a6SJacky Huang #define MA35D1_RESET_MCTLP 27 40476650a6SJacky Huang #define MA35D1_RESET_MCTLC 28 41476650a6SJacky Huang #define MA35D1_RESET_DDRPUB 29 42476650a6SJacky Huang #define MA35D1_RESET_TMR0 30 43476650a6SJacky Huang #define MA35D1_RESET_TMR1 31 44476650a6SJacky Huang #define MA35D1_RESET_TMR2 32 45476650a6SJacky Huang #define MA35D1_RESET_TMR3 33 46476650a6SJacky Huang #define MA35D1_RESET_I2C0 34 47476650a6SJacky Huang #define MA35D1_RESET_I2C1 35 48476650a6SJacky Huang #define MA35D1_RESET_I2C2 36 49476650a6SJacky Huang #define MA35D1_RESET_I2C3 37 50476650a6SJacky Huang #define MA35D1_RESET_QSPI0 38 51476650a6SJacky Huang #define MA35D1_RESET_SPI0 39 52476650a6SJacky Huang #define MA35D1_RESET_SPI1 40 53476650a6SJacky Huang #define MA35D1_RESET_SPI2 41 54476650a6SJacky Huang #define MA35D1_RESET_UART0 42 55476650a6SJacky Huang #define MA35D1_RESET_UART1 43 56476650a6SJacky Huang #define MA35D1_RESET_UART2 44 57476650a6SJacky Huang #define MA35D1_RESET_UART3 45 58476650a6SJacky Huang #define MA35D1_RESET_UART4 46 59476650a6SJacky Huang #define MA35D1_RESET_UART5 47 60476650a6SJacky Huang #define MA35D1_RESET_UART6 48 61476650a6SJacky Huang #define MA35D1_RESET_UART7 49 62476650a6SJacky Huang #define MA35D1_RESET_CANFD0 50 63476650a6SJacky Huang #define MA35D1_RESET_CANFD1 51 64476650a6SJacky Huang #define MA35D1_RESET_EADC0 52 65476650a6SJacky Huang #define MA35D1_RESET_I2S0 53 66476650a6SJacky Huang #define MA35D1_RESET_SC0 54 67476650a6SJacky Huang #define MA35D1_RESET_SC1 55 68476650a6SJacky Huang #define MA35D1_RESET_QSPI1 56 69476650a6SJacky Huang #define MA35D1_RESET_SPI3 57 70476650a6SJacky Huang #define MA35D1_RESET_EPWM0 58 71476650a6SJacky Huang #define MA35D1_RESET_EPWM1 59 72476650a6SJacky Huang #define MA35D1_RESET_QEI0 60 73476650a6SJacky Huang #define MA35D1_RESET_QEI1 61 74476650a6SJacky Huang #define MA35D1_RESET_ECAP0 62 75476650a6SJacky Huang #define MA35D1_RESET_ECAP1 63 76476650a6SJacky Huang #define MA35D1_RESET_CANFD2 64 77476650a6SJacky Huang #define MA35D1_RESET_ADC0 65 78476650a6SJacky Huang #define MA35D1_RESET_TMR4 66 79476650a6SJacky Huang #define MA35D1_RESET_TMR5 67 80476650a6SJacky Huang #define MA35D1_RESET_TMR6 68 81476650a6SJacky Huang #define MA35D1_RESET_TMR7 69 82476650a6SJacky Huang #define MA35D1_RESET_TMR8 70 83476650a6SJacky Huang #define MA35D1_RESET_TMR9 71 84476650a6SJacky Huang #define MA35D1_RESET_TMR10 72 85476650a6SJacky Huang #define MA35D1_RESET_TMR11 73 86476650a6SJacky Huang #define MA35D1_RESET_UART8 74 87476650a6SJacky Huang #define MA35D1_RESET_UART9 75 88476650a6SJacky Huang #define MA35D1_RESET_UART10 76 89476650a6SJacky Huang #define MA35D1_RESET_UART11 77 90476650a6SJacky Huang #define MA35D1_RESET_UART12 78 91476650a6SJacky Huang #define MA35D1_RESET_UART13 79 92476650a6SJacky Huang #define MA35D1_RESET_UART14 80 93476650a6SJacky Huang #define MA35D1_RESET_UART15 81 94476650a6SJacky Huang #define MA35D1_RESET_UART16 82 95476650a6SJacky Huang #define MA35D1_RESET_I2S1 83 96476650a6SJacky Huang #define MA35D1_RESET_I2C4 84 97476650a6SJacky Huang #define MA35D1_RESET_I2C5 85 98476650a6SJacky Huang #define MA35D1_RESET_EPWM2 86 99476650a6SJacky Huang #define MA35D1_RESET_ECAP2 87 100476650a6SJacky Huang #define MA35D1_RESET_QEI2 88 101476650a6SJacky Huang #define MA35D1_RESET_CANFD3 89 102476650a6SJacky Huang #define MA35D1_RESET_KPI 90 103476650a6SJacky Huang #define MA35D1_RESET_GIC 91 104476650a6SJacky Huang #define MA35D1_RESET_SSMCC 92 105476650a6SJacky Huang #define MA35D1_RESET_SSPCC 93 106476650a6SJacky Huang #define MA35D1_RESET_COUNT 94 107476650a6SJacky Huang 108476650a6SJacky Huang #endif 109