1*5c8d08f3SDmitry Osipenko /* SPDX-License-Identifier: GPL-2.0 */ 2*5c8d08f3SDmitry Osipenko #ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H 3*5c8d08f3SDmitry Osipenko #define DT_BINDINGS_MEMORY_TEGRA20_MC_H 4*5c8d08f3SDmitry Osipenko 5*5c8d08f3SDmitry Osipenko #define TEGRA20_MC_RESET_AVPC 0 6*5c8d08f3SDmitry Osipenko #define TEGRA20_MC_RESET_DC 1 7*5c8d08f3SDmitry Osipenko #define TEGRA20_MC_RESET_DCB 2 8*5c8d08f3SDmitry Osipenko #define TEGRA20_MC_RESET_EPP 3 9*5c8d08f3SDmitry Osipenko #define TEGRA20_MC_RESET_2D 4 10*5c8d08f3SDmitry Osipenko #define TEGRA20_MC_RESET_HC 5 11*5c8d08f3SDmitry Osipenko #define TEGRA20_MC_RESET_ISP 6 12*5c8d08f3SDmitry Osipenko #define TEGRA20_MC_RESET_MPCORE 7 13*5c8d08f3SDmitry Osipenko #define TEGRA20_MC_RESET_MPEA 8 14*5c8d08f3SDmitry Osipenko #define TEGRA20_MC_RESET_MPEB 9 15*5c8d08f3SDmitry Osipenko #define TEGRA20_MC_RESET_MPEC 10 16*5c8d08f3SDmitry Osipenko #define TEGRA20_MC_RESET_3D 11 17*5c8d08f3SDmitry Osipenko #define TEGRA20_MC_RESET_PPCS 12 18*5c8d08f3SDmitry Osipenko #define TEGRA20_MC_RESET_VDE 13 19*5c8d08f3SDmitry Osipenko #define TEGRA20_MC_RESET_VI 14 20*5c8d08f3SDmitry Osipenko 21*5c8d08f3SDmitry Osipenko #endif 22