1*1c82407aSHoulong Wei /* SPDX-License-Identifier: GPL-2.0 */ 2*1c82407aSHoulong Wei /* 3*1c82407aSHoulong Wei * Copyright (c) 2018 MediaTek Inc. 4*1c82407aSHoulong Wei * Author: Houlong Wei <houlong.wei@mediatek.com> 5*1c82407aSHoulong Wei * 6*1c82407aSHoulong Wei */ 7*1c82407aSHoulong Wei 8*1c82407aSHoulong Wei #ifndef _DT_BINDINGS_GCE_MT8173_H 9*1c82407aSHoulong Wei #define _DT_BINDINGS_GCE_MT8173_H 10*1c82407aSHoulong Wei 11*1c82407aSHoulong Wei /* GCE HW thread priority */ 12*1c82407aSHoulong Wei #define CMDQ_THR_PRIO_LOWEST 0 13*1c82407aSHoulong Wei #define CMDQ_THR_PRIO_HIGHEST 1 14*1c82407aSHoulong Wei 15*1c82407aSHoulong Wei /* GCE SUBSYS */ 16*1c82407aSHoulong Wei #define SUBSYS_1400XXXX 1 17*1c82407aSHoulong Wei #define SUBSYS_1401XXXX 2 18*1c82407aSHoulong Wei #define SUBSYS_1402XXXX 3 19*1c82407aSHoulong Wei 20*1c82407aSHoulong Wei /* GCE HW EVENT */ 21*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_OVL0_SOF 11 22*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_OVL1_SOF 12 23*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_RDMA0_SOF 13 24*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_RDMA1_SOF 14 25*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_RDMA2_SOF 15 26*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_WDMA0_SOF 16 27*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_WDMA1_SOF 17 28*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_OVL0_EOF 39 29*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_OVL1_EOF 40 30*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_RDMA0_EOF 41 31*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_RDMA1_EOF 42 32*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_RDMA2_EOF 43 33*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_WDMA0_EOF 44 34*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_WDMA1_EOF 45 35*1c82407aSHoulong Wei #define CMDQ_EVENT_MUTEX0_STREAM_EOF 53 36*1c82407aSHoulong Wei #define CMDQ_EVENT_MUTEX1_STREAM_EOF 54 37*1c82407aSHoulong Wei #define CMDQ_EVENT_MUTEX2_STREAM_EOF 55 38*1c82407aSHoulong Wei #define CMDQ_EVENT_MUTEX3_STREAM_EOF 56 39*1c82407aSHoulong Wei #define CMDQ_EVENT_MUTEX4_STREAM_EOF 57 40*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 63 41*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 64 42*1c82407aSHoulong Wei #define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 65 43*1c82407aSHoulong Wei 44*1c82407aSHoulong Wei #endif 45