1f99cdbd8SKathiravan T /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2f99cdbd8SKathiravan T /* 3f99cdbd8SKathiravan T * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4f99cdbd8SKathiravan T */ 5f99cdbd8SKathiravan T 6f99cdbd8SKathiravan T #ifndef _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H 7f99cdbd8SKathiravan T #define _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H 8f99cdbd8SKathiravan T 9f99cdbd8SKathiravan T #define GPLL0_MAIN 0 10f99cdbd8SKathiravan T #define GPLL0 1 11f99cdbd8SKathiravan T #define GPLL2_MAIN 2 12f99cdbd8SKathiravan T #define GPLL2 3 13f99cdbd8SKathiravan T #define GPLL4_MAIN 4 14f99cdbd8SKathiravan T #define GPLL4 5 15f99cdbd8SKathiravan T #define GCC_ADSS_PWM_CLK 6 16f99cdbd8SKathiravan T #define GCC_ADSS_PWM_CLK_SRC 7 17f99cdbd8SKathiravan T #define GCC_AHB_CLK 8 18f99cdbd8SKathiravan T #define GCC_APSS_AXI_CLK_SRC 9 19f99cdbd8SKathiravan T #define GCC_BLSP1_AHB_CLK 10 20f99cdbd8SKathiravan T #define GCC_BLSP1_QUP1_I2C_APPS_CLK 11 21f99cdbd8SKathiravan T #define GCC_BLSP1_QUP1_SPI_APPS_CLK 12 22f99cdbd8SKathiravan T #define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 13 23f99cdbd8SKathiravan T #define GCC_BLSP1_QUP2_I2C_APPS_CLK 14 24f99cdbd8SKathiravan T #define GCC_BLSP1_QUP2_SPI_APPS_CLK 15 25f99cdbd8SKathiravan T #define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 16 26f99cdbd8SKathiravan T #define GCC_BLSP1_QUP3_I2C_APPS_CLK 17 27f99cdbd8SKathiravan T #define GCC_BLSP1_QUP3_SPI_APPS_CLK 18 28f99cdbd8SKathiravan T #define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 19 29f99cdbd8SKathiravan T #define GCC_BLSP1_SLEEP_CLK 20 30f99cdbd8SKathiravan T #define GCC_BLSP1_UART1_APPS_CLK 21 31f99cdbd8SKathiravan T #define GCC_BLSP1_UART1_APPS_CLK_SRC 22 32f99cdbd8SKathiravan T #define GCC_BLSP1_UART2_APPS_CLK 23 33f99cdbd8SKathiravan T #define GCC_BLSP1_UART2_APPS_CLK_SRC 24 34f99cdbd8SKathiravan T #define GCC_BLSP1_UART3_APPS_CLK 25 35f99cdbd8SKathiravan T #define GCC_BLSP1_UART3_APPS_CLK_SRC 26 36f99cdbd8SKathiravan T #define GCC_CE_AHB_CLK 27 37f99cdbd8SKathiravan T #define GCC_CE_AXI_CLK 28 38f99cdbd8SKathiravan T #define GCC_CE_PCNOC_AHB_CLK 29 39f99cdbd8SKathiravan T #define GCC_CMN_12GPLL_AHB_CLK 30 40f99cdbd8SKathiravan T #define GCC_CMN_12GPLL_APU_CLK 31 41f99cdbd8SKathiravan T #define GCC_CMN_12GPLL_SYS_CLK 32 42f99cdbd8SKathiravan T #define GCC_GP1_CLK 33 43f99cdbd8SKathiravan T #define GCC_GP1_CLK_SRC 34 44f99cdbd8SKathiravan T #define GCC_GP2_CLK 35 45f99cdbd8SKathiravan T #define GCC_GP2_CLK_SRC 36 46f99cdbd8SKathiravan T #define GCC_LPASS_CORE_AXIM_CLK 37 47f99cdbd8SKathiravan T #define GCC_LPASS_SWAY_CLK 38 48f99cdbd8SKathiravan T #define GCC_LPASS_SWAY_CLK_SRC 39 49f99cdbd8SKathiravan T #define GCC_MDIO_AHB_CLK 40 50f99cdbd8SKathiravan T #define GCC_MDIO_SLAVE_AHB_CLK 41 51f99cdbd8SKathiravan T #define GCC_MEM_NOC_Q6_AXI_CLK 42 52f99cdbd8SKathiravan T #define GCC_MEM_NOC_TS_CLK 43 53f99cdbd8SKathiravan T #define GCC_NSS_TS_CLK 44 54f99cdbd8SKathiravan T #define GCC_NSS_TS_CLK_SRC 45 55f99cdbd8SKathiravan T #define GCC_NSSCC_CLK 46 56f99cdbd8SKathiravan T #define GCC_NSSCFG_CLK 47 57f99cdbd8SKathiravan T #define GCC_NSSNOC_ATB_CLK 48 58f99cdbd8SKathiravan T #define GCC_NSSNOC_NSSCC_CLK 49 59f99cdbd8SKathiravan T #define GCC_NSSNOC_QOSGEN_REF_CLK 50 60f99cdbd8SKathiravan T #define GCC_NSSNOC_SNOC_1_CLK 51 61f99cdbd8SKathiravan T #define GCC_NSSNOC_SNOC_CLK 52 62f99cdbd8SKathiravan T #define GCC_NSSNOC_TIMEOUT_REF_CLK 53 63f99cdbd8SKathiravan T #define GCC_NSSNOC_XO_DCD_CLK 54 64f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AHB_CLK 55 65f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AUX_CLK 56 66f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_CLK_SRC 57 67f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_M_CLK 58 68f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK 59 69f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_S_CLK 60 70f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_PIPE_CLK 61 71f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_RCHG_CLK 62 72f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_RCHG_CLK_SRC 63 73f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AHB_CLK 64 74f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AUX_CLK 65 75f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_CLK_SRC 66 76f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_M_CLK 67 77f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK 68 78f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_S_CLK 69 79f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_PIPE_CLK 70 80f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_RCHG_CLK 71 81f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_RCHG_CLK_SRC 72 82f99cdbd8SKathiravan T #define GCC_PCIE3X1_PHY_AHB_CLK 73 83f99cdbd8SKathiravan T #define GCC_PCIE3X2_AHB_CLK 74 84f99cdbd8SKathiravan T #define GCC_PCIE3X2_AUX_CLK 75 85f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_M_CLK 76 86f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_M_CLK_SRC 77 87f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_S_BRIDGE_CLK 78 88f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_S_CLK 79 89f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_S_CLK_SRC 80 90f99cdbd8SKathiravan T #define GCC_PCIE3X2_PHY_AHB_CLK 81 91f99cdbd8SKathiravan T #define GCC_PCIE3X2_PIPE_CLK 82 92f99cdbd8SKathiravan T #define GCC_PCIE3X2_RCHG_CLK 83 93f99cdbd8SKathiravan T #define GCC_PCIE3X2_RCHG_CLK_SRC 84 94f99cdbd8SKathiravan T #define GCC_PCIE_AUX_CLK_SRC 85 95f99cdbd8SKathiravan T #define GCC_PCNOC_AT_CLK 86 96f99cdbd8SKathiravan T #define GCC_PCNOC_BFDCD_CLK_SRC 87 97f99cdbd8SKathiravan T #define GCC_PCNOC_LPASS_CLK 88 98f99cdbd8SKathiravan T #define GCC_PRNG_AHB_CLK 89 99f99cdbd8SKathiravan T #define GCC_Q6_AXIM_CLK_SRC 93 100f99cdbd8SKathiravan T #define GCC_QDSS_AT_CLK 99 101f99cdbd8SKathiravan T #define GCC_QDSS_AT_CLK_SRC 100 102f99cdbd8SKathiravan T #define GCC_QDSS_CFG_AHB_CLK 101 103f99cdbd8SKathiravan T #define GCC_QDSS_DAP_AHB_CLK 102 104f99cdbd8SKathiravan T #define GCC_QDSS_DAP_CLK 103 105f99cdbd8SKathiravan T #define GCC_QDSS_DAP_DIV_CLK_SRC 104 106f99cdbd8SKathiravan T #define GCC_QDSS_ETR_USB_CLK 105 107f99cdbd8SKathiravan T #define GCC_QDSS_EUD_AT_CLK 106 108f99cdbd8SKathiravan T #define GCC_QDSS_TSCTR_CLK_SRC 107 109f99cdbd8SKathiravan T #define GCC_QPIC_AHB_CLK 108 110f99cdbd8SKathiravan T #define GCC_QPIC_CLK 109 111f99cdbd8SKathiravan T #define GCC_QPIC_IO_MACRO_CLK 110 112f99cdbd8SKathiravan T #define GCC_QPIC_IO_MACRO_CLK_SRC 111 113f99cdbd8SKathiravan T #define GCC_QPIC_SLEEP_CLK 112 114f99cdbd8SKathiravan T #define GCC_SDCC1_AHB_CLK 113 115f99cdbd8SKathiravan T #define GCC_SDCC1_APPS_CLK 114 116f99cdbd8SKathiravan T #define GCC_SDCC1_APPS_CLK_SRC 115 117f99cdbd8SKathiravan T #define GCC_SLEEP_CLK_SRC 116 118f99cdbd8SKathiravan T #define GCC_SNOC_LPASS_CFG_CLK 117 119f99cdbd8SKathiravan T #define GCC_SNOC_NSSNOC_1_CLK 118 120f99cdbd8SKathiravan T #define GCC_SNOC_NSSNOC_CLK 119 121f99cdbd8SKathiravan T #define GCC_SNOC_PCIE3_1LANE_1_M_CLK 120 122f99cdbd8SKathiravan T #define GCC_SNOC_PCIE3_1LANE_1_S_CLK 121 123f99cdbd8SKathiravan T #define GCC_SNOC_PCIE3_1LANE_M_CLK 122 124f99cdbd8SKathiravan T #define GCC_SNOC_PCIE3_1LANE_S_CLK 123 125f99cdbd8SKathiravan T #define GCC_SNOC_PCIE3_2LANE_M_CLK 124 126f99cdbd8SKathiravan T #define GCC_SNOC_PCIE3_2LANE_S_CLK 125 127f99cdbd8SKathiravan T #define GCC_SNOC_USB_CLK 126 128f99cdbd8SKathiravan T #define GCC_SYS_NOC_AT_CLK 127 129f99cdbd8SKathiravan T #define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129 130f99cdbd8SKathiravan T #define GCC_UNIPHY0_AHB_CLK 130 131f99cdbd8SKathiravan T #define GCC_UNIPHY0_SYS_CLK 131 132f99cdbd8SKathiravan T #define GCC_UNIPHY1_AHB_CLK 132 133f99cdbd8SKathiravan T #define GCC_UNIPHY1_SYS_CLK 133 134f99cdbd8SKathiravan T #define GCC_UNIPHY_SYS_CLK_SRC 134 135f99cdbd8SKathiravan T #define GCC_USB0_AUX_CLK 135 136f99cdbd8SKathiravan T #define GCC_USB0_AUX_CLK_SRC 136 137f99cdbd8SKathiravan T #define GCC_USB0_EUD_AT_CLK 137 138f99cdbd8SKathiravan T #define GCC_USB0_LFPS_CLK 138 139f99cdbd8SKathiravan T #define GCC_USB0_LFPS_CLK_SRC 139 140f99cdbd8SKathiravan T #define GCC_USB0_MASTER_CLK 140 141f99cdbd8SKathiravan T #define GCC_USB0_MASTER_CLK_SRC 141 142f99cdbd8SKathiravan T #define GCC_USB0_MOCK_UTMI_CLK 142 143f99cdbd8SKathiravan T #define GCC_USB0_MOCK_UTMI_CLK_SRC 143 144f99cdbd8SKathiravan T #define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 144 145f99cdbd8SKathiravan T #define GCC_USB0_PHY_CFG_AHB_CLK 145 146f99cdbd8SKathiravan T #define GCC_USB0_PIPE_CLK 146 147f99cdbd8SKathiravan T #define GCC_USB0_SLEEP_CLK 147 148f99cdbd8SKathiravan T #define GCC_WCSS_AHB_CLK_SRC 148 149f99cdbd8SKathiravan T #define GCC_XO_CLK 160 150f99cdbd8SKathiravan T #define GCC_XO_CLK_SRC 161 151f99cdbd8SKathiravan T #define GCC_XO_DIV4_CLK 162 152f99cdbd8SKathiravan T #define GCC_IM_SLEEP_CLK 163 153f99cdbd8SKathiravan T #define GCC_NSSNOC_PCNOC_1_CLK 164 154f99cdbd8SKathiravan T #define GCC_MEM_NOC_AHB_CLK 165 155f99cdbd8SKathiravan T #define GCC_MEM_NOC_APSS_AXI_CLK 166 156f99cdbd8SKathiravan T #define GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC 167 157f99cdbd8SKathiravan T #define GCC_MEM_NOC_QOSGEN_EXTREF_CLK 168 158f99cdbd8SKathiravan T #define GCC_PCIE3X2_PIPE_CLK_SRC 169 159f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_PIPE_CLK_SRC 170 160f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_PIPE_CLK_SRC 171 161f99cdbd8SKathiravan T #define GCC_USB0_PIPE_CLK_SRC 172 162f99cdbd8SKathiravan T 163f99cdbd8SKathiravan T #define GCC_ADSS_BCR 0 164f99cdbd8SKathiravan T #define GCC_ADSS_PWM_CLK_ARES 1 165f99cdbd8SKathiravan T #define GCC_AHB_CLK_ARES 2 166f99cdbd8SKathiravan T #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 3 167f99cdbd8SKathiravan T #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES 4 168f99cdbd8SKathiravan T #define GCC_APSS_AHB_CLK_ARES 5 169f99cdbd8SKathiravan T #define GCC_APSS_AXI_CLK_ARES 6 170f99cdbd8SKathiravan T #define GCC_BLSP1_AHB_CLK_ARES 7 171f99cdbd8SKathiravan T #define GCC_BLSP1_BCR 8 172f99cdbd8SKathiravan T #define GCC_BLSP1_QUP1_BCR 9 173f99cdbd8SKathiravan T #define GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES 10 174f99cdbd8SKathiravan T #define GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES 11 175f99cdbd8SKathiravan T #define GCC_BLSP1_QUP2_BCR 12 176f99cdbd8SKathiravan T #define GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES 13 177f99cdbd8SKathiravan T #define GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES 14 178f99cdbd8SKathiravan T #define GCC_BLSP1_QUP3_BCR 15 179f99cdbd8SKathiravan T #define GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES 16 180f99cdbd8SKathiravan T #define GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES 17 181f99cdbd8SKathiravan T #define GCC_BLSP1_SLEEP_CLK_ARES 18 182f99cdbd8SKathiravan T #define GCC_BLSP1_UART1_APPS_CLK_ARES 19 183f99cdbd8SKathiravan T #define GCC_BLSP1_UART1_BCR 20 184f99cdbd8SKathiravan T #define GCC_BLSP1_UART2_APPS_CLK_ARES 21 185f99cdbd8SKathiravan T #define GCC_BLSP1_UART2_BCR 22 186f99cdbd8SKathiravan T #define GCC_BLSP1_UART3_APPS_CLK_ARES 23 187f99cdbd8SKathiravan T #define GCC_BLSP1_UART3_BCR 24 188f99cdbd8SKathiravan T #define GCC_CE_BCR 25 189f99cdbd8SKathiravan T #define GCC_CMN_BLK_BCR 26 190f99cdbd8SKathiravan T #define GCC_CMN_LDO0_BCR 27 191f99cdbd8SKathiravan T #define GCC_CMN_LDO1_BCR 28 192f99cdbd8SKathiravan T #define GCC_DCC_BCR 29 193f99cdbd8SKathiravan T #define GCC_GP1_CLK_ARES 30 194f99cdbd8SKathiravan T #define GCC_GP2_CLK_ARES 31 195f99cdbd8SKathiravan T #define GCC_LPASS_BCR 32 196f99cdbd8SKathiravan T #define GCC_LPASS_CORE_AXIM_CLK_ARES 33 197f99cdbd8SKathiravan T #define GCC_LPASS_SWAY_CLK_ARES 34 198f99cdbd8SKathiravan T #define GCC_MDIOM_BCR 35 199f99cdbd8SKathiravan T #define GCC_MDIOS_BCR 36 200f99cdbd8SKathiravan T #define GCC_NSS_BCR 37 201f99cdbd8SKathiravan T #define GCC_NSS_TS_CLK_ARES 38 202f99cdbd8SKathiravan T #define GCC_NSSCC_CLK_ARES 39 203f99cdbd8SKathiravan T #define GCC_NSSCFG_CLK_ARES 40 204f99cdbd8SKathiravan T #define GCC_NSSNOC_ATB_CLK_ARES 41 205f99cdbd8SKathiravan T #define GCC_NSSNOC_NSSCC_CLK_ARES 42 206f99cdbd8SKathiravan T #define GCC_NSSNOC_QOSGEN_REF_CLK_ARES 43 207f99cdbd8SKathiravan T #define GCC_NSSNOC_SNOC_1_CLK_ARES 44 208f99cdbd8SKathiravan T #define GCC_NSSNOC_SNOC_CLK_ARES 45 209f99cdbd8SKathiravan T #define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES 46 210f99cdbd8SKathiravan T #define GCC_NSSNOC_XO_DCD_CLK_ARES 47 211f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AHB_CLK_ARES 48 212f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AUX_CLK_ARES 49 213f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_M_CLK_ARES 50 214f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES 51 215f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_S_CLK_ARES 52 216f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_BCR 53 217f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_LINK_DOWN_BCR 54 218f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_PHY_BCR 55 219f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_PHY_PHY_BCR 56 220f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AHB_CLK_ARES 57 221f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AUX_CLK_ARES 58 222f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_M_CLK_ARES 59 223f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES 60 224f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_S_CLK_ARES 61 225f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_BCR 62 226f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_LINK_DOWN_BCR 63 227f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_PHY_BCR 64 228f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_PHY_PHY_BCR 65 229f99cdbd8SKathiravan T #define GCC_PCIE3X1_PHY_AHB_CLK_ARES 66 230f99cdbd8SKathiravan T #define GCC_PCIE3X2_AHB_CLK_ARES 67 231f99cdbd8SKathiravan T #define GCC_PCIE3X2_AUX_CLK_ARES 68 232f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_M_CLK_ARES 69 233f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES 70 234f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_S_CLK_ARES 71 235f99cdbd8SKathiravan T #define GCC_PCIE3X2_BCR 72 236f99cdbd8SKathiravan T #define GCC_PCIE3X2_LINK_DOWN_BCR 73 237f99cdbd8SKathiravan T #define GCC_PCIE3X2_PHY_AHB_CLK_ARES 74 238f99cdbd8SKathiravan T #define GCC_PCIE3X2_PHY_BCR 75 239f99cdbd8SKathiravan T #define GCC_PCIE3X2PHY_PHY_BCR 76 240f99cdbd8SKathiravan T #define GCC_PCNOC_BCR 77 241f99cdbd8SKathiravan T #define GCC_PCNOC_LPASS_CLK_ARES 78 242f99cdbd8SKathiravan T #define GCC_PRNG_AHB_CLK_ARES 79 243f99cdbd8SKathiravan T #define GCC_PRNG_BCR 80 244f99cdbd8SKathiravan T #define GCC_Q6_AHB_CLK_ARES 81 245f99cdbd8SKathiravan T #define GCC_Q6_AHB_S_CLK_ARES 82 246f99cdbd8SKathiravan T #define GCC_Q6_AXIM_CLK_ARES 83 247f99cdbd8SKathiravan T #define GCC_Q6_AXIS_CLK_ARES 84 248f99cdbd8SKathiravan T #define GCC_Q6_TSCTR_1TO2_CLK_ARES 85 249f99cdbd8SKathiravan T #define GCC_Q6SS_ATBM_CLK_ARES 86 250f99cdbd8SKathiravan T #define GCC_Q6SS_PCLKDBG_CLK_ARES 87 251f99cdbd8SKathiravan T #define GCC_Q6SS_TRIG_CLK_ARES 88 252f99cdbd8SKathiravan T #define GCC_QDSS_APB2JTAG_CLK_ARES 89 253f99cdbd8SKathiravan T #define GCC_QDSS_AT_CLK_ARES 90 254f99cdbd8SKathiravan T #define GCC_QDSS_BCR 91 255f99cdbd8SKathiravan T #define GCC_QDSS_CFG_AHB_CLK_ARES 92 256f99cdbd8SKathiravan T #define GCC_QDSS_DAP_AHB_CLK_ARES 93 257f99cdbd8SKathiravan T #define GCC_QDSS_DAP_CLK_ARES 94 258f99cdbd8SKathiravan T #define GCC_QDSS_ETR_USB_CLK_ARES 95 259f99cdbd8SKathiravan T #define GCC_QDSS_EUD_AT_CLK_ARES 96 260f99cdbd8SKathiravan T #define GCC_QDSS_STM_CLK_ARES 97 261f99cdbd8SKathiravan T #define GCC_QDSS_TRACECLKIN_CLK_ARES 98 262f99cdbd8SKathiravan T #define GCC_QDSS_TS_CLK_ARES 99 263f99cdbd8SKathiravan T #define GCC_QDSS_TSCTR_DIV16_CLK_ARES 100 264f99cdbd8SKathiravan T #define GCC_QDSS_TSCTR_DIV2_CLK_ARES 101 265f99cdbd8SKathiravan T #define GCC_QDSS_TSCTR_DIV3_CLK_ARES 102 266f99cdbd8SKathiravan T #define GCC_QDSS_TSCTR_DIV4_CLK_ARES 103 267f99cdbd8SKathiravan T #define GCC_QDSS_TSCTR_DIV8_CLK_ARES 104 268f99cdbd8SKathiravan T #define GCC_QPIC_AHB_CLK_ARES 105 269f99cdbd8SKathiravan T #define GCC_QPIC_CLK_ARES 106 270f99cdbd8SKathiravan T #define GCC_QPIC_BCR 107 271f99cdbd8SKathiravan T #define GCC_QPIC_IO_MACRO_CLK_ARES 108 272f99cdbd8SKathiravan T #define GCC_QPIC_SLEEP_CLK_ARES 109 273f99cdbd8SKathiravan T #define GCC_QUSB2_0_PHY_BCR 110 274f99cdbd8SKathiravan T #define GCC_SDCC1_AHB_CLK_ARES 111 275f99cdbd8SKathiravan T #define GCC_SDCC1_APPS_CLK_ARES 112 276f99cdbd8SKathiravan T #define GCC_SDCC_BCR 113 277f99cdbd8SKathiravan T #define GCC_SNOC_BCR 114 278f99cdbd8SKathiravan T #define GCC_SNOC_LPASS_CFG_CLK_ARES 115 279f99cdbd8SKathiravan T #define GCC_SNOC_NSSNOC_1_CLK_ARES 116 280f99cdbd8SKathiravan T #define GCC_SNOC_NSSNOC_CLK_ARES 117 281f99cdbd8SKathiravan T #define GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES 118 282f99cdbd8SKathiravan T #define GCC_SYS_NOC_WCSS_AHB_CLK_ARES 119 283f99cdbd8SKathiravan T #define GCC_UNIPHY0_AHB_CLK_ARES 120 284f99cdbd8SKathiravan T #define GCC_UNIPHY0_BCR 121 285f99cdbd8SKathiravan T #define GCC_UNIPHY0_SYS_CLK_ARES 122 286f99cdbd8SKathiravan T #define GCC_UNIPHY1_AHB_CLK_ARES 123 287f99cdbd8SKathiravan T #define GCC_UNIPHY1_BCR 124 288f99cdbd8SKathiravan T #define GCC_UNIPHY1_SYS_CLK_ARES 125 289f99cdbd8SKathiravan T #define GCC_USB0_AUX_CLK_ARES 126 290f99cdbd8SKathiravan T #define GCC_USB0_EUD_AT_CLK_ARES 127 291f99cdbd8SKathiravan T #define GCC_USB0_LFPS_CLK_ARES 128 292f99cdbd8SKathiravan T #define GCC_USB0_MASTER_CLK_ARES 129 293f99cdbd8SKathiravan T #define GCC_USB0_MOCK_UTMI_CLK_ARES 130 294f99cdbd8SKathiravan T #define GCC_USB0_PHY_BCR 131 295f99cdbd8SKathiravan T #define GCC_USB0_PHY_CFG_AHB_CLK_ARES 132 296f99cdbd8SKathiravan T #define GCC_USB0_SLEEP_CLK_ARES 133 297f99cdbd8SKathiravan T #define GCC_USB3PHY_0_PHY_BCR 134 298f99cdbd8SKathiravan T #define GCC_USB_BCR 135 299f99cdbd8SKathiravan T #define GCC_WCSS_AXIM_CLK_ARES 136 300f99cdbd8SKathiravan T #define GCC_WCSS_AXIS_CLK_ARES 137 301f99cdbd8SKathiravan T #define GCC_WCSS_BCR 138 302f99cdbd8SKathiravan T #define GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES 139 303f99cdbd8SKathiravan T #define GCC_WCSS_DBG_IFC_APB_CLK_ARES 140 304f99cdbd8SKathiravan T #define GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES 141 305f99cdbd8SKathiravan T #define GCC_WCSS_DBG_IFC_ATB_CLK_ARES 142 306f99cdbd8SKathiravan T #define GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES 143 307f99cdbd8SKathiravan T #define GCC_WCSS_DBG_IFC_NTS_CLK_ARES 144 308f99cdbd8SKathiravan T #define GCC_WCSS_ECAHB_CLK_ARES 145 309f99cdbd8SKathiravan T #define GCC_WCSS_MST_ASYNC_BDG_CLK_ARES 146 310f99cdbd8SKathiravan T #define GCC_WCSS_Q6_BCR 147 311f99cdbd8SKathiravan T #define GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES 148 312f99cdbd8SKathiravan T #define GCC_XO_CLK_ARES 149 313f99cdbd8SKathiravan T #define GCC_XO_DIV4_CLK_ARES 150 314f99cdbd8SKathiravan T #define GCC_Q6SS_DBG_ARES 151 315f99cdbd8SKathiravan T #define GCC_WCSS_DBG_BDG_ARES 152 316f99cdbd8SKathiravan T #define GCC_WCSS_DBG_ARES 153 317f99cdbd8SKathiravan T #define GCC_WCSS_AXI_S_ARES 154 318f99cdbd8SKathiravan T #define GCC_WCSS_AXI_M_ARES 155 319f99cdbd8SKathiravan T #define GCC_WCSSAON_ARES 156 320f99cdbd8SKathiravan T #define GCC_PCIE3X2_PIPE_ARES 157 321f99cdbd8SKathiravan T #define GCC_PCIE3X2_CORE_STICKY_ARES 158 322f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_S_STICKY_ARES 159 323f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_M_STICKY_ARES 160 324f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_PIPE_ARES 161 325f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_CORE_STICKY_ARES 162 326f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_S_STICKY_ARES 163 327f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_M_STICKY_ARES 164 328f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_PIPE_ARES 165 329f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_CORE_STICKY_ARES 166 330f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_S_STICKY_ARES 167 331f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_M_STICKY_ARES 168 332f99cdbd8SKathiravan T #define GCC_IM_SLEEP_CLK_ARES 169 333f99cdbd8SKathiravan T #define GCC_NSSNOC_PCNOC_1_CLK_ARES 170 334f99cdbd8SKathiravan T #define GCC_UNIPHY0_XPCS_ARES 171 335f99cdbd8SKathiravan T #define GCC_UNIPHY1_XPCS_ARES 172 336f99cdbd8SKathiravan T #endif 337