1*c0f1cbf7SLuo Jie /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*c0f1cbf7SLuo Jie /* 3*c0f1cbf7SLuo Jie * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4*c0f1cbf7SLuo Jie */ 5*c0f1cbf7SLuo Jie 6*c0f1cbf7SLuo Jie #ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H 7*c0f1cbf7SLuo Jie #define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H 8*c0f1cbf7SLuo Jie 9*c0f1cbf7SLuo Jie /* CMN PLL core clock. */ 10*c0f1cbf7SLuo Jie #define CMN_PLL_CLK 0 11*c0f1cbf7SLuo Jie 12*c0f1cbf7SLuo Jie /* The output clocks from CMN PLL of IPQ9574. */ 13*c0f1cbf7SLuo Jie #define XO_24MHZ_CLK 1 14*c0f1cbf7SLuo Jie #define SLEEP_32KHZ_CLK 2 15*c0f1cbf7SLuo Jie #define PCS_31P25MHZ_CLK 3 16*c0f1cbf7SLuo Jie #define NSS_1200MHZ_CLK 4 17*c0f1cbf7SLuo Jie #define PPE_353MHZ_CLK 5 18*c0f1cbf7SLuo Jie #define ETH0_50MHZ_CLK 6 19*c0f1cbf7SLuo Jie #define ETH1_50MHZ_CLK 7 20*c0f1cbf7SLuo Jie #define ETH2_50MHZ_CLK 8 21*c0f1cbf7SLuo Jie #define ETH_25MHZ_CLK 9 22*c0f1cbf7SLuo Jie #endif 23