1d0173278SGuenter Roeck /* SPDX-License-Identifier: GPL-2.0+ */ 2456c7301SMike Waychison /* 3456c7301SMike Waychison * nv_tco: TCO timer driver for nVidia chipsets. 4456c7301SMike Waychison * 5456c7301SMike Waychison * (c) Copyright 2005 Google Inc., All Rights Reserved. 6456c7301SMike Waychison * 7456c7301SMike Waychison * Supported Chipsets: 8456c7301SMike Waychison * - MCP51/MCP55 9456c7301SMike Waychison * 10456c7301SMike Waychison * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights 11456c7301SMike Waychison * Reserved. 12*2ab77a34SAlexander A. Klimov * https://www.kernelconcepts.de 13456c7301SMike Waychison * 14456c7301SMike Waychison * Neither kernel concepts nor Nils Faerber admit liability nor provide 15456c7301SMike Waychison * warranty for any of this software. This material is provided 16456c7301SMike Waychison * "AS-IS" and at no charge. 17456c7301SMike Waychison * 18456c7301SMike Waychison * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de> 19456c7301SMike Waychison * developed for 20456c7301SMike Waychison * Jentro AG, Haar/Munich (Germany) 21456c7301SMike Waychison * 22456c7301SMike Waychison * TCO timer driver for NV chipsets 23456c7301SMike Waychison * based on softdog.c by Alan Cox <alan@redhat.com> 24456c7301SMike Waychison */ 25456c7301SMike Waychison 26456c7301SMike Waychison /* 27456c7301SMike Waychison * Some address definitions for the TCO 28456c7301SMike Waychison */ 29456c7301SMike Waychison 30456c7301SMike Waychison #define TCO_RLD(base) ((base) + 0x00) /* TCO Timer Reload and Current Value */ 31456c7301SMike Waychison #define TCO_TMR(base) ((base) + 0x01) /* TCO Timer Initial Value */ 32456c7301SMike Waychison 33456c7301SMike Waychison #define TCO_STS(base) ((base) + 0x04) /* TCO Status Register */ 34456c7301SMike Waychison /* 35456c7301SMike Waychison * TCO Boot Status bit: set on TCO reset, reset by software or standby 36456c7301SMike Waychison * power-good (survives reboots), unfortunately this bit is never 37456c7301SMike Waychison * set. 38456c7301SMike Waychison */ 39456c7301SMike Waychison # define TCO_STS_BOOT_STS (1 << 9) 40456c7301SMike Waychison /* 41456c7301SMike Waychison * first and 2nd timeout status bits, these also survive a warm boot, 42456c7301SMike Waychison * and they work, so we use them. 43456c7301SMike Waychison */ 44456c7301SMike Waychison # define TCO_STS_TCO_INT_STS (1 << 1) 45456c7301SMike Waychison # define TCO_STS_TCO2TO_STS (1 << 10) 46456c7301SMike Waychison # define TCO_STS_RESET (TCO_STS_BOOT_STS | TCO_STS_TCO2TO_STS | \ 47456c7301SMike Waychison TCO_STS_TCO_INT_STS) 48456c7301SMike Waychison 49456c7301SMike Waychison #define TCO_CNT(base) ((base) + 0x08) /* TCO Control Register */ 50456c7301SMike Waychison # define TCO_CNT_TCOHALT (1 << 12) 51456c7301SMike Waychison 52456c7301SMike Waychison #define MCP51_SMBUS_SETUP_B 0xe8 53456c7301SMike Waychison # define MCP51_SMBUS_SETUP_B_TCO_REBOOT (1 << 25) 54456c7301SMike Waychison 55456c7301SMike Waychison /* 56456c7301SMike Waychison * The SMI_EN register is at the base io address + 0x04, 57456c7301SMike Waychison * while TCOBASE is + 0x40. 58456c7301SMike Waychison */ 59456c7301SMike Waychison #define MCP51_SMI_EN(base) ((base) - 0x40 + 0x04) 60456c7301SMike Waychison # define MCP51_SMI_EN_TCO ((1 << 4) | (1 << 5)) 61