1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A66597 UDC 4 * 5 * Copyright (C) 2007-2009 Renesas Solutions Corp. 6 * 7 * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; version 2 of the License. 12 */ 13 14 #ifndef __R8A66597_H__ 15 #define __R8A66597_H__ 16 17 #include <linux/clk.h> 18 #include <linux/usb/r8a66597.h> 19 20 #define R8A66597_MAX_SAMPLING 10 21 22 #define R8A66597_MAX_NUM_PIPE 8 23 #define R8A66597_MAX_NUM_BULK 3 24 #define R8A66597_MAX_NUM_ISOC 2 25 #define R8A66597_MAX_NUM_INT 2 26 27 #define R8A66597_BASE_PIPENUM_BULK 3 28 #define R8A66597_BASE_PIPENUM_ISOC 1 29 #define R8A66597_BASE_PIPENUM_INT 6 30 31 #define R8A66597_BASE_BUFNUM 6 32 #define R8A66597_MAX_BUFNUM 0x4F 33 34 #define is_bulk_pipe(pipenum) \ 35 ((pipenum >= R8A66597_BASE_PIPENUM_BULK) && \ 36 (pipenum < (R8A66597_BASE_PIPENUM_BULK + R8A66597_MAX_NUM_BULK))) 37 #define is_interrupt_pipe(pipenum) \ 38 ((pipenum >= R8A66597_BASE_PIPENUM_INT) && \ 39 (pipenum < (R8A66597_BASE_PIPENUM_INT + R8A66597_MAX_NUM_INT))) 40 #define is_isoc_pipe(pipenum) \ 41 ((pipenum >= R8A66597_BASE_PIPENUM_ISOC) && \ 42 (pipenum < (R8A66597_BASE_PIPENUM_ISOC + R8A66597_MAX_NUM_ISOC))) 43 44 #define r8a66597_is_sudmac(r8a66597) (r8a66597->pdata->sudmac) 45 struct r8a66597_pipe_info { 46 u16 pipe; 47 u16 epnum; 48 u16 maxpacket; 49 u16 type; 50 u16 interval; 51 u16 dir_in; 52 }; 53 54 struct r8a66597_request { 55 struct usb_request req; 56 struct list_head queue; 57 }; 58 59 struct r8a66597_ep { 60 struct usb_ep ep; 61 struct r8a66597 *r8a66597; 62 struct r8a66597_dma *dma; 63 64 struct list_head queue; 65 unsigned busy:1; 66 unsigned wedge:1; 67 unsigned internal_ccpl:1; /* use only control */ 68 69 /* this member can able to after r8a66597_enable */ 70 unsigned use_dma:1; 71 u16 pipenum; 72 u16 type; 73 74 /* register address */ 75 unsigned char fifoaddr; 76 unsigned char fifosel; 77 unsigned char fifoctr; 78 unsigned char pipectr; 79 unsigned char pipetre; 80 unsigned char pipetrn; 81 }; 82 83 struct r8a66597_dma { 84 unsigned used:1; 85 unsigned dir:1; /* 1 = IN(write), 0 = OUT(read) */ 86 }; 87 88 struct r8a66597 { 89 spinlock_t lock; 90 void __iomem *reg; 91 void __iomem *sudmac_reg; 92 93 struct clk *clk; 94 struct r8a66597_platdata *pdata; 95 96 struct usb_gadget gadget; 97 struct usb_gadget_driver *driver; 98 99 struct r8a66597_ep ep[R8A66597_MAX_NUM_PIPE]; 100 struct r8a66597_ep *pipenum2ep[R8A66597_MAX_NUM_PIPE]; 101 struct r8a66597_ep *epaddr2ep[16]; 102 struct r8a66597_dma dma; 103 104 struct timer_list timer; 105 struct usb_request *ep0_req; /* for internal request */ 106 u16 ep0_data; /* for internal request */ 107 u16 old_vbus; 108 u16 scount; 109 u16 old_dvsq; 110 u16 device_status; /* for GET_STATUS */ 111 112 /* pipe config */ 113 unsigned char bulk; 114 unsigned char interrupt; 115 unsigned char isochronous; 116 unsigned char num_dma; 117 118 unsigned irq_sense_low:1; 119 }; 120 121 #define gadget_to_r8a66597(_gadget) \ 122 container_of(_gadget, struct r8a66597, gadget) 123 #define r8a66597_to_gadget(r8a66597) (&r8a66597->gadget) 124 #define r8a66597_to_dev(r8a66597) (r8a66597->gadget.dev.parent) 125 126 static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset) 127 { 128 return ioread16(r8a66597->reg + offset); 129 } 130 131 static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, 132 unsigned long offset, 133 unsigned char *buf, 134 int len) 135 { 136 void __iomem *fifoaddr = r8a66597->reg + offset; 137 unsigned int data = 0; 138 int i; 139 140 if (r8a66597->pdata->on_chip) { 141 /* 32-bit accesses for on_chip controllers */ 142 143 /* aligned buf case */ 144 if (len >= 4 && !((unsigned long)buf & 0x03)) { 145 ioread32_rep(fifoaddr, buf, len / 4); 146 buf += len & ~0x03; 147 len &= 0x03; 148 } 149 150 /* unaligned buf case */ 151 for (i = 0; i < len; i++) { 152 if (!(i & 0x03)) 153 data = ioread32(fifoaddr); 154 155 buf[i] = (data >> ((i & 0x03) * 8)) & 0xff; 156 } 157 } else { 158 /* 16-bit accesses for external controllers */ 159 160 /* aligned buf case */ 161 if (len >= 2 && !((unsigned long)buf & 0x01)) { 162 ioread16_rep(fifoaddr, buf, len / 2); 163 buf += len & ~0x01; 164 len &= 0x01; 165 } 166 167 /* unaligned buf case */ 168 for (i = 0; i < len; i++) { 169 if (!(i & 0x01)) 170 data = ioread16(fifoaddr); 171 172 buf[i] = (data >> ((i & 0x01) * 8)) & 0xff; 173 } 174 } 175 } 176 177 static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, 178 unsigned long offset) 179 { 180 iowrite16(val, r8a66597->reg + offset); 181 } 182 183 static inline void r8a66597_mdfy(struct r8a66597 *r8a66597, 184 u16 val, u16 pat, unsigned long offset) 185 { 186 u16 tmp; 187 tmp = r8a66597_read(r8a66597, offset); 188 tmp = tmp & (~pat); 189 tmp = tmp | val; 190 r8a66597_write(r8a66597, tmp, offset); 191 } 192 193 #define r8a66597_bclr(r8a66597, val, offset) \ 194 r8a66597_mdfy(r8a66597, 0, val, offset) 195 #define r8a66597_bset(r8a66597, val, offset) \ 196 r8a66597_mdfy(r8a66597, val, 0, offset) 197 198 static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, 199 struct r8a66597_ep *ep, 200 unsigned char *buf, 201 int len) 202 { 203 void __iomem *fifoaddr = r8a66597->reg + ep->fifoaddr; 204 int adj = 0; 205 int i; 206 207 if (r8a66597->pdata->on_chip) { 208 /* 32-bit access only if buf is 32-bit aligned */ 209 if (len >= 4 && !((unsigned long)buf & 0x03)) { 210 iowrite32_rep(fifoaddr, buf, len / 4); 211 buf += len & ~0x03; 212 len &= 0x03; 213 } 214 } else { 215 /* 16-bit access only if buf is 16-bit aligned */ 216 if (len >= 2 && !((unsigned long)buf & 0x01)) { 217 iowrite16_rep(fifoaddr, buf, len / 2); 218 buf += len & ~0x01; 219 len &= 0x01; 220 } 221 } 222 223 /* adjust fifo address in the little endian case */ 224 if (!(r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)) { 225 if (r8a66597->pdata->on_chip) 226 adj = 0x03; /* 32-bit wide */ 227 else 228 adj = 0x01; /* 16-bit wide */ 229 } 230 231 if (r8a66597->pdata->wr0_shorted_to_wr1) 232 r8a66597_bclr(r8a66597, MBW_16, ep->fifosel); 233 for (i = 0; i < len; i++) 234 iowrite8(buf[i], fifoaddr + adj - (i & adj)); 235 if (r8a66597->pdata->wr0_shorted_to_wr1) 236 r8a66597_bclr(r8a66597, MBW_16, ep->fifosel); 237 } 238 239 static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata) 240 { 241 u16 clock = 0; 242 243 switch (pdata->xtal) { 244 case R8A66597_PLATDATA_XTAL_12MHZ: 245 clock = XTAL12; 246 break; 247 case R8A66597_PLATDATA_XTAL_24MHZ: 248 clock = XTAL24; 249 break; 250 case R8A66597_PLATDATA_XTAL_48MHZ: 251 clock = XTAL48; 252 break; 253 default: 254 printk(KERN_ERR "r8a66597: platdata clock is wrong.\n"); 255 break; 256 } 257 258 return clock; 259 } 260 261 static inline u32 r8a66597_sudmac_read(struct r8a66597 *r8a66597, 262 unsigned long offset) 263 { 264 return ioread32(r8a66597->sudmac_reg + offset); 265 } 266 267 static inline void r8a66597_sudmac_write(struct r8a66597 *r8a66597, u32 val, 268 unsigned long offset) 269 { 270 iowrite32(val, r8a66597->sudmac_reg + offset); 271 } 272 273 #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2) 274 #define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4) 275 #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4) 276 277 #define enable_irq_ready(r8a66597, pipenum) \ 278 enable_pipe_irq(r8a66597, pipenum, BRDYENB) 279 #define disable_irq_ready(r8a66597, pipenum) \ 280 disable_pipe_irq(r8a66597, pipenum, BRDYENB) 281 #define enable_irq_empty(r8a66597, pipenum) \ 282 enable_pipe_irq(r8a66597, pipenum, BEMPENB) 283 #define disable_irq_empty(r8a66597, pipenum) \ 284 disable_pipe_irq(r8a66597, pipenum, BEMPENB) 285 #define enable_irq_nrdy(r8a66597, pipenum) \ 286 enable_pipe_irq(r8a66597, pipenum, NRDYENB) 287 #define disable_irq_nrdy(r8a66597, pipenum) \ 288 disable_pipe_irq(r8a66597, pipenum, NRDYENB) 289 290 #endif /* __R8A66597_H__ */ 291 292