1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/circ_buf.h> 11 #include <linux/clk.h> 12 #include <linux/console.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dmapool.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/irq.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_dma.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/serial_core.h> 27 #include <linux/slab.h> 28 #include <linux/tty_flip.h> 29 30 /* All registers are 8-bit width */ 31 #define UARTBDH 0x00 32 #define UARTBDL 0x01 33 #define UARTCR1 0x02 34 #define UARTCR2 0x03 35 #define UARTSR1 0x04 36 #define UARTCR3 0x06 37 #define UARTDR 0x07 38 #define UARTCR4 0x0a 39 #define UARTCR5 0x0b 40 #define UARTMODEM 0x0d 41 #define UARTPFIFO 0x10 42 #define UARTCFIFO 0x11 43 #define UARTSFIFO 0x12 44 #define UARTTWFIFO 0x13 45 #define UARTTCFIFO 0x14 46 #define UARTRWFIFO 0x15 47 48 #define UARTBDH_LBKDIE 0x80 49 #define UARTBDH_RXEDGIE 0x40 50 #define UARTBDH_SBR_MASK 0x1f 51 52 #define UARTCR1_LOOPS 0x80 53 #define UARTCR1_RSRC 0x20 54 #define UARTCR1_M 0x10 55 #define UARTCR1_WAKE 0x08 56 #define UARTCR1_ILT 0x04 57 #define UARTCR1_PE 0x02 58 #define UARTCR1_PT 0x01 59 60 #define UARTCR2_TIE 0x80 61 #define UARTCR2_TCIE 0x40 62 #define UARTCR2_RIE 0x20 63 #define UARTCR2_ILIE 0x10 64 #define UARTCR2_TE 0x08 65 #define UARTCR2_RE 0x04 66 #define UARTCR2_RWU 0x02 67 #define UARTCR2_SBK 0x01 68 69 #define UARTSR1_TDRE 0x80 70 #define UARTSR1_TC 0x40 71 #define UARTSR1_RDRF 0x20 72 #define UARTSR1_IDLE 0x10 73 #define UARTSR1_OR 0x08 74 #define UARTSR1_NF 0x04 75 #define UARTSR1_FE 0x02 76 #define UARTSR1_PE 0x01 77 78 #define UARTCR3_R8 0x80 79 #define UARTCR3_T8 0x40 80 #define UARTCR3_TXDIR 0x20 81 #define UARTCR3_TXINV 0x10 82 #define UARTCR3_ORIE 0x08 83 #define UARTCR3_NEIE 0x04 84 #define UARTCR3_FEIE 0x02 85 #define UARTCR3_PEIE 0x01 86 87 #define UARTCR4_MAEN1 0x80 88 #define UARTCR4_MAEN2 0x40 89 #define UARTCR4_M10 0x20 90 #define UARTCR4_BRFA_MASK 0x1f 91 #define UARTCR4_BRFA_OFF 0 92 93 #define UARTCR5_TDMAS 0x80 94 #define UARTCR5_RDMAS 0x20 95 96 #define UARTMODEM_RXRTSE 0x08 97 #define UARTMODEM_TXRTSPOL 0x04 98 #define UARTMODEM_TXRTSE 0x02 99 #define UARTMODEM_TXCTSE 0x01 100 101 #define UARTPFIFO_TXFE 0x80 102 #define UARTPFIFO_FIFOSIZE_MASK 0x7 103 #define UARTPFIFO_TXSIZE_OFF 4 104 #define UARTPFIFO_RXFE 0x08 105 #define UARTPFIFO_RXSIZE_OFF 0 106 107 #define UARTCFIFO_TXFLUSH 0x80 108 #define UARTCFIFO_RXFLUSH 0x40 109 #define UARTCFIFO_RXOFE 0x04 110 #define UARTCFIFO_TXOFE 0x02 111 #define UARTCFIFO_RXUFE 0x01 112 113 #define UARTSFIFO_TXEMPT 0x80 114 #define UARTSFIFO_RXEMPT 0x40 115 #define UARTSFIFO_RXOF 0x04 116 #define UARTSFIFO_TXOF 0x02 117 #define UARTSFIFO_RXUF 0x01 118 119 /* 32-bit global registers only for i.MX7ULP/i.MX8x 120 * Used to reset all internal logic and registers, except the Global Register. 121 */ 122 #define UART_GLOBAL 0x8 123 124 /* 32-bit register definition */ 125 #define UARTBAUD 0x00 126 #define UARTSTAT 0x04 127 #define UARTCTRL 0x08 128 #define UARTDATA 0x0C 129 #define UARTMATCH 0x10 130 #define UARTMODIR 0x14 131 #define UARTFIFO 0x18 132 #define UARTWATER 0x1c 133 134 #define UARTBAUD_MAEN1 0x80000000 135 #define UARTBAUD_MAEN2 0x40000000 136 #define UARTBAUD_M10 0x20000000 137 #define UARTBAUD_TDMAE 0x00800000 138 #define UARTBAUD_RDMAE 0x00200000 139 #define UARTBAUD_MATCFG 0x00400000 140 #define UARTBAUD_BOTHEDGE 0x00020000 141 #define UARTBAUD_RESYNCDIS 0x00010000 142 #define UARTBAUD_LBKDIE 0x00008000 143 #define UARTBAUD_RXEDGIE 0x00004000 144 #define UARTBAUD_SBNS 0x00002000 145 #define UARTBAUD_SBR 0x00000000 146 #define UARTBAUD_SBR_MASK 0x1fff 147 #define UARTBAUD_OSR_MASK 0x1f 148 #define UARTBAUD_OSR_SHIFT 24 149 150 #define UARTSTAT_LBKDIF 0x80000000 151 #define UARTSTAT_RXEDGIF 0x40000000 152 #define UARTSTAT_MSBF 0x20000000 153 #define UARTSTAT_RXINV 0x10000000 154 #define UARTSTAT_RWUID 0x08000000 155 #define UARTSTAT_BRK13 0x04000000 156 #define UARTSTAT_LBKDE 0x02000000 157 #define UARTSTAT_RAF 0x01000000 158 #define UARTSTAT_TDRE 0x00800000 159 #define UARTSTAT_TC 0x00400000 160 #define UARTSTAT_RDRF 0x00200000 161 #define UARTSTAT_IDLE 0x00100000 162 #define UARTSTAT_OR 0x00080000 163 #define UARTSTAT_NF 0x00040000 164 #define UARTSTAT_FE 0x00020000 165 #define UARTSTAT_PE 0x00010000 166 #define UARTSTAT_MA1F 0x00008000 167 #define UARTSTAT_M21F 0x00004000 168 169 #define UARTCTRL_R8T9 0x80000000 170 #define UARTCTRL_R9T8 0x40000000 171 #define UARTCTRL_TXDIR 0x20000000 172 #define UARTCTRL_TXINV 0x10000000 173 #define UARTCTRL_ORIE 0x08000000 174 #define UARTCTRL_NEIE 0x04000000 175 #define UARTCTRL_FEIE 0x02000000 176 #define UARTCTRL_PEIE 0x01000000 177 #define UARTCTRL_TIE 0x00800000 178 #define UARTCTRL_TCIE 0x00400000 179 #define UARTCTRL_RIE 0x00200000 180 #define UARTCTRL_ILIE 0x00100000 181 #define UARTCTRL_TE 0x00080000 182 #define UARTCTRL_RE 0x00040000 183 #define UARTCTRL_RWU 0x00020000 184 #define UARTCTRL_SBK 0x00010000 185 #define UARTCTRL_MA1IE 0x00008000 186 #define UARTCTRL_MA2IE 0x00004000 187 #define UARTCTRL_M7 0x00000800 188 #define UARTCTRL_IDLECFG GENMASK(10, 8) 189 #define UARTCTRL_LOOPS 0x00000080 190 #define UARTCTRL_DOZEEN 0x00000040 191 #define UARTCTRL_RSRC 0x00000020 192 #define UARTCTRL_M 0x00000010 193 #define UARTCTRL_WAKE 0x00000008 194 #define UARTCTRL_ILT 0x00000004 195 #define UARTCTRL_PE 0x00000002 196 #define UARTCTRL_PT 0x00000001 197 198 #define UARTDATA_NOISY 0x00008000 199 #define UARTDATA_PARITYE 0x00004000 200 #define UARTDATA_FRETSC 0x00002000 201 #define UARTDATA_RXEMPT 0x00001000 202 #define UARTDATA_IDLINE 0x00000800 203 #define UARTDATA_MASK 0x3ff 204 205 #define UARTMODIR_IREN 0x00020000 206 #define UARTMODIR_RTSWATER GENMASK(10, 8) 207 #define UARTMODIR_TXCTSSRC 0x00000020 208 #define UARTMODIR_TXCTSC 0x00000010 209 #define UARTMODIR_RXRTSE 0x00000008 210 #define UARTMODIR_TXRTSPOL 0x00000004 211 #define UARTMODIR_TXRTSE 0x00000002 212 #define UARTMODIR_TXCTSE 0x00000001 213 214 #define UARTFIFO_TXEMPT 0x00800000 215 #define UARTFIFO_RXEMPT 0x00400000 216 #define UARTFIFO_TXOF 0x00020000 217 #define UARTFIFO_RXUF 0x00010000 218 #define UARTFIFO_TXFLUSH 0x00008000 219 #define UARTFIFO_RXFLUSH 0x00004000 220 #define UARTFIFO_RXIDEN GENMASK(12, 10) 221 #define UARTFIFO_TXOFE 0x00000200 222 #define UARTFIFO_RXUFE 0x00000100 223 #define UARTFIFO_TXFE 0x00000080 224 #define UARTFIFO_FIFOSIZE_MASK 0x7 225 #define UARTFIFO_TXSIZE_OFF 4 226 #define UARTFIFO_RXFE 0x00000008 227 #define UARTFIFO_RXSIZE_OFF 0 228 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) 229 230 #define UARTWATER_COUNT_MASK 0xff 231 #define UARTWATER_TXCNT_OFF 8 232 #define UARTWATER_RXCNT_OFF 24 233 #define UARTWATER_WATER_MASK 0xff 234 #define UARTWATER_TXWATER_OFF 0 235 #define UARTWATER_RXWATER_OFF 16 236 237 #define UART_GLOBAL_RST 0x2 238 #define GLOBAL_RST_MIN_US 20 239 #define GLOBAL_RST_MAX_US 40 240 241 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 242 #define DMA_RX_TIMEOUT (10) 243 #define DMA_RX_IDLE_CHARS 8 244 #define UART_AUTOSUSPEND_TIMEOUT 3000 245 246 #define DRIVER_NAME "fsl-lpuart" 247 #define DEV_NAME "ttyLP" 248 #define UART_NR 12 249 250 /* IMX lpuart has four extra unused regs located at the beginning */ 251 #define IMX_REG_OFF 0x10 252 253 enum lpuart_type { 254 VF610_LPUART, 255 LS1021A_LPUART, 256 LS1028A_LPUART, 257 IMX7ULP_LPUART, 258 IMX8ULP_LPUART, 259 IMX8QXP_LPUART, 260 IMXRT1050_LPUART, 261 }; 262 263 struct lpuart_port { 264 struct uart_port port; 265 enum lpuart_type devtype; 266 struct clk *ipg_clk; 267 struct clk *baud_clk; 268 unsigned int txfifo_size; 269 unsigned int rxfifo_size; 270 271 u8 rx_watermark; 272 bool lpuart_dma_tx_use; 273 bool lpuart_dma_rx_use; 274 struct dma_chan *dma_tx_chan; 275 struct dma_chan *dma_rx_chan; 276 struct dma_async_tx_descriptor *dma_tx_desc; 277 struct dma_async_tx_descriptor *dma_rx_desc; 278 dma_cookie_t dma_tx_cookie; 279 dma_cookie_t dma_rx_cookie; 280 unsigned int dma_tx_bytes; 281 unsigned int dma_rx_bytes; 282 bool dma_tx_in_progress; 283 unsigned int dma_rx_timeout; 284 struct timer_list lpuart_timer; 285 struct scatterlist rx_sgl, tx_sgl[2]; 286 struct circ_buf rx_ring; 287 int rx_dma_rng_buf_len; 288 int last_residue; 289 unsigned int dma_tx_nents; 290 wait_queue_head_t dma_wait; 291 bool is_cs7; /* Set to true when character size is 7 */ 292 /* and the parity is enabled */ 293 bool dma_idle_int; 294 }; 295 296 struct lpuart_soc_data { 297 enum lpuart_type devtype; 298 char iotype; 299 u8 reg_off; 300 u8 rx_watermark; 301 }; 302 303 static const struct lpuart_soc_data vf_data = { 304 .devtype = VF610_LPUART, 305 .iotype = UPIO_MEM, 306 .rx_watermark = 1, 307 }; 308 309 static const struct lpuart_soc_data ls1021a_data = { 310 .devtype = LS1021A_LPUART, 311 .iotype = UPIO_MEM32BE, 312 .rx_watermark = 1, 313 }; 314 315 static const struct lpuart_soc_data ls1028a_data = { 316 .devtype = LS1028A_LPUART, 317 .iotype = UPIO_MEM32, 318 .rx_watermark = 0, 319 }; 320 321 static struct lpuart_soc_data imx7ulp_data = { 322 .devtype = IMX7ULP_LPUART, 323 .iotype = UPIO_MEM32, 324 .reg_off = IMX_REG_OFF, 325 .rx_watermark = 1, 326 }; 327 328 static struct lpuart_soc_data imx8ulp_data = { 329 .devtype = IMX8ULP_LPUART, 330 .iotype = UPIO_MEM32, 331 .reg_off = IMX_REG_OFF, 332 .rx_watermark = 3, 333 }; 334 335 static struct lpuart_soc_data imx8qxp_data = { 336 .devtype = IMX8QXP_LPUART, 337 .iotype = UPIO_MEM32, 338 .reg_off = IMX_REG_OFF, 339 .rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */ 340 }; 341 static struct lpuart_soc_data imxrt1050_data = { 342 .devtype = IMXRT1050_LPUART, 343 .iotype = UPIO_MEM32, 344 .reg_off = IMX_REG_OFF, 345 .rx_watermark = 1, 346 }; 347 348 static const struct of_device_id lpuart_dt_ids[] = { 349 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 350 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, }, 351 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, }, 352 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, 353 { .compatible = "fsl,imx8ulp-lpuart", .data = &imx8ulp_data, }, 354 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, 355 { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data}, 356 { /* sentinel */ } 357 }; 358 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 359 360 /* Forward declare this for the dma callbacks*/ 361 static void lpuart_dma_tx_complete(void *arg); 362 363 static inline bool is_layerscape_lpuart(struct lpuart_port *sport) 364 { 365 return (sport->devtype == LS1021A_LPUART || 366 sport->devtype == LS1028A_LPUART); 367 } 368 369 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport) 370 { 371 return sport->devtype == IMX7ULP_LPUART; 372 } 373 374 static inline bool is_imx8ulp_lpuart(struct lpuart_port *sport) 375 { 376 return sport->devtype == IMX8ULP_LPUART; 377 } 378 379 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) 380 { 381 return sport->devtype == IMX8QXP_LPUART; 382 } 383 384 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 385 { 386 switch (port->iotype) { 387 case UPIO_MEM32: 388 return readl(port->membase + off); 389 case UPIO_MEM32BE: 390 return ioread32be(port->membase + off); 391 default: 392 return 0; 393 } 394 } 395 396 static inline void lpuart32_write(struct uart_port *port, u32 val, 397 u32 off) 398 { 399 switch (port->iotype) { 400 case UPIO_MEM32: 401 writel(val, port->membase + off); 402 break; 403 case UPIO_MEM32BE: 404 iowrite32be(val, port->membase + off); 405 break; 406 } 407 } 408 409 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) 410 { 411 int ret = 0; 412 413 if (is_en) { 414 ret = clk_prepare_enable(sport->ipg_clk); 415 if (ret) 416 return ret; 417 418 ret = clk_prepare_enable(sport->baud_clk); 419 if (ret) { 420 clk_disable_unprepare(sport->ipg_clk); 421 return ret; 422 } 423 } else { 424 clk_disable_unprepare(sport->baud_clk); 425 clk_disable_unprepare(sport->ipg_clk); 426 } 427 428 return 0; 429 } 430 431 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) 432 { 433 if (is_imx8qxp_lpuart(sport)) 434 return clk_get_rate(sport->baud_clk); 435 436 return clk_get_rate(sport->ipg_clk); 437 } 438 439 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) 440 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) 441 442 static void lpuart_stop_tx(struct uart_port *port) 443 { 444 u8 cr2; 445 446 cr2 = readb(port->membase + UARTCR2); 447 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE); 448 writeb(cr2, port->membase + UARTCR2); 449 } 450 451 static void lpuart32_stop_tx(struct uart_port *port) 452 { 453 u32 ctrl; 454 455 ctrl = lpuart32_read(port, UARTCTRL); 456 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 457 lpuart32_write(port, ctrl, UARTCTRL); 458 } 459 460 static void lpuart_stop_rx(struct uart_port *port) 461 { 462 u8 cr2; 463 464 cr2 = readb(port->membase + UARTCR2); 465 writeb(cr2 & ~UARTCR2_RE, port->membase + UARTCR2); 466 } 467 468 static void lpuart32_stop_rx(struct uart_port *port) 469 { 470 u32 ctrl; 471 472 ctrl = lpuart32_read(port, UARTCTRL); 473 lpuart32_write(port, ctrl & ~UARTCTRL_RE, UARTCTRL); 474 } 475 476 static void lpuart_dma_tx(struct lpuart_port *sport) 477 { 478 struct tty_port *tport = &sport->port.state->port; 479 struct scatterlist *sgl = sport->tx_sgl; 480 struct device *dev = sport->port.dev; 481 struct dma_chan *chan = sport->dma_tx_chan; 482 int ret; 483 484 if (sport->dma_tx_in_progress) 485 return; 486 487 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl)); 488 sport->dma_tx_bytes = kfifo_len(&tport->xmit_fifo); 489 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl, 490 ARRAY_SIZE(sport->tx_sgl), sport->dma_tx_bytes); 491 492 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, 493 DMA_TO_DEVICE); 494 if (!ret) { 495 dev_err(dev, "DMA mapping error for TX.\n"); 496 return; 497 } 498 499 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, 500 ret, DMA_MEM_TO_DEV, 501 DMA_PREP_INTERRUPT); 502 if (!sport->dma_tx_desc) { 503 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 504 DMA_TO_DEVICE); 505 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 506 return; 507 } 508 509 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 510 sport->dma_tx_desc->callback_param = sport; 511 sport->dma_tx_in_progress = true; 512 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 513 dma_async_issue_pending(chan); 514 } 515 516 static bool lpuart_stopped_or_empty(struct uart_port *port) 517 { 518 return kfifo_is_empty(&port->state->port.xmit_fifo) || 519 uart_tx_stopped(port); 520 } 521 522 static void lpuart_dma_tx_complete(void *arg) 523 { 524 struct lpuart_port *sport = arg; 525 struct scatterlist *sgl = &sport->tx_sgl[0]; 526 struct tty_port *tport = &sport->port.state->port; 527 struct dma_chan *chan = sport->dma_tx_chan; 528 unsigned long flags; 529 530 uart_port_lock_irqsave(&sport->port, &flags); 531 if (!sport->dma_tx_in_progress) { 532 uart_port_unlock_irqrestore(&sport->port, flags); 533 return; 534 } 535 536 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 537 DMA_TO_DEVICE); 538 539 uart_xmit_advance(&sport->port, sport->dma_tx_bytes); 540 sport->dma_tx_in_progress = false; 541 uart_port_unlock_irqrestore(&sport->port, flags); 542 543 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 544 uart_write_wakeup(&sport->port); 545 546 if (waitqueue_active(&sport->dma_wait)) { 547 wake_up(&sport->dma_wait); 548 return; 549 } 550 551 uart_port_lock_irqsave(&sport->port, &flags); 552 553 if (!lpuart_stopped_or_empty(&sport->port)) 554 lpuart_dma_tx(sport); 555 556 uart_port_unlock_irqrestore(&sport->port, flags); 557 } 558 559 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) 560 { 561 switch (sport->port.iotype) { 562 case UPIO_MEM32: 563 return sport->port.mapbase + UARTDATA; 564 case UPIO_MEM32BE: 565 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; 566 } 567 return sport->port.mapbase + UARTDR; 568 } 569 570 static int lpuart_dma_tx_request(struct uart_port *port) 571 { 572 struct lpuart_port *sport = container_of(port, 573 struct lpuart_port, port); 574 struct dma_slave_config dma_tx_sconfig = {}; 575 int ret; 576 577 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); 578 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 579 dma_tx_sconfig.dst_maxburst = 1; 580 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 581 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 582 583 if (ret) { 584 dev_err(port->dev, 585 "DMA slave config failed, err = %d\n", ret); 586 return ret; 587 } 588 589 return 0; 590 } 591 592 static bool lpuart_is_32(struct lpuart_port *sport) 593 { 594 return sport->port.iotype == UPIO_MEM32 || 595 sport->port.iotype == UPIO_MEM32BE; 596 } 597 598 static void lpuart_flush_buffer(struct uart_port *port) 599 { 600 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 601 struct dma_chan *chan = sport->dma_tx_chan; 602 u32 fifo; 603 604 if (sport->lpuart_dma_tx_use) { 605 if (sport->dma_tx_in_progress) { 606 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], 607 sport->dma_tx_nents, DMA_TO_DEVICE); 608 sport->dma_tx_in_progress = false; 609 } 610 dmaengine_terminate_async(chan); 611 } 612 613 if (lpuart_is_32(sport)) { 614 fifo = lpuart32_read(port, UARTFIFO); 615 fifo |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 616 lpuart32_write(port, fifo, UARTFIFO); 617 } else { 618 fifo = readb(port->membase + UARTCFIFO); 619 fifo |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; 620 writeb(fifo, port->membase + UARTCFIFO); 621 } 622 } 623 624 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset, 625 u8 bit) 626 { 627 while (!(readb(port->membase + offset) & bit)) 628 cpu_relax(); 629 } 630 631 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset, 632 u32 bit) 633 { 634 while (!(lpuart32_read(port, offset) & bit)) 635 cpu_relax(); 636 } 637 638 #if defined(CONFIG_CONSOLE_POLL) 639 640 static int lpuart_poll_init(struct uart_port *port) 641 { 642 unsigned long flags; 643 u8 fifo; 644 645 port->fifosize = 0; 646 647 uart_port_lock_irqsave(port, &flags); 648 /* Disable Rx & Tx */ 649 writeb(0, port->membase + UARTCR2); 650 651 fifo = readb(port->membase + UARTPFIFO); 652 /* Enable Rx and Tx FIFO */ 653 writeb(fifo | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 654 port->membase + UARTPFIFO); 655 656 /* flush Tx and Rx FIFO */ 657 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 658 port->membase + UARTCFIFO); 659 660 /* explicitly clear RDRF */ 661 if (readb(port->membase + UARTSR1) & UARTSR1_RDRF) { 662 readb(port->membase + UARTDR); 663 writeb(UARTSFIFO_RXUF, port->membase + UARTSFIFO); 664 } 665 666 writeb(0, port->membase + UARTTWFIFO); 667 writeb(1, port->membase + UARTRWFIFO); 668 669 /* Enable Rx and Tx */ 670 writeb(UARTCR2_RE | UARTCR2_TE, port->membase + UARTCR2); 671 uart_port_unlock_irqrestore(port, flags); 672 673 return 0; 674 } 675 676 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 677 { 678 /* drain */ 679 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 680 writeb(c, port->membase + UARTDR); 681 } 682 683 static int lpuart_poll_get_char(struct uart_port *port) 684 { 685 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 686 return NO_POLL_CHAR; 687 688 return readb(port->membase + UARTDR); 689 } 690 691 static int lpuart32_poll_init(struct uart_port *port) 692 { 693 unsigned long flags; 694 u32 fifo; 695 696 port->fifosize = 0; 697 698 uart_port_lock_irqsave(port, &flags); 699 700 /* Disable Rx & Tx */ 701 lpuart32_write(port, 0, UARTCTRL); 702 703 fifo = lpuart32_read(port, UARTFIFO); 704 705 /* Enable Rx and Tx FIFO */ 706 lpuart32_write(port, fifo | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); 707 708 /* flush Tx and Rx FIFO */ 709 lpuart32_write(port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); 710 711 /* explicitly clear RDRF */ 712 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_RDRF) { 713 lpuart32_read(port, UARTDATA); 714 lpuart32_write(port, UARTFIFO_RXUF, UARTFIFO); 715 } 716 717 /* Enable Rx and Tx */ 718 lpuart32_write(port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); 719 uart_port_unlock_irqrestore(port, flags); 720 721 return 0; 722 } 723 724 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 725 { 726 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 727 lpuart32_write(port, c, UARTDATA); 728 } 729 730 static int lpuart32_poll_get_char(struct uart_port *port) 731 { 732 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF)) 733 return NO_POLL_CHAR; 734 735 return lpuart32_read(port, UARTDATA); 736 } 737 #endif 738 739 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 740 { 741 struct uart_port *port = &sport->port; 742 u8 ch; 743 744 uart_port_tx(port, ch, 745 readb(port->membase + UARTTCFIFO) < sport->txfifo_size, 746 writeb(ch, port->membase + UARTDR)); 747 } 748 749 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 750 { 751 struct tty_port *tport = &sport->port.state->port; 752 u32 txcnt; 753 unsigned char c; 754 755 if (sport->port.x_char) { 756 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 757 sport->port.icount.tx++; 758 sport->port.x_char = 0; 759 return; 760 } 761 762 if (lpuart_stopped_or_empty(&sport->port)) { 763 lpuart32_stop_tx(&sport->port); 764 return; 765 } 766 767 txcnt = lpuart32_read(&sport->port, UARTWATER); 768 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 769 txcnt &= UARTWATER_COUNT_MASK; 770 while (txcnt < sport->txfifo_size && 771 uart_fifo_get(&sport->port, &c)) { 772 lpuart32_write(&sport->port, c, UARTDATA); 773 txcnt = lpuart32_read(&sport->port, UARTWATER); 774 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 775 txcnt &= UARTWATER_COUNT_MASK; 776 } 777 778 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 779 uart_write_wakeup(&sport->port); 780 781 if (kfifo_is_empty(&tport->xmit_fifo)) 782 lpuart32_stop_tx(&sport->port); 783 } 784 785 static void lpuart_start_tx(struct uart_port *port) 786 { 787 struct lpuart_port *sport = container_of(port, 788 struct lpuart_port, port); 789 u8 cr2; 790 791 cr2 = readb(port->membase + UARTCR2); 792 writeb(cr2 | UARTCR2_TIE, port->membase + UARTCR2); 793 794 if (sport->lpuart_dma_tx_use) { 795 if (!lpuart_stopped_or_empty(port)) 796 lpuart_dma_tx(sport); 797 } else { 798 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 799 lpuart_transmit_buffer(sport); 800 } 801 } 802 803 static void lpuart32_start_tx(struct uart_port *port) 804 { 805 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 806 u32 ctrl; 807 808 if (sport->lpuart_dma_tx_use) { 809 if (!lpuart_stopped_or_empty(port)) 810 lpuart_dma_tx(sport); 811 } else { 812 ctrl = lpuart32_read(port, UARTCTRL); 813 lpuart32_write(port, ctrl | UARTCTRL_TIE, UARTCTRL); 814 815 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 816 lpuart32_transmit_buffer(sport); 817 } 818 } 819 820 static void 821 lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) 822 { 823 switch (state) { 824 case UART_PM_STATE_OFF: 825 pm_runtime_mark_last_busy(port->dev); 826 pm_runtime_put_autosuspend(port->dev); 827 break; 828 default: 829 pm_runtime_get_sync(port->dev); 830 break; 831 } 832 } 833 834 /* return TIOCSER_TEMT when transmitter is not busy */ 835 static unsigned int lpuart_tx_empty(struct uart_port *port) 836 { 837 struct lpuart_port *sport = container_of(port, 838 struct lpuart_port, port); 839 u8 sr1 = readb(port->membase + UARTSR1); 840 u8 sfifo = readb(port->membase + UARTSFIFO); 841 842 if (sport->dma_tx_in_progress) 843 return 0; 844 845 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 846 return TIOCSER_TEMT; 847 848 return 0; 849 } 850 851 static unsigned int lpuart32_tx_empty(struct uart_port *port) 852 { 853 struct lpuart_port *sport = container_of(port, 854 struct lpuart_port, port); 855 u32 stat = lpuart32_read(port, UARTSTAT); 856 u32 sfifo = lpuart32_read(port, UARTFIFO); 857 u32 ctrl = lpuart32_read(port, UARTCTRL); 858 859 if (sport->dma_tx_in_progress) 860 return 0; 861 862 /* 863 * LPUART Transmission Complete Flag may never be set while queuing a break 864 * character, so avoid checking for transmission complete when UARTCTRL_SBK 865 * is asserted. 866 */ 867 if ((stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) || ctrl & UARTCTRL_SBK) 868 return TIOCSER_TEMT; 869 870 return 0; 871 } 872 873 static void lpuart_txint(struct lpuart_port *sport) 874 { 875 uart_port_lock(&sport->port); 876 lpuart_transmit_buffer(sport); 877 uart_port_unlock(&sport->port); 878 } 879 880 static void lpuart_rxint(struct lpuart_port *sport) 881 { 882 unsigned int flg, ignored = 0, overrun = 0; 883 struct tty_port *port = &sport->port.state->port; 884 u8 rx, sr; 885 886 uart_port_lock(&sport->port); 887 888 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 889 flg = TTY_NORMAL; 890 sport->port.icount.rx++; 891 /* 892 * to clear the FE, OR, NF, FE, PE flags, 893 * read SR1 then read DR 894 */ 895 sr = readb(sport->port.membase + UARTSR1); 896 rx = readb(sport->port.membase + UARTDR); 897 898 if (uart_prepare_sysrq_char(&sport->port, rx)) 899 continue; 900 901 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 902 if (sr & UARTSR1_PE) 903 sport->port.icount.parity++; 904 else if (sr & UARTSR1_FE) 905 sport->port.icount.frame++; 906 907 if (sr & UARTSR1_OR) 908 overrun++; 909 910 if (sr & sport->port.ignore_status_mask) { 911 if (++ignored > 100) 912 goto out; 913 continue; 914 } 915 916 sr &= sport->port.read_status_mask; 917 918 if (sr & UARTSR1_PE) 919 flg = TTY_PARITY; 920 else if (sr & UARTSR1_FE) 921 flg = TTY_FRAME; 922 923 if (sr & UARTSR1_OR) 924 flg = TTY_OVERRUN; 925 926 sport->port.sysrq = 0; 927 } 928 929 if (tty_insert_flip_char(port, rx, flg) == 0) 930 sport->port.icount.buf_overrun++; 931 } 932 933 out: 934 if (overrun) { 935 sport->port.icount.overrun += overrun; 936 937 /* 938 * Overruns cause FIFO pointers to become missaligned. 939 * Flushing the receive FIFO reinitializes the pointers. 940 */ 941 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 942 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); 943 } 944 945 uart_unlock_and_check_sysrq(&sport->port); 946 947 tty_flip_buffer_push(port); 948 } 949 950 static void lpuart32_txint(struct lpuart_port *sport) 951 { 952 uart_port_lock(&sport->port); 953 lpuart32_transmit_buffer(sport); 954 uart_port_unlock(&sport->port); 955 } 956 957 static void lpuart32_rxint(struct lpuart_port *sport) 958 { 959 unsigned int flg, ignored = 0; 960 struct tty_port *port = &sport->port.state->port; 961 u32 rx, sr; 962 bool is_break; 963 964 uart_port_lock(&sport->port); 965 966 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 967 flg = TTY_NORMAL; 968 sport->port.icount.rx++; 969 /* 970 * to clear the FE, OR, NF, FE, PE flags, 971 * read STAT then read DATA reg 972 */ 973 sr = lpuart32_read(&sport->port, UARTSTAT); 974 rx = lpuart32_read(&sport->port, UARTDATA); 975 rx &= UARTDATA_MASK; 976 977 /* 978 * The LPUART can't distinguish between a break and a framing error, 979 * thus we assume it is a break if the received data is zero. 980 */ 981 is_break = (sr & UARTSTAT_FE) && !rx; 982 983 if (is_break && uart_handle_break(&sport->port)) 984 continue; 985 986 if (uart_prepare_sysrq_char(&sport->port, rx)) 987 continue; 988 989 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 990 if (sr & UARTSTAT_PE) { 991 sport->port.icount.parity++; 992 } else if (sr & UARTSTAT_FE) { 993 if (is_break) 994 sport->port.icount.brk++; 995 else 996 sport->port.icount.frame++; 997 } 998 999 if (sr & UARTSTAT_OR) 1000 sport->port.icount.overrun++; 1001 1002 if (sr & sport->port.ignore_status_mask) { 1003 if (++ignored > 100) 1004 goto out; 1005 continue; 1006 } 1007 1008 sr &= sport->port.read_status_mask; 1009 1010 if (sr & UARTSTAT_PE) { 1011 flg = TTY_PARITY; 1012 } else if (sr & UARTSTAT_FE) { 1013 if (is_break) 1014 flg = TTY_BREAK; 1015 else 1016 flg = TTY_FRAME; 1017 } 1018 1019 if (sr & UARTSTAT_OR) 1020 flg = TTY_OVERRUN; 1021 } 1022 1023 if (sport->is_cs7) 1024 rx &= 0x7F; 1025 1026 if (tty_insert_flip_char(port, rx, flg) == 0) 1027 sport->port.icount.buf_overrun++; 1028 } 1029 1030 out: 1031 uart_unlock_and_check_sysrq(&sport->port); 1032 1033 tty_flip_buffer_push(port); 1034 } 1035 1036 static irqreturn_t lpuart_int(int irq, void *dev_id) 1037 { 1038 struct lpuart_port *sport = dev_id; 1039 u8 sts; 1040 1041 sts = readb(sport->port.membase + UARTSR1); 1042 1043 /* SysRq, using dma, check for linebreak by framing err. */ 1044 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { 1045 readb(sport->port.membase + UARTDR); 1046 uart_handle_break(&sport->port); 1047 /* linebreak produces some garbage, removing it */ 1048 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 1049 return IRQ_HANDLED; 1050 } 1051 1052 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) 1053 lpuart_rxint(sport); 1054 1055 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) 1056 lpuart_txint(sport); 1057 1058 return IRQ_HANDLED; 1059 } 1060 1061 static inline void lpuart_handle_sysrq_chars(struct uart_port *port, 1062 unsigned char *p, int count) 1063 { 1064 while (count--) { 1065 if (*p && uart_handle_sysrq_char(port, *p)) 1066 return; 1067 p++; 1068 } 1069 } 1070 1071 static void lpuart_handle_sysrq(struct lpuart_port *sport) 1072 { 1073 struct circ_buf *ring = &sport->rx_ring; 1074 int count; 1075 1076 if (ring->head < ring->tail) { 1077 count = sport->rx_sgl.length - ring->tail; 1078 lpuart_handle_sysrq_chars(&sport->port, 1079 ring->buf + ring->tail, count); 1080 ring->tail = 0; 1081 } 1082 1083 if (ring->head > ring->tail) { 1084 count = ring->head - ring->tail; 1085 lpuart_handle_sysrq_chars(&sport->port, 1086 ring->buf + ring->tail, count); 1087 ring->tail = ring->head; 1088 } 1089 } 1090 1091 static int lpuart_tty_insert_flip_string(struct tty_port *port, 1092 unsigned char *chars, size_t size, bool is_cs7) 1093 { 1094 int i; 1095 1096 if (is_cs7) 1097 for (i = 0; i < size; i++) 1098 chars[i] &= 0x7F; 1099 return tty_insert_flip_string(port, chars, size); 1100 } 1101 1102 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 1103 { 1104 struct tty_port *port = &sport->port.state->port; 1105 struct dma_tx_state state; 1106 enum dma_status dmastat; 1107 struct dma_chan *chan = sport->dma_rx_chan; 1108 struct circ_buf *ring = &sport->rx_ring; 1109 unsigned long flags; 1110 int count, copied; 1111 1112 if (lpuart_is_32(sport)) { 1113 u32 sr = lpuart32_read(&sport->port, UARTSTAT); 1114 1115 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { 1116 /* Clear the error flags */ 1117 lpuart32_write(&sport->port, sr, UARTSTAT); 1118 1119 if (sr & UARTSTAT_PE) 1120 sport->port.icount.parity++; 1121 else if (sr & UARTSTAT_FE) 1122 sport->port.icount.frame++; 1123 } 1124 } else { 1125 u8 sr = readb(sport->port.membase + UARTSR1); 1126 1127 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 1128 u8 cr2; 1129 1130 /* Disable receiver during this operation... */ 1131 cr2 = readb(sport->port.membase + UARTCR2); 1132 cr2 &= ~UARTCR2_RE; 1133 writeb(cr2, sport->port.membase + UARTCR2); 1134 1135 /* Read DR to clear the error flags */ 1136 readb(sport->port.membase + UARTDR); 1137 1138 if (sr & UARTSR1_PE) 1139 sport->port.icount.parity++; 1140 else if (sr & UARTSR1_FE) 1141 sport->port.icount.frame++; 1142 /* 1143 * At this point parity/framing error is 1144 * cleared However, since the DMA already read 1145 * the data register and we had to read it 1146 * again after reading the status register to 1147 * properly clear the flags, the FIFO actually 1148 * underflowed... This requires a clearing of 1149 * the FIFO... 1150 */ 1151 if (readb(sport->port.membase + UARTSFIFO) & 1152 UARTSFIFO_RXUF) { 1153 writeb(UARTSFIFO_RXUF, 1154 sport->port.membase + UARTSFIFO); 1155 writeb(UARTCFIFO_RXFLUSH, 1156 sport->port.membase + UARTCFIFO); 1157 } 1158 1159 cr2 |= UARTCR2_RE; 1160 writeb(cr2, sport->port.membase + UARTCR2); 1161 } 1162 } 1163 1164 async_tx_ack(sport->dma_rx_desc); 1165 1166 uart_port_lock_irqsave(&sport->port, &flags); 1167 1168 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1169 if (dmastat == DMA_ERROR) { 1170 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1171 uart_port_unlock_irqrestore(&sport->port, flags); 1172 return; 1173 } 1174 1175 /* CPU claims ownership of RX DMA buffer */ 1176 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, 1177 DMA_FROM_DEVICE); 1178 1179 /* 1180 * ring->head points to the end of data already written by the DMA. 1181 * ring->tail points to the beginning of data to be read by the 1182 * framework. 1183 * The current transfer size should not be larger than the dma buffer 1184 * length. 1185 */ 1186 ring->head = sport->rx_sgl.length - state.residue; 1187 BUG_ON(ring->head > sport->rx_sgl.length); 1188 1189 /* 1190 * Silent handling of keys pressed in the sysrq timeframe 1191 */ 1192 if (sport->port.sysrq) { 1193 lpuart_handle_sysrq(sport); 1194 goto exit; 1195 } 1196 1197 /* 1198 * At this point ring->head may point to the first byte right after the 1199 * last byte of the dma buffer: 1200 * 0 <= ring->head <= sport->rx_sgl.length 1201 * 1202 * However ring->tail must always points inside the dma buffer: 1203 * 0 <= ring->tail <= sport->rx_sgl.length - 1 1204 * 1205 * Since we use a ring buffer, we have to handle the case 1206 * where head is lower than tail. In such a case, we first read from 1207 * tail to the end of the buffer then reset tail. 1208 */ 1209 if (ring->head < ring->tail) { 1210 count = sport->rx_sgl.length - ring->tail; 1211 1212 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, 1213 count, sport->is_cs7); 1214 if (copied != count) 1215 sport->port.icount.buf_overrun++; 1216 ring->tail = 0; 1217 sport->port.icount.rx += copied; 1218 } 1219 1220 /* Finally we read data from tail to head */ 1221 if (ring->tail < ring->head) { 1222 count = ring->head - ring->tail; 1223 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, 1224 count, sport->is_cs7); 1225 if (copied != count) 1226 sport->port.icount.buf_overrun++; 1227 /* Wrap ring->head if needed */ 1228 if (ring->head >= sport->rx_sgl.length) 1229 ring->head = 0; 1230 ring->tail = ring->head; 1231 sport->port.icount.rx += copied; 1232 } 1233 1234 sport->last_residue = state.residue; 1235 1236 exit: 1237 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, 1238 DMA_FROM_DEVICE); 1239 1240 uart_port_unlock_irqrestore(&sport->port, flags); 1241 1242 tty_flip_buffer_push(port); 1243 if (!sport->dma_idle_int) 1244 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 1245 } 1246 1247 static void lpuart_dma_rx_complete(void *arg) 1248 { 1249 struct lpuart_port *sport = arg; 1250 1251 lpuart_copy_rx_to_tty(sport); 1252 } 1253 1254 static void lpuart32_dma_idleint(struct lpuart_port *sport) 1255 { 1256 enum dma_status dmastat; 1257 struct dma_chan *chan = sport->dma_rx_chan; 1258 struct circ_buf *ring = &sport->rx_ring; 1259 struct dma_tx_state state; 1260 int count = 0; 1261 1262 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1263 if (dmastat == DMA_ERROR) { 1264 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1265 return; 1266 } 1267 1268 ring->head = sport->rx_sgl.length - state.residue; 1269 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); 1270 1271 /* Check if new data received before copying */ 1272 if (count) 1273 lpuart_copy_rx_to_tty(sport); 1274 } 1275 1276 static irqreturn_t lpuart32_int(int irq, void *dev_id) 1277 { 1278 struct lpuart_port *sport = dev_id; 1279 u32 sts, rxcount; 1280 1281 sts = lpuart32_read(&sport->port, UARTSTAT); 1282 rxcount = lpuart32_read(&sport->port, UARTWATER); 1283 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 1284 1285 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) 1286 lpuart32_rxint(sport); 1287 1288 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) 1289 lpuart32_txint(sport); 1290 1291 if ((sts & UARTSTAT_IDLE) && sport->lpuart_dma_rx_use && sport->dma_idle_int) 1292 lpuart32_dma_idleint(sport); 1293 1294 lpuart32_write(&sport->port, sts, UARTSTAT); 1295 return IRQ_HANDLED; 1296 } 1297 1298 /* 1299 * Timer function to simulate the hardware EOP (End Of Package) event. 1300 * The timer callback is to check for new RX data and copy to TTY buffer. 1301 * If no new data are received since last interval, the EOP condition is 1302 * met, complete the DMA transfer by copying the data. Otherwise, just 1303 * restart timer. 1304 */ 1305 static void lpuart_timer_func(struct timer_list *t) 1306 { 1307 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); 1308 enum dma_status dmastat; 1309 struct dma_chan *chan = sport->dma_rx_chan; 1310 struct circ_buf *ring = &sport->rx_ring; 1311 struct dma_tx_state state; 1312 unsigned long flags; 1313 int count; 1314 1315 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1316 if (dmastat == DMA_ERROR) { 1317 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1318 return; 1319 } 1320 1321 ring->head = sport->rx_sgl.length - state.residue; 1322 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); 1323 1324 /* Check if new data received before copying */ 1325 if ((count != 0) && (sport->last_residue == state.residue)) 1326 lpuart_copy_rx_to_tty(sport); 1327 else 1328 mod_timer(&sport->lpuart_timer, 1329 jiffies + sport->dma_rx_timeout); 1330 1331 if (uart_port_trylock_irqsave(&sport->port, &flags)) { 1332 sport->last_residue = state.residue; 1333 uart_port_unlock_irqrestore(&sport->port, flags); 1334 } 1335 } 1336 1337 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 1338 { 1339 struct dma_slave_config dma_rx_sconfig = {}; 1340 struct circ_buf *ring = &sport->rx_ring; 1341 int ret, nent; 1342 struct tty_port *port = &sport->port.state->port; 1343 struct tty_struct *tty = port->tty; 1344 struct ktermios *termios = &tty->termios; 1345 struct dma_chan *chan = sport->dma_rx_chan; 1346 unsigned int bits = tty_get_frame_size(termios->c_cflag); 1347 unsigned int baud = tty_get_baud_rate(tty); 1348 1349 /* 1350 * Calculate length of one DMA buffer size to keep latency below 1351 * 10ms at any baud rate. 1352 */ 1353 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1354 sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len)); 1355 sport->rx_dma_rng_buf_len = max_t(int, 1356 sport->rxfifo_size * 2, 1357 sport->rx_dma_rng_buf_len); 1358 /* 1359 * Keep this condition check in case rxfifo_size is unavailable 1360 * for some SoCs. 1361 */ 1362 if (sport->rx_dma_rng_buf_len < 16) 1363 sport->rx_dma_rng_buf_len = 16; 1364 1365 sport->last_residue = 0; 1366 sport->dma_rx_timeout = max(nsecs_to_jiffies( 1367 sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL); 1368 1369 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1370 if (!ring->buf) 1371 return -ENOMEM; 1372 1373 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1374 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, 1375 DMA_FROM_DEVICE); 1376 1377 if (!nent) { 1378 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1379 return -EINVAL; 1380 } 1381 1382 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); 1383 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1384 dma_rx_sconfig.src_maxburst = 1; 1385 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1386 ret = dmaengine_slave_config(chan, &dma_rx_sconfig); 1387 1388 if (ret < 0) { 1389 dev_err(sport->port.dev, 1390 "DMA Rx slave config failed, err = %d\n", ret); 1391 return ret; 1392 } 1393 1394 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, 1395 sg_dma_address(&sport->rx_sgl), 1396 sport->rx_sgl.length, 1397 sport->rx_sgl.length / 2, 1398 DMA_DEV_TO_MEM, 1399 DMA_PREP_INTERRUPT); 1400 if (!sport->dma_rx_desc) { 1401 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1402 return -EFAULT; 1403 } 1404 1405 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1406 sport->dma_rx_desc->callback_param = sport; 1407 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1408 dma_async_issue_pending(chan); 1409 1410 if (lpuart_is_32(sport)) { 1411 u32 baud = lpuart32_read(&sport->port, UARTBAUD); 1412 1413 lpuart32_write(&sport->port, baud | UARTBAUD_RDMAE, UARTBAUD); 1414 1415 if (sport->dma_idle_int) { 1416 u32 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1417 1418 lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL); 1419 } 1420 } else { 1421 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1422 sport->port.membase + UARTCR5); 1423 } 1424 1425 return 0; 1426 } 1427 1428 static void lpuart_dma_rx_free(struct uart_port *port) 1429 { 1430 struct lpuart_port *sport = container_of(port, 1431 struct lpuart_port, port); 1432 struct dma_chan *chan = sport->dma_rx_chan; 1433 1434 dmaengine_terminate_sync(chan); 1435 if (!sport->dma_idle_int) 1436 timer_delete_sync(&sport->lpuart_timer); 1437 1438 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1439 kfree(sport->rx_ring.buf); 1440 sport->rx_ring.tail = 0; 1441 sport->rx_ring.head = 0; 1442 sport->dma_rx_desc = NULL; 1443 sport->dma_rx_cookie = -EINVAL; 1444 } 1445 1446 static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios, 1447 struct serial_rs485 *rs485) 1448 { 1449 u8 modem = readb(port->membase + UARTMODEM) & 1450 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1451 writeb(modem, port->membase + UARTMODEM); 1452 1453 if (rs485->flags & SER_RS485_ENABLED) { 1454 /* Enable auto RS-485 RTS mode */ 1455 modem |= UARTMODEM_TXRTSE; 1456 1457 /* 1458 * The hardware defaults to RTS logic HIGH while transfer. 1459 * Switch polarity in case RTS shall be logic HIGH 1460 * after transfer. 1461 * Note: UART is assumed to be active high. 1462 */ 1463 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1464 modem |= UARTMODEM_TXRTSPOL; 1465 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1466 modem &= ~UARTMODEM_TXRTSPOL; 1467 } 1468 1469 writeb(modem, port->membase + UARTMODEM); 1470 return 0; 1471 } 1472 1473 static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios, 1474 struct serial_rs485 *rs485) 1475 { 1476 u32 modem = lpuart32_read(port, UARTMODIR) 1477 & ~(UARTMODIR_TXRTSPOL | UARTMODIR_TXRTSE); 1478 u32 ctrl; 1479 1480 /* TXRTSE and TXRTSPOL only can be changed when transmitter is disabled. */ 1481 ctrl = lpuart32_read(port, UARTCTRL); 1482 if (ctrl & UARTCTRL_TE) { 1483 /* wait for the transmit engine to complete */ 1484 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TC); 1485 lpuart32_write(port, ctrl & ~UARTCTRL_TE, UARTCTRL); 1486 1487 while (lpuart32_read(port, UARTCTRL) & UARTCTRL_TE) 1488 cpu_relax(); 1489 } 1490 1491 lpuart32_write(port, modem, UARTMODIR); 1492 1493 if (rs485->flags & SER_RS485_ENABLED) { 1494 /* Enable auto RS-485 RTS mode */ 1495 modem |= UARTMODIR_TXRTSE; 1496 1497 /* 1498 * The hardware defaults to RTS logic HIGH while transfer. 1499 * Switch polarity in case RTS shall be logic HIGH 1500 * after transfer. 1501 * Note: UART is assumed to be active high. 1502 */ 1503 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1504 modem |= UARTMODIR_TXRTSPOL; 1505 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1506 modem &= ~UARTMODIR_TXRTSPOL; 1507 } 1508 1509 lpuart32_write(port, modem, UARTMODIR); 1510 1511 if (ctrl & UARTCTRL_TE) 1512 lpuart32_write(port, ctrl, UARTCTRL); 1513 1514 return 0; 1515 } 1516 1517 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1518 { 1519 unsigned int mctrl = 0; 1520 u8 cr1; 1521 1522 cr1 = readb(port->membase + UARTCR1); 1523 if (cr1 & UARTCR1_LOOPS) 1524 mctrl |= TIOCM_LOOP; 1525 1526 return mctrl; 1527 } 1528 1529 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1530 { 1531 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 1532 u32 ctrl; 1533 1534 ctrl = lpuart32_read(port, UARTCTRL); 1535 if (ctrl & UARTCTRL_LOOPS) 1536 mctrl |= TIOCM_LOOP; 1537 1538 return mctrl; 1539 } 1540 1541 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1542 { 1543 u8 cr1; 1544 1545 cr1 = readb(port->membase + UARTCR1); 1546 1547 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1548 cr1 &= ~(UARTCR1_LOOPS | UARTCR1_RSRC); 1549 if (mctrl & TIOCM_LOOP) 1550 cr1 |= UARTCR1_LOOPS; 1551 1552 writeb(cr1, port->membase + UARTCR1); 1553 } 1554 1555 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1556 { 1557 u32 ctrl; 1558 1559 ctrl = lpuart32_read(port, UARTCTRL); 1560 1561 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1562 ctrl &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC); 1563 if (mctrl & TIOCM_LOOP) 1564 ctrl |= UARTCTRL_LOOPS; 1565 1566 lpuart32_write(port, ctrl, UARTCTRL); 1567 } 1568 1569 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1570 { 1571 u8 cr2; 1572 1573 cr2 = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1574 1575 if (break_state != 0) 1576 cr2 |= UARTCR2_SBK; 1577 1578 writeb(cr2, port->membase + UARTCR2); 1579 } 1580 1581 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1582 { 1583 u32 ctrl; 1584 1585 ctrl = lpuart32_read(port, UARTCTRL); 1586 1587 /* 1588 * LPUART IP now has two known bugs, one is CTS has higher priority than the 1589 * break signal, which causes the break signal sending through UARTCTRL_SBK 1590 * may impacted by the CTS input if the HW flow control is enabled. It 1591 * exists on all platforms we support in this driver. 1592 * Another bug is i.MX8QM LPUART may have an additional break character 1593 * being sent after SBK was cleared. 1594 * To avoid above two bugs, we use Transmit Data Inversion function to send 1595 * the break signal instead of UARTCTRL_SBK. 1596 */ 1597 if (break_state != 0) { 1598 /* 1599 * Disable the transmitter to prevent any data from being sent out 1600 * during break, then invert the TX line to send break. 1601 */ 1602 ctrl &= ~UARTCTRL_TE; 1603 lpuart32_write(port, ctrl, UARTCTRL); 1604 ctrl |= UARTCTRL_TXINV; 1605 lpuart32_write(port, ctrl, UARTCTRL); 1606 } else { 1607 /* Disable the TXINV to turn off break and re-enable transmitter. */ 1608 ctrl &= ~UARTCTRL_TXINV; 1609 lpuart32_write(port, ctrl, UARTCTRL); 1610 ctrl |= UARTCTRL_TE; 1611 lpuart32_write(port, ctrl, UARTCTRL); 1612 } 1613 } 1614 1615 static void lpuart_setup_watermark(struct lpuart_port *sport) 1616 { 1617 u8 fifo, cr2, cr2_saved; 1618 1619 cr2 = readb(sport->port.membase + UARTCR2); 1620 cr2_saved = cr2; 1621 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1622 UARTCR2_RIE | UARTCR2_RE); 1623 writeb(cr2, sport->port.membase + UARTCR2); 1624 1625 fifo = readb(sport->port.membase + UARTPFIFO); 1626 writeb(fifo | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1627 sport->port.membase + UARTPFIFO); 1628 1629 /* flush Tx and Rx FIFO */ 1630 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1631 sport->port.membase + UARTCFIFO); 1632 1633 /* explicitly clear RDRF */ 1634 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1635 readb(sport->port.membase + UARTDR); 1636 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1637 } 1638 1639 if (uart_console(&sport->port)) 1640 sport->rx_watermark = 1; 1641 writeb(0, sport->port.membase + UARTTWFIFO); 1642 writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO); 1643 1644 /* Restore cr2 */ 1645 writeb(cr2_saved, sport->port.membase + UARTCR2); 1646 } 1647 1648 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) 1649 { 1650 u8 cr2; 1651 1652 lpuart_setup_watermark(sport); 1653 1654 cr2 = readb(sport->port.membase + UARTCR2); 1655 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; 1656 writeb(cr2, sport->port.membase + UARTCR2); 1657 } 1658 1659 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1660 { 1661 u32 val, ctrl, ctrl_saved; 1662 1663 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1664 ctrl_saved = ctrl; 1665 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1666 UARTCTRL_RIE | UARTCTRL_RE | UARTCTRL_ILIE); 1667 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1668 1669 /* enable FIFO mode */ 1670 val = lpuart32_read(&sport->port, UARTFIFO); 1671 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1672 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1673 val |= FIELD_PREP(UARTFIFO_RXIDEN, 0x3); 1674 lpuart32_write(&sport->port, val, UARTFIFO); 1675 1676 /* set the watermark */ 1677 if (uart_console(&sport->port)) 1678 sport->rx_watermark = 1; 1679 val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) | 1680 (0x0 << UARTWATER_TXWATER_OFF); 1681 lpuart32_write(&sport->port, val, UARTWATER); 1682 1683 /* set RTS watermark */ 1684 if (!uart_console(&sport->port)) { 1685 val = lpuart32_read(&sport->port, UARTMODIR); 1686 val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1); 1687 lpuart32_write(&sport->port, val, UARTMODIR); 1688 } 1689 1690 /* Restore cr2 */ 1691 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1692 } 1693 1694 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) 1695 { 1696 u32 ctrl; 1697 1698 lpuart32_setup_watermark(sport); 1699 1700 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1701 ctrl |= UARTCTRL_RE | UARTCTRL_TE; 1702 ctrl |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7); 1703 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1704 } 1705 1706 static void rx_dma_timer_init(struct lpuart_port *sport) 1707 { 1708 if (sport->dma_idle_int) 1709 return; 1710 1711 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); 1712 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1713 add_timer(&sport->lpuart_timer); 1714 } 1715 1716 static void lpuart_request_dma(struct lpuart_port *sport) 1717 { 1718 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); 1719 if (IS_ERR(sport->dma_tx_chan)) { 1720 dev_dbg_once(sport->port.dev, 1721 "DMA tx channel request failed, operating without tx DMA (%ld)\n", 1722 PTR_ERR(sport->dma_tx_chan)); 1723 sport->dma_tx_chan = NULL; 1724 } 1725 1726 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); 1727 if (IS_ERR(sport->dma_rx_chan)) { 1728 dev_dbg_once(sport->port.dev, 1729 "DMA rx channel request failed, operating without rx DMA (%ld)\n", 1730 PTR_ERR(sport->dma_rx_chan)); 1731 sport->dma_rx_chan = NULL; 1732 } 1733 } 1734 1735 static void lpuart_tx_dma_startup(struct lpuart_port *sport) 1736 { 1737 u32 uartbaud; 1738 int ret; 1739 1740 if (uart_console(&sport->port)) 1741 goto err; 1742 1743 if (!sport->dma_tx_chan) 1744 goto err; 1745 1746 ret = lpuart_dma_tx_request(&sport->port); 1747 if (ret) 1748 goto err; 1749 1750 init_waitqueue_head(&sport->dma_wait); 1751 sport->lpuart_dma_tx_use = true; 1752 if (lpuart_is_32(sport)) { 1753 uartbaud = lpuart32_read(&sport->port, UARTBAUD); 1754 lpuart32_write(&sport->port, 1755 uartbaud | UARTBAUD_TDMAE, UARTBAUD); 1756 } else { 1757 writeb(readb(sport->port.membase + UARTCR5) | 1758 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 1759 } 1760 1761 return; 1762 1763 err: 1764 sport->lpuart_dma_tx_use = false; 1765 } 1766 1767 static void lpuart_rx_dma_startup(struct lpuart_port *sport) 1768 { 1769 int ret; 1770 u8 cr3; 1771 1772 if (uart_console(&sport->port)) 1773 goto err; 1774 1775 if (!sport->dma_rx_chan) 1776 goto err; 1777 1778 /* set default Rx DMA timeout */ 1779 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1780 1781 ret = lpuart_start_rx_dma(sport); 1782 if (ret) 1783 goto err; 1784 1785 if (!sport->dma_rx_timeout) 1786 sport->dma_rx_timeout = 1; 1787 1788 sport->lpuart_dma_rx_use = true; 1789 rx_dma_timer_init(sport); 1790 1791 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { 1792 cr3 = readb(sport->port.membase + UARTCR3); 1793 cr3 |= UARTCR3_FEIE; 1794 writeb(cr3, sport->port.membase + UARTCR3); 1795 } 1796 1797 return; 1798 1799 err: 1800 sport->lpuart_dma_rx_use = false; 1801 } 1802 1803 static void lpuart_hw_setup(struct lpuart_port *sport) 1804 { 1805 unsigned long flags; 1806 1807 uart_port_lock_irqsave(&sport->port, &flags); 1808 1809 lpuart_setup_watermark_enable(sport); 1810 1811 lpuart_rx_dma_startup(sport); 1812 lpuart_tx_dma_startup(sport); 1813 1814 uart_port_unlock_irqrestore(&sport->port, flags); 1815 } 1816 1817 static int lpuart_startup(struct uart_port *port) 1818 { 1819 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1820 u8 fifo; 1821 1822 /* determine FIFO size and enable FIFO mode */ 1823 fifo = readb(port->membase + UARTPFIFO); 1824 1825 sport->txfifo_size = UARTFIFO_DEPTH((fifo >> UARTPFIFO_TXSIZE_OFF) & 1826 UARTPFIFO_FIFOSIZE_MASK); 1827 port->fifosize = sport->txfifo_size; 1828 1829 sport->rxfifo_size = UARTFIFO_DEPTH((fifo >> UARTPFIFO_RXSIZE_OFF) & 1830 UARTPFIFO_FIFOSIZE_MASK); 1831 1832 lpuart_request_dma(sport); 1833 lpuart_hw_setup(sport); 1834 1835 return 0; 1836 } 1837 1838 static void lpuart32_hw_disable(struct lpuart_port *sport) 1839 { 1840 u32 ctrl; 1841 1842 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1843 ctrl &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE | 1844 UARTCTRL_TIE | UARTCTRL_TE); 1845 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1846 } 1847 1848 static void lpuart32_configure(struct lpuart_port *sport) 1849 { 1850 u32 ctrl; 1851 1852 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1853 if (!sport->lpuart_dma_rx_use) 1854 ctrl |= UARTCTRL_RIE | UARTCTRL_ILIE; 1855 if (!sport->lpuart_dma_tx_use) 1856 ctrl |= UARTCTRL_TIE; 1857 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1858 } 1859 1860 static void lpuart32_hw_setup(struct lpuart_port *sport) 1861 { 1862 unsigned long flags; 1863 1864 uart_port_lock_irqsave(&sport->port, &flags); 1865 1866 lpuart32_hw_disable(sport); 1867 1868 lpuart_rx_dma_startup(sport); 1869 lpuart_tx_dma_startup(sport); 1870 1871 lpuart32_setup_watermark_enable(sport); 1872 lpuart32_configure(sport); 1873 1874 uart_port_unlock_irqrestore(&sport->port, flags); 1875 } 1876 1877 static int lpuart32_startup(struct uart_port *port) 1878 { 1879 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1880 u32 fifo; 1881 1882 /* determine FIFO size */ 1883 fifo = lpuart32_read(port, UARTFIFO); 1884 1885 sport->txfifo_size = UARTFIFO_DEPTH((fifo >> UARTFIFO_TXSIZE_OFF) & 1886 UARTFIFO_FIFOSIZE_MASK); 1887 port->fifosize = sport->txfifo_size; 1888 1889 sport->rxfifo_size = UARTFIFO_DEPTH((fifo >> UARTFIFO_RXSIZE_OFF) & 1890 UARTFIFO_FIFOSIZE_MASK); 1891 1892 /* 1893 * The LS1021A and LS1028A have a fixed FIFO depth of 16 words. 1894 * Although they support the RX/TXSIZE fields, their encoding is 1895 * different. Eg the reference manual states 0b101 is 16 words. 1896 */ 1897 if (is_layerscape_lpuart(sport)) { 1898 sport->rxfifo_size = 16; 1899 sport->txfifo_size = 16; 1900 port->fifosize = sport->txfifo_size; 1901 } 1902 1903 lpuart_request_dma(sport); 1904 lpuart32_hw_setup(sport); 1905 1906 return 0; 1907 } 1908 1909 static void lpuart_dma_shutdown(struct lpuart_port *sport) 1910 { 1911 if (sport->lpuart_dma_rx_use) { 1912 lpuart_dma_rx_free(&sport->port); 1913 sport->lpuart_dma_rx_use = false; 1914 } 1915 1916 if (sport->lpuart_dma_tx_use) { 1917 if (wait_event_interruptible_timeout(sport->dma_wait, 1918 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { 1919 sport->dma_tx_in_progress = false; 1920 dmaengine_terminate_sync(sport->dma_tx_chan); 1921 } 1922 sport->lpuart_dma_tx_use = false; 1923 } 1924 1925 if (sport->dma_tx_chan) 1926 dma_release_channel(sport->dma_tx_chan); 1927 if (sport->dma_rx_chan) 1928 dma_release_channel(sport->dma_rx_chan); 1929 } 1930 1931 static void lpuart_shutdown(struct uart_port *port) 1932 { 1933 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1934 u8 cr2; 1935 unsigned long flags; 1936 1937 uart_port_lock_irqsave(port, &flags); 1938 1939 /* disable Rx/Tx and interrupts */ 1940 cr2 = readb(port->membase + UARTCR2); 1941 cr2 &= ~(UARTCR2_TE | UARTCR2_RE | 1942 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1943 writeb(cr2, port->membase + UARTCR2); 1944 1945 uart_port_unlock_irqrestore(port, flags); 1946 1947 lpuart_dma_shutdown(sport); 1948 } 1949 1950 static void lpuart32_shutdown(struct uart_port *port) 1951 { 1952 struct lpuart_port *sport = 1953 container_of(port, struct lpuart_port, port); 1954 u32 temp; 1955 unsigned long flags; 1956 1957 uart_port_lock_irqsave(port, &flags); 1958 1959 /* clear status */ 1960 temp = lpuart32_read(port, UARTSTAT); 1961 lpuart32_write(port, temp, UARTSTAT); 1962 1963 /* disable Rx/Tx DMA */ 1964 temp = lpuart32_read(port, UARTBAUD); 1965 temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); 1966 lpuart32_write(port, temp, UARTBAUD); 1967 1968 /* disable Rx/Tx and interrupts and break condition */ 1969 temp = lpuart32_read(port, UARTCTRL); 1970 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_ILIE | 1971 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK); 1972 lpuart32_write(port, temp, UARTCTRL); 1973 1974 /* flush Rx/Tx FIFO */ 1975 temp = lpuart32_read(port, UARTFIFO); 1976 temp |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1977 lpuart32_write(port, temp, UARTFIFO); 1978 1979 uart_port_unlock_irqrestore(port, flags); 1980 1981 lpuart_dma_shutdown(sport); 1982 } 1983 1984 static void 1985 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1986 const struct ktermios *old) 1987 { 1988 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1989 unsigned long flags; 1990 u8 cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1991 unsigned int baud; 1992 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1993 unsigned int sbr, brfa; 1994 1995 cr1 = old_cr1 = readb(port->membase + UARTCR1); 1996 old_cr2 = readb(port->membase + UARTCR2); 1997 cr3 = readb(port->membase + UARTCR3); 1998 cr4 = readb(port->membase + UARTCR4); 1999 bdh = readb(port->membase + UARTBDH); 2000 modem = readb(port->membase + UARTMODEM); 2001 /* 2002 * only support CS8 and CS7, and for CS7 must enable PE. 2003 * supported mode: 2004 * - (7,e/o,1) 2005 * - (8,n,1) 2006 * - (8,m/s,1) 2007 * - (8,e/o,1) 2008 */ 2009 while ((termios->c_cflag & CSIZE) != CS8 && 2010 (termios->c_cflag & CSIZE) != CS7) { 2011 termios->c_cflag &= ~CSIZE; 2012 termios->c_cflag |= old_csize; 2013 old_csize = CS8; 2014 } 2015 2016 if ((termios->c_cflag & CSIZE) == CS8 || 2017 (termios->c_cflag & CSIZE) == CS7) 2018 cr1 = old_cr1 & ~UARTCR1_M; 2019 2020 if (termios->c_cflag & CMSPAR) { 2021 if ((termios->c_cflag & CSIZE) != CS8) { 2022 termios->c_cflag &= ~CSIZE; 2023 termios->c_cflag |= CS8; 2024 } 2025 cr1 |= UARTCR1_M; 2026 } 2027 2028 /* 2029 * When auto RS-485 RTS mode is enabled, 2030 * hardware flow control need to be disabled. 2031 */ 2032 if (port->rs485.flags & SER_RS485_ENABLED) 2033 termios->c_cflag &= ~CRTSCTS; 2034 2035 if (termios->c_cflag & CRTSCTS) 2036 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE; 2037 else 2038 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 2039 2040 termios->c_cflag &= ~CSTOPB; 2041 2042 /* parity must be enabled when CS7 to match 8-bits format */ 2043 if ((termios->c_cflag & CSIZE) == CS7) 2044 termios->c_cflag |= PARENB; 2045 2046 if (termios->c_cflag & PARENB) { 2047 if (termios->c_cflag & CMSPAR) { 2048 cr1 &= ~UARTCR1_PE; 2049 if (termios->c_cflag & PARODD) 2050 cr3 |= UARTCR3_T8; 2051 else 2052 cr3 &= ~UARTCR3_T8; 2053 } else { 2054 cr1 |= UARTCR1_PE; 2055 if ((termios->c_cflag & CSIZE) == CS8) 2056 cr1 |= UARTCR1_M; 2057 if (termios->c_cflag & PARODD) 2058 cr1 |= UARTCR1_PT; 2059 else 2060 cr1 &= ~UARTCR1_PT; 2061 } 2062 } else { 2063 cr1 &= ~UARTCR1_PE; 2064 } 2065 2066 /* ask the core to calculate the divisor */ 2067 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 2068 2069 /* 2070 * Need to update the Ring buffer length according to the selected 2071 * baud rate and restart Rx DMA path. 2072 * 2073 * Since timer function acqures port->lock, need to stop before 2074 * acquring same lock because otherwise timer_delete_sync() can deadlock. 2075 */ 2076 if (old && sport->lpuart_dma_rx_use) 2077 lpuart_dma_rx_free(port); 2078 2079 uart_port_lock_irqsave(port, &flags); 2080 2081 port->read_status_mask = 0; 2082 if (termios->c_iflag & INPCK) 2083 port->read_status_mask |= UARTSR1_FE | UARTSR1_PE; 2084 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2085 port->read_status_mask |= UARTSR1_FE; 2086 2087 /* characters to ignore */ 2088 port->ignore_status_mask = 0; 2089 if (termios->c_iflag & IGNPAR) 2090 port->ignore_status_mask |= UARTSR1_PE; 2091 if (termios->c_iflag & IGNBRK) { 2092 port->ignore_status_mask |= UARTSR1_FE; 2093 /* 2094 * if we're ignoring parity and break indicators, 2095 * ignore overruns too (for real raw support). 2096 */ 2097 if (termios->c_iflag & IGNPAR) 2098 port->ignore_status_mask |= UARTSR1_OR; 2099 } 2100 2101 /* update the per-port timeout */ 2102 uart_update_timeout(port, termios->c_cflag, baud); 2103 2104 /* wait transmit engin complete */ 2105 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TC); 2106 2107 /* disable transmit and receive */ 2108 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 2109 port->membase + UARTCR2); 2110 2111 sbr = port->uartclk / (16 * baud); 2112 brfa = ((port->uartclk - (16 * sbr * baud)) * 2) / baud; 2113 bdh &= ~UARTBDH_SBR_MASK; 2114 bdh |= (sbr >> 8) & 0x1F; 2115 cr4 &= ~UARTCR4_BRFA_MASK; 2116 brfa &= UARTCR4_BRFA_MASK; 2117 writeb(cr4 | brfa, port->membase + UARTCR4); 2118 writeb(bdh, port->membase + UARTBDH); 2119 writeb(sbr & 0xFF, port->membase + UARTBDL); 2120 writeb(cr3, port->membase + UARTCR3); 2121 writeb(cr1, port->membase + UARTCR1); 2122 writeb(modem, port->membase + UARTMODEM); 2123 2124 /* restore control register */ 2125 writeb(old_cr2, port->membase + UARTCR2); 2126 2127 if (old && sport->lpuart_dma_rx_use) { 2128 if (!lpuart_start_rx_dma(sport)) 2129 rx_dma_timer_init(sport); 2130 else 2131 sport->lpuart_dma_rx_use = false; 2132 } 2133 2134 uart_port_unlock_irqrestore(port, flags); 2135 } 2136 2137 static void __lpuart32_serial_setbrg(struct uart_port *port, 2138 unsigned int baudrate, bool use_rx_dma, 2139 bool use_tx_dma) 2140 { 2141 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, baud; 2142 u32 clk = port->uartclk; 2143 2144 /* 2145 * The idea is to use the best OSR (over-sampling rate) possible. 2146 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 2147 * Loop to find the best OSR value possible, one that generates minimum 2148 * baud_diff iterate through the rest of the supported values of OSR. 2149 * 2150 * Calculation Formula: 2151 * Baud Rate = baud clock / ((OSR+1) × SBR) 2152 */ 2153 baud_diff = baudrate; 2154 osr = 0; 2155 sbr = 0; 2156 2157 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 2158 /* calculate the temporary sbr value */ 2159 tmp_sbr = (clk / (baudrate * tmp_osr)); 2160 if (tmp_sbr == 0) 2161 tmp_sbr = 1; 2162 2163 /* 2164 * calculate the baud rate difference based on the temporary 2165 * osr and sbr values 2166 */ 2167 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 2168 2169 /* select best values between sbr and sbr+1 */ 2170 baud = clk / (tmp_osr * (tmp_sbr + 1)); 2171 if (tmp_diff > (baudrate - baud)) { 2172 tmp_diff = baudrate - baud; 2173 tmp_sbr++; 2174 } 2175 2176 if (tmp_sbr > UARTBAUD_SBR_MASK) 2177 continue; 2178 2179 if (tmp_diff <= baud_diff) { 2180 baud_diff = tmp_diff; 2181 osr = tmp_osr; 2182 sbr = tmp_sbr; 2183 2184 if (!baud_diff) 2185 break; 2186 } 2187 } 2188 2189 /* handle buadrate outside acceptable rate */ 2190 if (baud_diff > ((baudrate / 100) * 3)) 2191 dev_warn(port->dev, 2192 "unacceptable baud rate difference of more than 3%%\n"); 2193 2194 baud = lpuart32_read(port, UARTBAUD); 2195 2196 if ((osr > 3) && (osr < 8)) 2197 baud |= UARTBAUD_BOTHEDGE; 2198 2199 baud &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 2200 baud |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; 2201 2202 baud &= ~UARTBAUD_SBR_MASK; 2203 baud |= sbr & UARTBAUD_SBR_MASK; 2204 2205 if (!use_rx_dma) 2206 baud &= ~UARTBAUD_RDMAE; 2207 if (!use_tx_dma) 2208 baud &= ~UARTBAUD_TDMAE; 2209 2210 lpuart32_write(port, baud, UARTBAUD); 2211 } 2212 2213 static void lpuart32_serial_setbrg(struct lpuart_port *sport, 2214 unsigned int baudrate) 2215 { 2216 __lpuart32_serial_setbrg(&sport->port, baudrate, 2217 sport->lpuart_dma_rx_use, 2218 sport->lpuart_dma_tx_use); 2219 } 2220 2221 2222 static void 2223 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 2224 const struct ktermios *old) 2225 { 2226 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 2227 unsigned long flags; 2228 u32 ctrl, old_ctrl, bd, modem; 2229 unsigned int baud; 2230 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 2231 2232 ctrl = old_ctrl = lpuart32_read(port, UARTCTRL); 2233 bd = lpuart32_read(port, UARTBAUD); 2234 modem = lpuart32_read(port, UARTMODIR); 2235 sport->is_cs7 = false; 2236 /* 2237 * only support CS8 and CS7 2238 * supported mode: 2239 * - (7,n,1) (imx only) 2240 * - (7,e/o,1) 2241 * - (8,n,1) 2242 * - (8,m/s,1) 2243 * - (8,e/o,1) 2244 */ 2245 while ((termios->c_cflag & CSIZE) != CS8 && 2246 (termios->c_cflag & CSIZE) != CS7) { 2247 termios->c_cflag &= ~CSIZE; 2248 termios->c_cflag |= old_csize; 2249 old_csize = CS8; 2250 } 2251 2252 if ((termios->c_cflag & CSIZE) == CS8 || 2253 (termios->c_cflag & CSIZE) == CS7) 2254 ctrl = old_ctrl & ~(UARTCTRL_M | UARTCTRL_M7); 2255 2256 if (termios->c_cflag & CMSPAR) { 2257 if ((termios->c_cflag & CSIZE) != CS8) { 2258 termios->c_cflag &= ~CSIZE; 2259 termios->c_cflag |= CS8; 2260 } 2261 ctrl |= UARTCTRL_M; 2262 } 2263 2264 /* 2265 * When auto RS-485 RTS mode is enabled, 2266 * hardware flow control need to be disabled. 2267 */ 2268 if (port->rs485.flags & SER_RS485_ENABLED) 2269 termios->c_cflag &= ~CRTSCTS; 2270 2271 if (termios->c_cflag & CRTSCTS) 2272 modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE; 2273 else 2274 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2275 2276 if (termios->c_cflag & CSTOPB) 2277 bd |= UARTBAUD_SBNS; 2278 else 2279 bd &= ~UARTBAUD_SBNS; 2280 2281 /* 2282 * imx support 7-bits format, no limitation on parity when CS7 2283 * for layerscape, parity must be enabled when CS7 to match 8-bits format 2284 */ 2285 if ((termios->c_cflag & CSIZE) == CS7 && !(termios->c_cflag & PARENB)) { 2286 if (is_imx7ulp_lpuart(sport) || 2287 is_imx8ulp_lpuart(sport) || 2288 is_imx8qxp_lpuart(sport)) 2289 ctrl |= UARTCTRL_M7; 2290 else 2291 termios->c_cflag |= PARENB; 2292 } 2293 2294 if ((termios->c_cflag & PARENB)) { 2295 if (termios->c_cflag & CMSPAR) { 2296 ctrl &= ~UARTCTRL_PE; 2297 ctrl |= UARTCTRL_M; 2298 } else { 2299 ctrl |= UARTCTRL_PE; 2300 if ((termios->c_cflag & CSIZE) == CS8) 2301 ctrl |= UARTCTRL_M; 2302 if (termios->c_cflag & PARODD) 2303 ctrl |= UARTCTRL_PT; 2304 else 2305 ctrl &= ~UARTCTRL_PT; 2306 } 2307 } else { 2308 ctrl &= ~UARTCTRL_PE; 2309 } 2310 2311 /* ask the core to calculate the divisor */ 2312 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); 2313 2314 /* 2315 * Need to update the Ring buffer length according to the selected 2316 * baud rate and restart Rx DMA path. 2317 * 2318 * Since timer function acqures port->lock, need to stop before 2319 * acquring same lock because otherwise timer_delete_sync() can deadlock. 2320 */ 2321 if (old && sport->lpuart_dma_rx_use) 2322 lpuart_dma_rx_free(port); 2323 2324 uart_port_lock_irqsave(port, &flags); 2325 2326 port->read_status_mask = 0; 2327 if (termios->c_iflag & INPCK) 2328 port->read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; 2329 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2330 port->read_status_mask |= UARTSTAT_FE; 2331 2332 /* characters to ignore */ 2333 port->ignore_status_mask = 0; 2334 if (termios->c_iflag & IGNPAR) 2335 port->ignore_status_mask |= UARTSTAT_PE; 2336 if (termios->c_iflag & IGNBRK) { 2337 port->ignore_status_mask |= UARTSTAT_FE; 2338 /* 2339 * if we're ignoring parity and break indicators, 2340 * ignore overruns too (for real raw support). 2341 */ 2342 if (termios->c_iflag & IGNPAR) 2343 port->ignore_status_mask |= UARTSTAT_OR; 2344 } 2345 2346 /* update the per-port timeout */ 2347 uart_update_timeout(port, termios->c_cflag, baud); 2348 2349 /* 2350 * disable CTS to ensure the transmit engine is not blocked by the flow 2351 * control when there is dirty data in TX FIFO 2352 */ 2353 lpuart32_write(port, modem & ~UARTMODIR_TXCTSE, UARTMODIR); 2354 2355 /* 2356 * LPUART Transmission Complete Flag may never be set while queuing a break 2357 * character, so skip waiting for transmission complete when UARTCTRL_SBK is 2358 * asserted. 2359 */ 2360 if (!(old_ctrl & UARTCTRL_SBK)) 2361 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TC); 2362 2363 /* disable transmit and receive */ 2364 lpuart32_write(port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 2365 UARTCTRL); 2366 2367 lpuart32_write(port, bd, UARTBAUD); 2368 lpuart32_serial_setbrg(sport, baud); 2369 /* restore control register */ 2370 lpuart32_write(port, ctrl, UARTCTRL); 2371 /* re-enable the CTS if needed */ 2372 lpuart32_write(port, modem, UARTMODIR); 2373 2374 if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE) 2375 sport->is_cs7 = true; 2376 2377 if (old && sport->lpuart_dma_rx_use) { 2378 if (!lpuart_start_rx_dma(sport)) 2379 rx_dma_timer_init(sport); 2380 else 2381 sport->lpuart_dma_rx_use = false; 2382 } 2383 2384 uart_port_unlock_irqrestore(port, flags); 2385 } 2386 2387 static const char *lpuart_type(struct uart_port *port) 2388 { 2389 return "FSL_LPUART"; 2390 } 2391 2392 static void lpuart_release_port(struct uart_port *port) 2393 { 2394 /* nothing to do */ 2395 } 2396 2397 static int lpuart_request_port(struct uart_port *port) 2398 { 2399 return 0; 2400 } 2401 2402 /* configure/autoconfigure the port */ 2403 static void lpuart_config_port(struct uart_port *port, int flags) 2404 { 2405 if (flags & UART_CONFIG_TYPE) 2406 port->type = PORT_LPUART; 2407 } 2408 2409 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 2410 { 2411 int ret = 0; 2412 2413 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 2414 ret = -EINVAL; 2415 if (port->irq != ser->irq) 2416 ret = -EINVAL; 2417 if (ser->io_type != UPIO_MEM) 2418 ret = -EINVAL; 2419 if (port->uartclk / 16 != ser->baud_base) 2420 ret = -EINVAL; 2421 if (port->iobase != ser->port) 2422 ret = -EINVAL; 2423 if (ser->hub6 != 0) 2424 ret = -EINVAL; 2425 return ret; 2426 } 2427 2428 static const struct uart_ops lpuart_pops = { 2429 .tx_empty = lpuart_tx_empty, 2430 .set_mctrl = lpuart_set_mctrl, 2431 .get_mctrl = lpuart_get_mctrl, 2432 .stop_tx = lpuart_stop_tx, 2433 .start_tx = lpuart_start_tx, 2434 .stop_rx = lpuart_stop_rx, 2435 .break_ctl = lpuart_break_ctl, 2436 .startup = lpuart_startup, 2437 .shutdown = lpuart_shutdown, 2438 .set_termios = lpuart_set_termios, 2439 .pm = lpuart_uart_pm, 2440 .type = lpuart_type, 2441 .request_port = lpuart_request_port, 2442 .release_port = lpuart_release_port, 2443 .config_port = lpuart_config_port, 2444 .verify_port = lpuart_verify_port, 2445 .flush_buffer = lpuart_flush_buffer, 2446 #if defined(CONFIG_CONSOLE_POLL) 2447 .poll_init = lpuart_poll_init, 2448 .poll_get_char = lpuart_poll_get_char, 2449 .poll_put_char = lpuart_poll_put_char, 2450 #endif 2451 }; 2452 2453 static const struct uart_ops lpuart32_pops = { 2454 .tx_empty = lpuart32_tx_empty, 2455 .set_mctrl = lpuart32_set_mctrl, 2456 .get_mctrl = lpuart32_get_mctrl, 2457 .stop_tx = lpuart32_stop_tx, 2458 .start_tx = lpuart32_start_tx, 2459 .stop_rx = lpuart32_stop_rx, 2460 .break_ctl = lpuart32_break_ctl, 2461 .startup = lpuart32_startup, 2462 .shutdown = lpuart32_shutdown, 2463 .set_termios = lpuart32_set_termios, 2464 .pm = lpuart_uart_pm, 2465 .type = lpuart_type, 2466 .request_port = lpuart_request_port, 2467 .release_port = lpuart_release_port, 2468 .config_port = lpuart_config_port, 2469 .verify_port = lpuart_verify_port, 2470 .flush_buffer = lpuart_flush_buffer, 2471 #if defined(CONFIG_CONSOLE_POLL) 2472 .poll_init = lpuart32_poll_init, 2473 .poll_get_char = lpuart32_poll_get_char, 2474 .poll_put_char = lpuart32_poll_put_char, 2475 #endif 2476 }; 2477 2478 static struct lpuart_port *lpuart_ports[UART_NR]; 2479 2480 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 2481 static void lpuart_console_putchar(struct uart_port *port, unsigned char ch) 2482 { 2483 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 2484 writeb(ch, port->membase + UARTDR); 2485 } 2486 2487 static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch) 2488 { 2489 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 2490 lpuart32_write(port, ch, UARTDATA); 2491 } 2492 2493 static void 2494 lpuart_console_write(struct console *co, const char *s, unsigned int count) 2495 { 2496 struct lpuart_port *sport = lpuart_ports[co->index]; 2497 u8 old_cr2, cr2; 2498 unsigned long flags; 2499 int locked = 1; 2500 2501 if (oops_in_progress) 2502 locked = uart_port_trylock_irqsave(&sport->port, &flags); 2503 else 2504 uart_port_lock_irqsave(&sport->port, &flags); 2505 2506 /* first save CR2 and then disable interrupts */ 2507 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 2508 cr2 |= UARTCR2_TE | UARTCR2_RE; 2509 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 2510 writeb(cr2, sport->port.membase + UARTCR2); 2511 2512 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 2513 2514 /* wait for transmitter finish complete and restore CR2 */ 2515 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 2516 2517 writeb(old_cr2, sport->port.membase + UARTCR2); 2518 2519 if (locked) 2520 uart_port_unlock_irqrestore(&sport->port, flags); 2521 } 2522 2523 static void 2524 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 2525 { 2526 struct lpuart_port *sport = lpuart_ports[co->index]; 2527 u32 old_cr, cr; 2528 unsigned long flags; 2529 int locked = 1; 2530 2531 if (oops_in_progress) 2532 locked = uart_port_trylock_irqsave(&sport->port, &flags); 2533 else 2534 uart_port_lock_irqsave(&sport->port, &flags); 2535 2536 /* first save CR2 and then disable interrupts */ 2537 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 2538 cr |= UARTCTRL_TE | UARTCTRL_RE; 2539 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 2540 lpuart32_write(&sport->port, cr, UARTCTRL); 2541 2542 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 2543 2544 /* wait for transmitter finish complete and restore CR2 */ 2545 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2546 2547 lpuart32_write(&sport->port, old_cr, UARTCTRL); 2548 2549 if (locked) 2550 uart_port_unlock_irqrestore(&sport->port, flags); 2551 } 2552 2553 /* 2554 * if the port was already initialised (eg, by a boot loader), 2555 * try to determine the current setup. 2556 */ 2557 static void __init 2558 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 2559 int *parity, int *bits) 2560 { 2561 u8 cr, bdh, bdl, brfa; 2562 unsigned int sbr, uartclk, baud_raw; 2563 2564 cr = readb(sport->port.membase + UARTCR2); 2565 cr &= UARTCR2_TE | UARTCR2_RE; 2566 if (!cr) 2567 return; 2568 2569 /* ok, the port was enabled */ 2570 2571 cr = readb(sport->port.membase + UARTCR1); 2572 2573 *parity = 'n'; 2574 if (cr & UARTCR1_PE) { 2575 if (cr & UARTCR1_PT) 2576 *parity = 'o'; 2577 else 2578 *parity = 'e'; 2579 } 2580 2581 if (cr & UARTCR1_M) 2582 *bits = 9; 2583 else 2584 *bits = 8; 2585 2586 bdh = readb(sport->port.membase + UARTBDH); 2587 bdh &= UARTBDH_SBR_MASK; 2588 bdl = readb(sport->port.membase + UARTBDL); 2589 sbr = bdh; 2590 sbr <<= 8; 2591 sbr |= bdl; 2592 brfa = readb(sport->port.membase + UARTCR4); 2593 brfa &= UARTCR4_BRFA_MASK; 2594 2595 uartclk = lpuart_get_baud_clk_rate(sport); 2596 /* 2597 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2598 */ 2599 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 2600 2601 if (*baud != baud_raw) 2602 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2603 "from %d to %d\n", baud_raw, *baud); 2604 } 2605 2606 static void __init 2607 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 2608 int *parity, int *bits) 2609 { 2610 u32 cr, bd; 2611 unsigned int sbr, uartclk, baud_raw; 2612 2613 cr = lpuart32_read(&sport->port, UARTCTRL); 2614 cr &= UARTCTRL_TE | UARTCTRL_RE; 2615 if (!cr) 2616 return; 2617 2618 /* ok, the port was enabled */ 2619 2620 cr = lpuart32_read(&sport->port, UARTCTRL); 2621 2622 *parity = 'n'; 2623 if (cr & UARTCTRL_PE) { 2624 if (cr & UARTCTRL_PT) 2625 *parity = 'o'; 2626 else 2627 *parity = 'e'; 2628 } 2629 2630 if (cr & UARTCTRL_M) 2631 *bits = 9; 2632 else 2633 *bits = 8; 2634 2635 bd = lpuart32_read(&sport->port, UARTBAUD); 2636 bd &= UARTBAUD_SBR_MASK; 2637 if (!bd) 2638 return; 2639 2640 sbr = bd; 2641 uartclk = lpuart_get_baud_clk_rate(sport); 2642 /* 2643 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2644 */ 2645 baud_raw = uartclk / (16 * sbr); 2646 2647 if (*baud != baud_raw) 2648 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2649 "from %d to %d\n", baud_raw, *baud); 2650 } 2651 2652 static int __init lpuart_console_setup(struct console *co, char *options) 2653 { 2654 struct lpuart_port *sport; 2655 int baud = 115200; 2656 int bits = 8; 2657 int parity = 'n'; 2658 int flow = 'n'; 2659 2660 /* 2661 * check whether an invalid uart number has been specified, and 2662 * if so, search for the first available port that does have 2663 * console support. 2664 */ 2665 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2666 co->index = 0; 2667 2668 sport = lpuart_ports[co->index]; 2669 if (sport == NULL) 2670 return -ENODEV; 2671 2672 if (options) 2673 uart_parse_options(options, &baud, &parity, &bits, &flow); 2674 else 2675 if (lpuart_is_32(sport)) 2676 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2677 else 2678 lpuart_console_get_options(sport, &baud, &parity, &bits); 2679 2680 if (lpuart_is_32(sport)) 2681 lpuart32_setup_watermark(sport); 2682 else 2683 lpuart_setup_watermark(sport); 2684 2685 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2686 } 2687 2688 static struct uart_driver lpuart_reg; 2689 static struct console lpuart_console = { 2690 .name = DEV_NAME, 2691 .write = lpuart_console_write, 2692 .device = uart_console_device, 2693 .setup = lpuart_console_setup, 2694 .flags = CON_PRINTBUFFER, 2695 .index = -1, 2696 .data = &lpuart_reg, 2697 }; 2698 2699 static struct console lpuart32_console = { 2700 .name = DEV_NAME, 2701 .write = lpuart32_console_write, 2702 .device = uart_console_device, 2703 .setup = lpuart_console_setup, 2704 .flags = CON_PRINTBUFFER, 2705 .index = -1, 2706 .data = &lpuart_reg, 2707 }; 2708 2709 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2710 { 2711 struct earlycon_device *dev = con->data; 2712 2713 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2714 } 2715 2716 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2717 { 2718 struct earlycon_device *dev = con->data; 2719 2720 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2721 } 2722 2723 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2724 const char *opt) 2725 { 2726 if (!device->port.membase) 2727 return -ENODEV; 2728 2729 device->con->write = lpuart_early_write; 2730 return 0; 2731 } 2732 2733 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2734 const char *opt) 2735 { 2736 if (!device->port.membase) 2737 return -ENODEV; 2738 2739 if (device->port.iotype != UPIO_MEM32) 2740 device->port.iotype = UPIO_MEM32BE; 2741 2742 device->con->write = lpuart32_early_write; 2743 return 0; 2744 } 2745 2746 static int __init ls1028a_early_console_setup(struct earlycon_device *device, 2747 const char *opt) 2748 { 2749 u32 cr; 2750 2751 if (!device->port.membase) 2752 return -ENODEV; 2753 2754 device->port.iotype = UPIO_MEM32; 2755 device->con->write = lpuart32_early_write; 2756 2757 /* set the baudrate */ 2758 if (device->port.uartclk && device->baud) 2759 __lpuart32_serial_setbrg(&device->port, device->baud, 2760 false, false); 2761 2762 /* enable transmitter */ 2763 cr = lpuart32_read(&device->port, UARTCTRL); 2764 cr |= UARTCTRL_TE; 2765 lpuart32_write(&device->port, cr, UARTCTRL); 2766 2767 return 0; 2768 } 2769 2770 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2771 const char *opt) 2772 { 2773 if (!device->port.membase) 2774 return -ENODEV; 2775 2776 device->port.iotype = UPIO_MEM32; 2777 device->port.membase += IMX_REG_OFF; 2778 device->con->write = lpuart32_early_write; 2779 2780 return 0; 2781 } 2782 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2783 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2784 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup); 2785 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2786 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup); 2787 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup); 2788 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup); 2789 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2790 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2791 2792 #define LPUART_CONSOLE (&lpuart_console) 2793 #define LPUART32_CONSOLE (&lpuart32_console) 2794 #else 2795 #define LPUART_CONSOLE NULL 2796 #define LPUART32_CONSOLE NULL 2797 #endif 2798 2799 static struct uart_driver lpuart_reg = { 2800 .owner = THIS_MODULE, 2801 .driver_name = DRIVER_NAME, 2802 .dev_name = DEV_NAME, 2803 .nr = ARRAY_SIZE(lpuart_ports), 2804 .cons = LPUART_CONSOLE, 2805 }; 2806 2807 static const struct serial_rs485 lpuart_rs485_supported = { 2808 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND, 2809 /* delay_rts_* and RX_DURING_TX are not supported */ 2810 }; 2811 2812 static int lpuart_global_reset(struct lpuart_port *sport) 2813 { 2814 struct uart_port *port = &sport->port; 2815 void __iomem *global_addr; 2816 u32 ctrl, bd; 2817 unsigned int val = 0; 2818 int ret; 2819 2820 ret = clk_prepare_enable(sport->ipg_clk); 2821 if (ret) { 2822 dev_err(port->dev, "failed to enable uart ipg clk: %d\n", ret); 2823 return ret; 2824 } 2825 2826 if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) { 2827 /* 2828 * If the transmitter is used by earlycon, wait for transmit engine to 2829 * complete and then reset. 2830 */ 2831 ctrl = lpuart32_read(port, UARTCTRL); 2832 if (ctrl & UARTCTRL_TE) { 2833 bd = lpuart32_read(port, UARTBAUD); 2834 if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false, 2835 port)) { 2836 dev_warn(port->dev, 2837 "timeout waiting for transmit engine to complete\n"); 2838 clk_disable_unprepare(sport->ipg_clk); 2839 return 0; 2840 } 2841 } 2842 2843 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; 2844 writel(UART_GLOBAL_RST, global_addr); 2845 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 2846 writel(0, global_addr); 2847 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 2848 2849 /* Recover the transmitter for earlycon. */ 2850 if (ctrl & UARTCTRL_TE) { 2851 lpuart32_write(port, bd, UARTBAUD); 2852 lpuart32_write(port, ctrl, UARTCTRL); 2853 } 2854 } 2855 2856 clk_disable_unprepare(sport->ipg_clk); 2857 return 0; 2858 } 2859 2860 static int lpuart_probe(struct platform_device *pdev) 2861 { 2862 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev); 2863 struct device_node *np = pdev->dev.of_node; 2864 struct lpuart_port *sport; 2865 struct resource *res; 2866 irq_handler_t handler; 2867 int ret; 2868 2869 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2870 if (!sport) 2871 return -ENOMEM; 2872 2873 sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2874 if (IS_ERR(sport->port.membase)) 2875 return PTR_ERR(sport->port.membase); 2876 2877 sport->port.membase += sdata->reg_off; 2878 sport->port.mapbase = res->start + sdata->reg_off; 2879 sport->port.dev = &pdev->dev; 2880 sport->port.type = PORT_LPUART; 2881 sport->devtype = sdata->devtype; 2882 sport->rx_watermark = sdata->rx_watermark; 2883 sport->dma_idle_int = is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || 2884 is_imx8qxp_lpuart(sport); 2885 ret = platform_get_irq(pdev, 0); 2886 if (ret < 0) 2887 return ret; 2888 sport->port.irq = ret; 2889 sport->port.iotype = sdata->iotype; 2890 if (lpuart_is_32(sport)) 2891 sport->port.ops = &lpuart32_pops; 2892 else 2893 sport->port.ops = &lpuart_pops; 2894 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); 2895 sport->port.flags = UPF_BOOT_AUTOCONF; 2896 2897 if (lpuart_is_32(sport)) 2898 sport->port.rs485_config = lpuart32_config_rs485; 2899 else 2900 sport->port.rs485_config = lpuart_config_rs485; 2901 sport->port.rs485_supported = lpuart_rs485_supported; 2902 2903 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 2904 if (IS_ERR(sport->ipg_clk)) { 2905 ret = PTR_ERR(sport->ipg_clk); 2906 return dev_err_probe(&pdev->dev, ret, "failed to get uart ipg clk\n"); 2907 } 2908 2909 sport->baud_clk = NULL; 2910 if (is_imx8qxp_lpuart(sport)) { 2911 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); 2912 if (IS_ERR(sport->baud_clk)) { 2913 ret = PTR_ERR(sport->baud_clk); 2914 return dev_err_probe(&pdev->dev, ret, "failed to get uart baud clk\n"); 2915 } 2916 } 2917 2918 ret = of_alias_get_id(np, "serial"); 2919 if (ret < 0) { 2920 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2921 return ret; 2922 } 2923 if (ret >= ARRAY_SIZE(lpuart_ports)) { 2924 dev_err(&pdev->dev, "serial%d out of range\n", ret); 2925 return -EINVAL; 2926 } 2927 sport->port.line = ret; 2928 2929 ret = lpuart_enable_clks(sport); 2930 if (ret) 2931 return ret; 2932 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); 2933 2934 lpuart_ports[sport->port.line] = sport; 2935 2936 platform_set_drvdata(pdev, &sport->port); 2937 2938 if (lpuart_is_32(sport)) { 2939 lpuart_reg.cons = LPUART32_CONSOLE; 2940 handler = lpuart32_int; 2941 } else { 2942 lpuart_reg.cons = LPUART_CONSOLE; 2943 handler = lpuart_int; 2944 } 2945 2946 pm_runtime_use_autosuspend(&pdev->dev); 2947 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 2948 pm_runtime_set_active(&pdev->dev); 2949 pm_runtime_enable(&pdev->dev); 2950 pm_runtime_mark_last_busy(&pdev->dev); 2951 2952 ret = lpuart_global_reset(sport); 2953 if (ret) 2954 goto failed_reset; 2955 2956 ret = uart_get_rs485_mode(&sport->port); 2957 if (ret) 2958 goto failed_get_rs485; 2959 2960 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2961 if (ret) 2962 goto failed_attach_port; 2963 2964 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0, 2965 dev_name(&pdev->dev), sport); 2966 if (ret) 2967 goto failed_irq_request; 2968 2969 return 0; 2970 2971 failed_irq_request: 2972 uart_remove_one_port(&lpuart_reg, &sport->port); 2973 failed_attach_port: 2974 failed_get_rs485: 2975 failed_reset: 2976 pm_runtime_disable(&pdev->dev); 2977 pm_runtime_set_suspended(&pdev->dev); 2978 pm_runtime_dont_use_autosuspend(&pdev->dev); 2979 lpuart_disable_clks(sport); 2980 return ret; 2981 } 2982 2983 static void lpuart_remove(struct platform_device *pdev) 2984 { 2985 struct lpuart_port *sport = platform_get_drvdata(pdev); 2986 2987 uart_remove_one_port(&lpuart_reg, &sport->port); 2988 2989 lpuart_disable_clks(sport); 2990 2991 if (sport->dma_tx_chan) 2992 dma_release_channel(sport->dma_tx_chan); 2993 2994 if (sport->dma_rx_chan) 2995 dma_release_channel(sport->dma_rx_chan); 2996 2997 pm_runtime_disable(&pdev->dev); 2998 pm_runtime_set_suspended(&pdev->dev); 2999 pm_runtime_dont_use_autosuspend(&pdev->dev); 3000 } 3001 3002 static int lpuart_runtime_suspend(struct device *dev) 3003 { 3004 struct platform_device *pdev = to_platform_device(dev); 3005 struct lpuart_port *sport = platform_get_drvdata(pdev); 3006 3007 lpuart_disable_clks(sport); 3008 3009 return 0; 3010 }; 3011 3012 static int lpuart_runtime_resume(struct device *dev) 3013 { 3014 struct platform_device *pdev = to_platform_device(dev); 3015 struct lpuart_port *sport = platform_get_drvdata(pdev); 3016 3017 return lpuart_enable_clks(sport); 3018 }; 3019 3020 static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on) 3021 { 3022 u32 val, baud; 3023 3024 if (lpuart_is_32(sport)) { 3025 val = lpuart32_read(&sport->port, UARTCTRL); 3026 baud = lpuart32_read(&sport->port, UARTBAUD); 3027 if (on) { 3028 /* set rx_watermark to 0 in wakeup source mode */ 3029 lpuart32_write(&sport->port, 0, UARTWATER); 3030 val |= UARTCTRL_RIE; 3031 /* clear RXEDGIF flag before enable RXEDGIE interrupt */ 3032 lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT); 3033 baud |= UARTBAUD_RXEDGIE; 3034 } else { 3035 val &= ~UARTCTRL_RIE; 3036 baud &= ~UARTBAUD_RXEDGIE; 3037 } 3038 lpuart32_write(&sport->port, val, UARTCTRL); 3039 lpuart32_write(&sport->port, baud, UARTBAUD); 3040 } else { 3041 val = readb(sport->port.membase + UARTCR2); 3042 if (on) 3043 val |= UARTCR2_RIE; 3044 else 3045 val &= ~UARTCR2_RIE; 3046 writeb(val, sport->port.membase + UARTCR2); 3047 } 3048 } 3049 3050 static bool lpuart_uport_is_active(struct lpuart_port *sport) 3051 { 3052 struct tty_port *port = &sport->port.state->port; 3053 struct tty_struct *tty; 3054 struct device *tty_dev; 3055 int may_wake = 0; 3056 3057 tty = tty_port_tty_get(port); 3058 if (tty) { 3059 tty_dev = tty->dev; 3060 may_wake = tty_dev && device_may_wakeup(tty_dev); 3061 tty_kref_put(tty); 3062 } 3063 3064 if ((tty_port_initialized(port) && may_wake) || 3065 (!console_suspend_enabled && uart_console(&sport->port))) 3066 return true; 3067 3068 return false; 3069 } 3070 3071 static int lpuart_suspend_noirq(struct device *dev) 3072 { 3073 struct lpuart_port *sport = dev_get_drvdata(dev); 3074 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 3075 3076 if (lpuart_uport_is_active(sport)) 3077 serial_lpuart_enable_wakeup(sport, !!irq_wake); 3078 3079 pinctrl_pm_select_sleep_state(dev); 3080 3081 return 0; 3082 } 3083 3084 static int lpuart_resume_noirq(struct device *dev) 3085 { 3086 struct lpuart_port *sport = dev_get_drvdata(dev); 3087 u32 stat; 3088 3089 pinctrl_pm_select_default_state(dev); 3090 3091 if (lpuart_uport_is_active(sport)) { 3092 serial_lpuart_enable_wakeup(sport, false); 3093 3094 /* clear the wakeup flags */ 3095 if (lpuart_is_32(sport)) { 3096 stat = lpuart32_read(&sport->port, UARTSTAT); 3097 lpuart32_write(&sport->port, stat, UARTSTAT); 3098 } 3099 } 3100 3101 return 0; 3102 } 3103 3104 static int lpuart_suspend(struct device *dev) 3105 { 3106 struct lpuart_port *sport = dev_get_drvdata(dev); 3107 u32 temp; 3108 unsigned long flags; 3109 3110 uart_suspend_port(&lpuart_reg, &sport->port); 3111 3112 if (lpuart_uport_is_active(sport)) { 3113 uart_port_lock_irqsave(&sport->port, &flags); 3114 if (lpuart_is_32(sport)) { 3115 /* disable Rx/Tx and interrupts */ 3116 temp = lpuart32_read(&sport->port, UARTCTRL); 3117 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 3118 lpuart32_write(&sport->port, temp, UARTCTRL); 3119 } else { 3120 /* disable Rx/Tx and interrupts */ 3121 temp = readb(sport->port.membase + UARTCR2); 3122 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 3123 writeb(temp, sport->port.membase + UARTCR2); 3124 } 3125 uart_port_unlock_irqrestore(&sport->port, flags); 3126 3127 if (sport->lpuart_dma_rx_use) { 3128 /* 3129 * EDMA driver during suspend will forcefully release any 3130 * non-idle DMA channels. If port wakeup is enabled or if port 3131 * is console port or 'no_console_suspend' is set the Rx DMA 3132 * cannot resume as expected, hence gracefully release the 3133 * Rx DMA path before suspend and start Rx DMA path on resume. 3134 */ 3135 lpuart_dma_rx_free(&sport->port); 3136 3137 /* Disable Rx DMA to use UART port as wakeup source */ 3138 uart_port_lock_irqsave(&sport->port, &flags); 3139 if (lpuart_is_32(sport)) { 3140 temp = lpuart32_read(&sport->port, UARTBAUD); 3141 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 3142 UARTBAUD); 3143 } else { 3144 writeb(readb(sport->port.membase + UARTCR5) & 3145 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 3146 } 3147 uart_port_unlock_irqrestore(&sport->port, flags); 3148 } 3149 3150 if (sport->lpuart_dma_tx_use) { 3151 uart_port_lock_irqsave(&sport->port, &flags); 3152 if (lpuart_is_32(sport)) { 3153 temp = lpuart32_read(&sport->port, UARTBAUD); 3154 temp &= ~UARTBAUD_TDMAE; 3155 lpuart32_write(&sport->port, temp, UARTBAUD); 3156 } else { 3157 temp = readb(sport->port.membase + UARTCR5); 3158 temp &= ~UARTCR5_TDMAS; 3159 writeb(temp, sport->port.membase + UARTCR5); 3160 } 3161 uart_port_unlock_irqrestore(&sport->port, flags); 3162 sport->dma_tx_in_progress = false; 3163 dmaengine_terminate_sync(sport->dma_tx_chan); 3164 } 3165 } else if (pm_runtime_active(sport->port.dev)) { 3166 lpuart_disable_clks(sport); 3167 pm_runtime_disable(sport->port.dev); 3168 pm_runtime_set_suspended(sport->port.dev); 3169 } 3170 3171 return 0; 3172 } 3173 3174 static void lpuart_console_fixup(struct lpuart_port *sport) 3175 { 3176 struct tty_port *port = &sport->port.state->port; 3177 struct uart_port *uport = &sport->port; 3178 struct ktermios termios; 3179 3180 /* i.MX7ULP enter VLLS mode that lpuart module power off and registers 3181 * all lost no matter the port is wakeup source. 3182 * For console port, console baud rate setting lost and print messy 3183 * log when enable the console port as wakeup source. To avoid the 3184 * issue happen, user should not enable uart port as wakeup source 3185 * in VLLS mode, or restore console setting here. 3186 */ 3187 if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) && 3188 console_suspend_enabled && uart_console(uport)) { 3189 3190 mutex_lock(&port->mutex); 3191 memset(&termios, 0, sizeof(struct ktermios)); 3192 termios.c_cflag = uport->cons->cflag; 3193 if (port->tty && termios.c_cflag == 0) 3194 termios = port->tty->termios; 3195 uport->ops->set_termios(uport, &termios, NULL); 3196 mutex_unlock(&port->mutex); 3197 } 3198 } 3199 3200 static int lpuart_resume(struct device *dev) 3201 { 3202 struct lpuart_port *sport = dev_get_drvdata(dev); 3203 int ret; 3204 3205 if (lpuart_uport_is_active(sport)) { 3206 if (lpuart_is_32(sport)) 3207 lpuart32_hw_setup(sport); 3208 else 3209 lpuart_hw_setup(sport); 3210 } else if (pm_runtime_active(sport->port.dev)) { 3211 ret = lpuart_enable_clks(sport); 3212 if (ret) 3213 return ret; 3214 pm_runtime_set_active(sport->port.dev); 3215 pm_runtime_enable(sport->port.dev); 3216 } 3217 3218 lpuart_console_fixup(sport); 3219 uart_resume_port(&lpuart_reg, &sport->port); 3220 3221 return 0; 3222 } 3223 3224 static const struct dev_pm_ops lpuart_pm_ops = { 3225 RUNTIME_PM_OPS(lpuart_runtime_suspend, 3226 lpuart_runtime_resume, NULL) 3227 NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq, 3228 lpuart_resume_noirq) 3229 SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume) 3230 }; 3231 3232 static struct platform_driver lpuart_driver = { 3233 .probe = lpuart_probe, 3234 .remove = lpuart_remove, 3235 .driver = { 3236 .name = "fsl-lpuart", 3237 .of_match_table = lpuart_dt_ids, 3238 .pm = pm_ptr(&lpuart_pm_ops), 3239 }, 3240 }; 3241 3242 static int __init lpuart_serial_init(void) 3243 { 3244 int ret = uart_register_driver(&lpuart_reg); 3245 3246 if (ret) 3247 return ret; 3248 3249 ret = platform_driver_register(&lpuart_driver); 3250 if (ret) 3251 uart_unregister_driver(&lpuart_reg); 3252 3253 return ret; 3254 } 3255 3256 static void __exit lpuart_serial_exit(void) 3257 { 3258 platform_driver_unregister(&lpuart_driver); 3259 uart_unregister_driver(&lpuart_reg); 3260 } 3261 3262 module_init(lpuart_serial_init); 3263 module_exit(lpuart_serial_exit); 3264 3265 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 3266 MODULE_LICENSE("GPL v2"); 3267