1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/debugfs.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/reset.h> 19 #include <linux/thermal.h> 20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h> 21 22 #include "../thermal_hwmon.h" 23 24 #define LVTS_MONCTL0(__base) (__base + 0x0000) 25 #define LVTS_MONCTL1(__base) (__base + 0x0004) 26 #define LVTS_MONCTL2(__base) (__base + 0x0008) 27 #define LVTS_MONINT(__base) (__base + 0x000C) 28 #define LVTS_MONINTSTS(__base) (__base + 0x0010) 29 #define LVTS_MONIDET0(__base) (__base + 0x0014) 30 #define LVTS_MONIDET1(__base) (__base + 0x0018) 31 #define LVTS_MONIDET2(__base) (__base + 0x001C) 32 #define LVTS_MONIDET3(__base) (__base + 0x0020) 33 #define LVTS_H2NTHRE(__base) (__base + 0x0024) 34 #define LVTS_HTHRE(__base) (__base + 0x0028) 35 #define LVTS_OFFSETH(__base) (__base + 0x0030) 36 #define LVTS_OFFSETL(__base) (__base + 0x0034) 37 #define LVTS_MSRCTL0(__base) (__base + 0x0038) 38 #define LVTS_MSRCTL1(__base) (__base + 0x003C) 39 #define LVTS_TSSEL(__base) (__base + 0x0040) 40 #define LVTS_CALSCALE(__base) (__base + 0x0048) 41 #define LVTS_ID(__base) (__base + 0x004C) 42 #define LVTS_CONFIG(__base) (__base + 0x0050) 43 #define LVTS_EDATA00(__base) (__base + 0x0054) 44 #define LVTS_EDATA01(__base) (__base + 0x0058) 45 #define LVTS_EDATA02(__base) (__base + 0x005C) 46 #define LVTS_EDATA03(__base) (__base + 0x0060) 47 #define LVTS_MSR0(__base) (__base + 0x0090) 48 #define LVTS_MSR1(__base) (__base + 0x0094) 49 #define LVTS_MSR2(__base) (__base + 0x0098) 50 #define LVTS_MSR3(__base) (__base + 0x009C) 51 #define LVTS_IMMD0(__base) (__base + 0x00A0) 52 #define LVTS_IMMD1(__base) (__base + 0x00A4) 53 #define LVTS_IMMD2(__base) (__base + 0x00A8) 54 #define LVTS_IMMD3(__base) (__base + 0x00AC) 55 #define LVTS_PROTCTL(__base) (__base + 0x00C0) 56 #define LVTS_PROTTA(__base) (__base + 0x00C4) 57 #define LVTS_PROTTB(__base) (__base + 0x00C8) 58 #define LVTS_PROTTC(__base) (__base + 0x00CC) 59 #define LVTS_CLKEN(__base) (__base + 0x00E4) 60 61 #define LVTS_PERIOD_UNIT ((118 * 1000) / (256 * 38)) 62 #define LVTS_GROUP_INTERVAL 1 63 #define LVTS_FILTER_INTERVAL 1 64 #define LVTS_SENSOR_INTERVAL 1 65 #define LVTS_HW_FILTER 0x2 66 #define LVTS_TSSEL_CONF 0x13121110 67 #define LVTS_CALSCALE_CONF 0x300 68 #define LVTS_MONINT_CONF 0x8300318C 69 70 #define LVTS_MONINT_OFFSET_SENSOR0 0xC 71 #define LVTS_MONINT_OFFSET_SENSOR1 0x180 72 #define LVTS_MONINT_OFFSET_SENSOR2 0x3000 73 #define LVTS_MONINT_OFFSET_SENSOR3 0x3000000 74 75 #define LVTS_INT_SENSOR0 0x0009001F 76 #define LVTS_INT_SENSOR1 0x001203E0 77 #define LVTS_INT_SENSOR2 0x00247C00 78 #define LVTS_INT_SENSOR3 0x1FC00000 79 80 #define LVTS_SENSOR_MAX 4 81 #define LVTS_GOLDEN_TEMP_MAX 62 82 #define LVTS_GOLDEN_TEMP_DEFAULT 50 83 #define LVTS_COEFF_A -250460 84 #define LVTS_COEFF_B 250460 85 86 #define LVTS_MSR_IMMEDIATE_MODE 0 87 #define LVTS_MSR_FILTERED_MODE 1 88 89 #define LVTS_HW_SHUTDOWN_MT8195 105000 90 91 #define LVTS_MINIMUM_THRESHOLD 20000 92 93 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; 94 static int coeff_b = LVTS_COEFF_B; 95 96 struct lvts_sensor_data { 97 int dt_id; 98 }; 99 100 struct lvts_ctrl_data { 101 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; 102 int cal_offset[LVTS_SENSOR_MAX]; 103 int hw_tshut_temp; 104 int num_lvts_sensor; 105 int offset; 106 int mode; 107 }; 108 109 struct lvts_data { 110 const struct lvts_ctrl_data *lvts_ctrl; 111 int num_lvts_ctrl; 112 }; 113 114 struct lvts_sensor { 115 struct thermal_zone_device *tz; 116 void __iomem *msr; 117 void __iomem *base; 118 int id; 119 int dt_id; 120 int low_thresh; 121 int high_thresh; 122 }; 123 124 struct lvts_ctrl { 125 struct lvts_sensor sensors[LVTS_SENSOR_MAX]; 126 u32 calibration[LVTS_SENSOR_MAX]; 127 u32 hw_tshut_raw_temp; 128 int num_lvts_sensor; 129 int mode; 130 void __iomem *base; 131 int low_thresh; 132 int high_thresh; 133 }; 134 135 struct lvts_domain { 136 struct lvts_ctrl *lvts_ctrl; 137 struct reset_control *reset; 138 struct clk *clk; 139 int num_lvts_ctrl; 140 void __iomem *base; 141 size_t calib_len; 142 u8 *calib; 143 #ifdef CONFIG_DEBUG_FS 144 struct dentry *dom_dentry; 145 #endif 146 }; 147 148 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS 149 150 #define LVTS_DEBUG_FS_REGS(__reg) \ 151 { \ 152 .name = __stringify(__reg), \ 153 .offset = __reg(0), \ 154 } 155 156 static const struct debugfs_reg32 lvts_regs[] = { 157 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), 158 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), 159 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), 160 LVTS_DEBUG_FS_REGS(LVTS_MONINT), 161 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), 162 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), 163 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), 164 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), 165 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), 166 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), 167 LVTS_DEBUG_FS_REGS(LVTS_HTHRE), 168 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), 169 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), 170 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), 171 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), 172 LVTS_DEBUG_FS_REGS(LVTS_TSSEL), 173 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), 174 LVTS_DEBUG_FS_REGS(LVTS_ID), 175 LVTS_DEBUG_FS_REGS(LVTS_CONFIG), 176 LVTS_DEBUG_FS_REGS(LVTS_EDATA00), 177 LVTS_DEBUG_FS_REGS(LVTS_EDATA01), 178 LVTS_DEBUG_FS_REGS(LVTS_EDATA02), 179 LVTS_DEBUG_FS_REGS(LVTS_EDATA03), 180 LVTS_DEBUG_FS_REGS(LVTS_MSR0), 181 LVTS_DEBUG_FS_REGS(LVTS_MSR1), 182 LVTS_DEBUG_FS_REGS(LVTS_MSR2), 183 LVTS_DEBUG_FS_REGS(LVTS_MSR3), 184 LVTS_DEBUG_FS_REGS(LVTS_IMMD0), 185 LVTS_DEBUG_FS_REGS(LVTS_IMMD1), 186 LVTS_DEBUG_FS_REGS(LVTS_IMMD2), 187 LVTS_DEBUG_FS_REGS(LVTS_IMMD3), 188 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), 189 LVTS_DEBUG_FS_REGS(LVTS_PROTTA), 190 LVTS_DEBUG_FS_REGS(LVTS_PROTTB), 191 LVTS_DEBUG_FS_REGS(LVTS_PROTTC), 192 LVTS_DEBUG_FS_REGS(LVTS_CLKEN), 193 }; 194 195 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) 196 { 197 struct debugfs_regset32 *regset; 198 struct lvts_ctrl *lvts_ctrl; 199 struct dentry *dentry; 200 char name[64]; 201 int i; 202 203 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); 204 if (IS_ERR(lvts_td->dom_dentry)) 205 return 0; 206 207 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 208 209 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 210 211 sprintf(name, "controller%d", i); 212 dentry = debugfs_create_dir(name, lvts_td->dom_dentry); 213 if (!dentry) 214 continue; 215 216 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 217 if (!regset) 218 continue; 219 220 regset->base = lvts_ctrl->base; 221 regset->regs = lvts_regs; 222 regset->nregs = ARRAY_SIZE(lvts_regs); 223 224 debugfs_create_regset32("registers", 0400, dentry, regset); 225 } 226 227 return 0; 228 } 229 230 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) 231 { 232 debugfs_remove_recursive(lvts_td->dom_dentry); 233 } 234 235 #else 236 237 static inline int lvts_debugfs_init(struct device *dev, 238 struct lvts_domain *lvts_td) 239 { 240 return 0; 241 } 242 243 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { } 244 245 #endif 246 247 static int lvts_raw_to_temp(u32 raw_temp) 248 { 249 int temperature; 250 251 temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14; 252 temperature += coeff_b; 253 254 return temperature; 255 } 256 257 static u32 lvts_temp_to_raw(int temperature) 258 { 259 u32 raw_temp = ((s64)(coeff_b - temperature)) << 14; 260 261 raw_temp = div_s64(raw_temp, -LVTS_COEFF_A); 262 263 return raw_temp; 264 } 265 266 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) 267 { 268 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 269 void __iomem *msr = lvts_sensor->msr; 270 u32 value; 271 272 /* 273 * Measurement registers: 274 * 275 * LVTS_MSR[0-3] / LVTS_IMMD[0-3] 276 * 277 * Bits: 278 * 279 * 32-17: Unused 280 * 16 : Valid temperature 281 * 15-0 : Raw temperature 282 */ 283 value = readl(msr); 284 285 /* 286 * As the thermal zone temperature will read before the 287 * hardware sensor is fully initialized, we have to check the 288 * validity of the temperature returned when reading the 289 * measurement register. The thermal controller will set the 290 * valid bit temperature only when it is totally initialized. 291 * 292 * Otherwise, we may end up with garbage values out of the 293 * functionning temperature and directly jump to a system 294 * shutdown. 295 */ 296 if (!(value & BIT(16))) 297 return -EAGAIN; 298 299 *temp = lvts_raw_to_temp(value & 0xFFFF); 300 301 return 0; 302 } 303 304 static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) 305 { 306 u32 masks[] = { 307 LVTS_MONINT_OFFSET_SENSOR0, 308 LVTS_MONINT_OFFSET_SENSOR1, 309 LVTS_MONINT_OFFSET_SENSOR2, 310 LVTS_MONINT_OFFSET_SENSOR3, 311 }; 312 u32 value = 0; 313 int i; 314 315 value = readl(LVTS_MONINT(lvts_ctrl->base)); 316 317 for (i = 0; i < ARRAY_SIZE(masks); i++) { 318 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 319 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 320 value |= masks[i]; 321 else 322 value &= ~masks[i]; 323 } 324 325 writel(value, LVTS_MONINT(lvts_ctrl->base)); 326 } 327 328 static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high) 329 { 330 int i; 331 332 if (high > lvts_ctrl->high_thresh) 333 return true; 334 335 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) 336 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 337 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 338 return false; 339 340 return true; 341 } 342 343 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) 344 { 345 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 346 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]); 347 void __iomem *base = lvts_sensor->base; 348 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD); 349 u32 raw_high = lvts_temp_to_raw(high); 350 bool should_update_thresh; 351 352 lvts_sensor->low_thresh = low; 353 lvts_sensor->high_thresh = high; 354 355 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high); 356 if (should_update_thresh) { 357 lvts_ctrl->high_thresh = high; 358 lvts_ctrl->low_thresh = low; 359 } 360 lvts_update_irq_mask(lvts_ctrl); 361 362 if (!should_update_thresh) 363 return 0; 364 365 /* 366 * Low offset temperature threshold 367 * 368 * LVTS_OFFSETL 369 * 370 * Bits: 371 * 372 * 14-0 : Raw temperature for threshold 373 */ 374 pr_debug("%s: Setting low limit temperature interrupt: %d\n", 375 thermal_zone_device_type(tz), low); 376 writel(raw_low, LVTS_OFFSETL(base)); 377 378 /* 379 * High offset temperature threshold 380 * 381 * LVTS_OFFSETH 382 * 383 * Bits: 384 * 385 * 14-0 : Raw temperature for threshold 386 */ 387 pr_debug("%s: Setting high limit temperature interrupt: %d\n", 388 thermal_zone_device_type(tz), high); 389 writel(raw_high, LVTS_OFFSETH(base)); 390 391 return 0; 392 } 393 394 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) 395 { 396 irqreturn_t iret = IRQ_NONE; 397 u32 value; 398 u32 masks[] = { 399 LVTS_INT_SENSOR0, 400 LVTS_INT_SENSOR1, 401 LVTS_INT_SENSOR2, 402 LVTS_INT_SENSOR3 403 }; 404 int i; 405 406 /* 407 * Interrupt monitoring status 408 * 409 * LVTS_MONINTST 410 * 411 * Bits: 412 * 413 * 31 : Interrupt for stage 3 414 * 30 : Interrupt for stage 2 415 * 29 : Interrupt for state 1 416 * 28 : Interrupt using filter on sensor 3 417 * 418 * 27 : Interrupt using immediate on sensor 3 419 * 26 : Interrupt normal to hot on sensor 3 420 * 25 : Interrupt high offset on sensor 3 421 * 24 : Interrupt low offset on sensor 3 422 * 423 * 23 : Interrupt hot threshold on sensor 3 424 * 22 : Interrupt cold threshold on sensor 3 425 * 21 : Interrupt using filter on sensor 2 426 * 20 : Interrupt using filter on sensor 1 427 * 428 * 19 : Interrupt using filter on sensor 0 429 * 18 : Interrupt using immediate on sensor 2 430 * 17 : Interrupt using immediate on sensor 1 431 * 16 : Interrupt using immediate on sensor 0 432 * 433 * 15 : Interrupt device access timeout interrupt 434 * 14 : Interrupt normal to hot on sensor 2 435 * 13 : Interrupt high offset interrupt on sensor 2 436 * 12 : Interrupt low offset interrupt on sensor 2 437 * 438 * 11 : Interrupt hot threshold on sensor 2 439 * 10 : Interrupt cold threshold on sensor 2 440 * 9 : Interrupt normal to hot on sensor 1 441 * 8 : Interrupt high offset interrupt on sensor 1 442 * 443 * 7 : Interrupt low offset interrupt on sensor 1 444 * 6 : Interrupt hot threshold on sensor 1 445 * 5 : Interrupt cold threshold on sensor 1 446 * 4 : Interrupt normal to hot on sensor 0 447 * 448 * 3 : Interrupt high offset interrupt on sensor 0 449 * 2 : Interrupt low offset interrupt on sensor 0 450 * 1 : Interrupt hot threshold on sensor 0 451 * 0 : Interrupt cold threshold on sensor 0 452 * 453 * We are interested in the sensor(s) responsible of the 454 * interrupt event. We update the thermal framework with the 455 * thermal zone associated with the sensor. The framework will 456 * take care of the rest whatever the kind of interrupt, we 457 * are only interested in which sensor raised the interrupt. 458 * 459 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 460 * => 0x1FC00000 461 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 462 * => 0x00247C00 463 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 464 * => 0X001203E0 465 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 466 * => 0x0009001F 467 */ 468 value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); 469 470 /* 471 * Let's figure out which sensors raised the interrupt 472 * 473 * NOTE: the masks array must be ordered with the index 474 * corresponding to the sensor id eg. index=0, mask for 475 * sensor0. 476 */ 477 for (i = 0; i < ARRAY_SIZE(masks); i++) { 478 479 if (!(value & masks[i])) 480 continue; 481 482 thermal_zone_device_update(lvts_ctrl->sensors[i].tz, 483 THERMAL_TRIP_VIOLATED); 484 iret = IRQ_HANDLED; 485 } 486 487 /* 488 * Write back to clear the interrupt status (W1C) 489 */ 490 writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); 491 492 return iret; 493 } 494 495 /* 496 * Temperature interrupt handler. Even if the driver supports more 497 * interrupt modes, we use the interrupt when the temperature crosses 498 * the hot threshold the way up and the way down (modulo the 499 * hysteresis). 500 * 501 * Each thermal domain has a couple of interrupts, one for hardware 502 * reset and another one for all the thermal events happening on the 503 * different sensors. 504 * 505 * The interrupt is configured for thermal events when crossing the 506 * hot temperature limit. At each interrupt, we check in every 507 * controller if there is an interrupt pending. 508 */ 509 static irqreturn_t lvts_irq_handler(int irq, void *data) 510 { 511 struct lvts_domain *lvts_td = data; 512 irqreturn_t aux, iret = IRQ_NONE; 513 int i; 514 515 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 516 517 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]); 518 if (aux != IRQ_HANDLED) 519 continue; 520 521 iret = IRQ_HANDLED; 522 } 523 524 return iret; 525 } 526 527 static struct thermal_zone_device_ops lvts_ops = { 528 .get_temp = lvts_get_temp, 529 .set_trips = lvts_set_trips, 530 }; 531 532 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 533 const struct lvts_ctrl_data *lvts_ctrl_data) 534 { 535 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; 536 void __iomem *msr_regs[] = { 537 LVTS_MSR0(lvts_ctrl->base), 538 LVTS_MSR1(lvts_ctrl->base), 539 LVTS_MSR2(lvts_ctrl->base), 540 LVTS_MSR3(lvts_ctrl->base) 541 }; 542 543 void __iomem *imm_regs[] = { 544 LVTS_IMMD0(lvts_ctrl->base), 545 LVTS_IMMD1(lvts_ctrl->base), 546 LVTS_IMMD2(lvts_ctrl->base), 547 LVTS_IMMD3(lvts_ctrl->base) 548 }; 549 550 int i; 551 552 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { 553 554 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; 555 556 /* 557 * At this point, we don't know which id matches which 558 * sensor. Let's set arbitrally the id from the index. 559 */ 560 lvts_sensor[i].id = i; 561 562 /* 563 * The thermal zone registration will set the trip 564 * point interrupt in the thermal controller 565 * register. But this one will be reset in the 566 * initialization after. So we need to post pone the 567 * thermal zone creation after the controller is 568 * setup. For this reason, we store the device tree 569 * node id from the data in the sensor structure 570 */ 571 lvts_sensor[i].dt_id = dt_id; 572 573 /* 574 * We assign the base address of the thermal 575 * controller as a back pointer. So it will be 576 * accessible from the different thermal framework ops 577 * as we pass the lvts_sensor pointer as thermal zone 578 * private data. 579 */ 580 lvts_sensor[i].base = lvts_ctrl->base; 581 582 /* 583 * Each sensor has its own register address to read from. 584 */ 585 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? 586 imm_regs[i] : msr_regs[i]; 587 588 lvts_sensor[i].low_thresh = INT_MIN; 589 lvts_sensor[i].high_thresh = INT_MIN; 590 }; 591 592 lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; 593 594 return 0; 595 } 596 597 /* 598 * The efuse blob values follows the sensor enumeration per thermal 599 * controller. The decoding of the stream is as follow: 600 * 601 * stream index map for MCU Domain : 602 * 603 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 604 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 605 * 606 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 607 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 608 * 609 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 610 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 611 * 612 * stream index map for AP Domain : 613 * 614 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 615 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A 616 * 617 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 618 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 619 * 620 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> 621 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F 622 * 623 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> 624 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 625 * 626 * The data description gives the offset of the calibration data in 627 * this bytes stream for each sensor. 628 */ 629 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 630 const struct lvts_ctrl_data *lvts_ctrl_data, 631 u8 *efuse_calibration) 632 { 633 int i; 634 635 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) 636 memcpy(&lvts_ctrl->calibration[i], 637 efuse_calibration + lvts_ctrl_data->cal_offset[i], 2); 638 639 return 0; 640 } 641 642 /* 643 * The efuse bytes stream can be split into different chunk of 644 * nvmems. This function reads and concatenate those into a single 645 * buffer so it can be read sequentially when initializing the 646 * calibration data. 647 */ 648 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, 649 const struct lvts_data *lvts_data) 650 { 651 struct device_node *np = dev_of_node(dev); 652 struct nvmem_cell *cell; 653 struct property *prop; 654 const char *cell_name; 655 656 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { 657 size_t len; 658 u8 *efuse; 659 660 cell = of_nvmem_cell_get(np, cell_name); 661 if (IS_ERR(cell)) { 662 dev_err(dev, "Failed to get cell '%s'\n", cell_name); 663 return PTR_ERR(cell); 664 } 665 666 efuse = nvmem_cell_read(cell, &len); 667 668 nvmem_cell_put(cell); 669 670 if (IS_ERR(efuse)) { 671 dev_err(dev, "Failed to read cell '%s'\n", cell_name); 672 return PTR_ERR(efuse); 673 } 674 675 lvts_td->calib = devm_krealloc(dev, lvts_td->calib, 676 lvts_td->calib_len + len, GFP_KERNEL); 677 if (!lvts_td->calib) 678 return -ENOMEM; 679 680 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); 681 682 lvts_td->calib_len += len; 683 684 kfree(efuse); 685 } 686 687 return 0; 688 } 689 690 static int lvts_golden_temp_init(struct device *dev, u32 *value) 691 { 692 u32 gt; 693 694 gt = (*value) >> 24; 695 696 if (gt && gt < LVTS_GOLDEN_TEMP_MAX) 697 golden_temp = gt; 698 699 coeff_b = golden_temp * 500 + LVTS_COEFF_B; 700 701 return 0; 702 } 703 704 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, 705 const struct lvts_data *lvts_data) 706 { 707 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; 708 struct lvts_ctrl *lvts_ctrl; 709 int i, ret; 710 711 /* 712 * Create the calibration bytes stream from efuse data 713 */ 714 ret = lvts_calibration_read(dev, lvts_td, lvts_data); 715 if (ret) 716 return ret; 717 718 /* 719 * The golden temp information is contained in the first chunk 720 * of efuse data. 721 */ 722 ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib); 723 if (ret) 724 return ret; 725 726 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); 727 if (!lvts_ctrl) 728 return -ENOMEM; 729 730 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { 731 732 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; 733 734 ret = lvts_sensor_init(dev, &lvts_ctrl[i], 735 &lvts_data->lvts_ctrl[i]); 736 if (ret) 737 return ret; 738 739 ret = lvts_calibration_init(dev, &lvts_ctrl[i], 740 &lvts_data->lvts_ctrl[i], 741 lvts_td->calib); 742 if (ret) 743 return ret; 744 745 /* 746 * The mode the ctrl will use to read the temperature 747 * (filtered or immediate) 748 */ 749 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; 750 751 /* 752 * The temperature to raw temperature must be done 753 * after initializing the calibration. 754 */ 755 lvts_ctrl[i].hw_tshut_raw_temp = 756 lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp); 757 758 lvts_ctrl[i].low_thresh = INT_MIN; 759 lvts_ctrl[i].high_thresh = INT_MIN; 760 } 761 762 /* 763 * We no longer need the efuse bytes stream, let's free it 764 */ 765 devm_kfree(dev, lvts_td->calib); 766 767 lvts_td->lvts_ctrl = lvts_ctrl; 768 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; 769 770 return 0; 771 } 772 773 /* 774 * At this point the configuration register is the only place in the 775 * driver where we write multiple values. Per hardware constraint, 776 * each write in the configuration register must be separated by a 777 * delay of 2 us. 778 */ 779 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) 780 { 781 int i; 782 783 /* 784 * Configuration register 785 */ 786 for (i = 0; i < nr_cmds; i++) { 787 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); 788 usleep_range(2, 4); 789 } 790 } 791 792 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) 793 { 794 /* 795 * LVTS_PROTCTL : Thermal Protection Sensor Selection 796 * 797 * Bits: 798 * 799 * 19-18 : Sensor to base the protection on 800 * 17-16 : Strategy: 801 * 00 : Average of 4 sensors 802 * 01 : Max of 4 sensors 803 * 10 : Selected sensor with bits 19-18 804 * 11 : Reserved 805 */ 806 writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); 807 808 /* 809 * LVTS_PROTTA : Stage 1 temperature threshold 810 * LVTS_PROTTB : Stage 2 temperature threshold 811 * LVTS_PROTTC : Stage 3 temperature threshold 812 * 813 * Bits: 814 * 815 * 14-0: Raw temperature threshold 816 * 817 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); 818 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); 819 */ 820 writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); 821 822 /* 823 * LVTS_MONINT : Interrupt configuration register 824 * 825 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS 826 * register, except we set the bits to enable the interrupt. 827 */ 828 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); 829 830 return 0; 831 } 832 833 static int lvts_domain_reset(struct device *dev, struct reset_control *reset) 834 { 835 int ret; 836 837 ret = reset_control_assert(reset); 838 if (ret) 839 return ret; 840 841 return reset_control_deassert(reset); 842 } 843 844 /* 845 * Enable or disable the clocks of a specified thermal controller 846 */ 847 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) 848 { 849 /* 850 * LVTS_CLKEN : Internal LVTS clock 851 * 852 * Bits: 853 * 854 * 0 : enable / disable clock 855 */ 856 writel(enable, LVTS_CLKEN(lvts_ctrl->base)); 857 858 return 0; 859 } 860 861 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) 862 { 863 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; 864 865 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 866 867 /* 868 * LVTS_ID : Get ID and status of the thermal controller 869 * 870 * Bits: 871 * 872 * 0-5 : thermal controller id 873 * 7 : thermal controller connection is valid 874 */ 875 id = readl(LVTS_ID(lvts_ctrl->base)); 876 if (!(id & BIT(7))) 877 return -EIO; 878 879 return 0; 880 } 881 882 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) 883 { 884 /* 885 * Write device mask: 0xC1030000 886 */ 887 u32 cmds[] = { 888 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, 889 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, 890 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, 891 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 892 }; 893 894 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 895 896 return 0; 897 } 898 899 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) 900 { 901 int i; 902 void __iomem *lvts_edata[] = { 903 LVTS_EDATA00(lvts_ctrl->base), 904 LVTS_EDATA01(lvts_ctrl->base), 905 LVTS_EDATA02(lvts_ctrl->base), 906 LVTS_EDATA03(lvts_ctrl->base) 907 }; 908 909 /* 910 * LVTS_EDATA0X : Efuse calibration reference value for sensor X 911 * 912 * Bits: 913 * 914 * 20-0 : Efuse value for normalization data 915 */ 916 for (i = 0; i < LVTS_SENSOR_MAX; i++) 917 writel(lvts_ctrl->calibration[i], lvts_edata[i]); 918 919 return 0; 920 } 921 922 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) 923 { 924 u32 value; 925 926 /* 927 * LVTS_TSSEL : Sensing point index numbering 928 * 929 * Bits: 930 * 931 * 31-24: ADC Sense 3 932 * 23-16: ADC Sense 2 933 * 15-8 : ADC Sense 1 934 * 7-0 : ADC Sense 0 935 */ 936 value = LVTS_TSSEL_CONF; 937 writel(value, LVTS_TSSEL(lvts_ctrl->base)); 938 939 /* 940 * LVTS_CALSCALE : ADC voltage round 941 */ 942 value = 0x300; 943 value = LVTS_CALSCALE_CONF; 944 945 /* 946 * LVTS_MSRCTL0 : Sensor filtering strategy 947 * 948 * Filters: 949 * 950 * 000 : One sample 951 * 001 : Avg 2 samples 952 * 010 : 4 samples, drop min and max, avg 2 samples 953 * 011 : 6 samples, drop min and max, avg 4 samples 954 * 100 : 10 samples, drop min and max, avg 8 samples 955 * 101 : 18 samples, drop min and max, avg 16 samples 956 * 957 * Bits: 958 * 959 * 0-2 : Sensor0 filter 960 * 3-5 : Sensor1 filter 961 * 6-8 : Sensor2 filter 962 * 9-11 : Sensor3 filter 963 */ 964 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | 965 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; 966 writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); 967 968 /* 969 * LVTS_MONCTL1 : Period unit and group interval configuration 970 * 971 * The clock source of LVTS thermal controller is 26MHz. 972 * 973 * The period unit is a time base for all the interval delays 974 * specified in the registers. By default we use 12. The time 975 * conversion is done by multiplying by 256 and 1/26.10^6 976 * 977 * An interval delay multiplied by the period unit gives the 978 * duration in seconds. 979 * 980 * - Filter interval delay is a delay between two samples of 981 * the same sensor. 982 * 983 * - Sensor interval delay is a delay between two samples of 984 * different sensors. 985 * 986 * - Group interval delay is a delay between different rounds. 987 * 988 * For example: 989 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, 990 * and two sensors, TS1 and TS2, are in a LVTS thermal controller 991 * and then 992 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us 993 * Filter interval delay = 1 * Period unit = 118.149us 994 * Sensor interval delay = 2 * Period unit = 236.298us 995 * Group interval delay = 1 * Period unit = 118.149us 996 * 997 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... 998 * <--> Filter interval delay 999 * <--> Sensor interval delay 1000 * <--> Group interval delay 1001 * Bits: 1002 * 29 - 20 : Group interval 1003 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) 1004 * or an interrupt everytime the hot threshold is crossed (0) 1005 * 9 - 0 : Period unit 1006 * 1007 */ 1008 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; 1009 writel(value, LVTS_MONCTL1(lvts_ctrl->base)); 1010 1011 /* 1012 * LVTS_MONCTL2 : Filtering and sensor interval 1013 * 1014 * Bits: 1015 * 1016 * 25-16 : Interval unit in PERIOD_UNIT between sample on 1017 * the same sensor, filter interval 1018 * 9-0 : Interval unit in PERIOD_UNIT between each sensor 1019 * 1020 */ 1021 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; 1022 writel(value, LVTS_MONCTL2(lvts_ctrl->base)); 1023 1024 return lvts_irq_init(lvts_ctrl); 1025 } 1026 1027 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) 1028 { 1029 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; 1030 struct thermal_zone_device *tz; 1031 u32 sensor_map = 0; 1032 int i; 1033 /* 1034 * Bitmaps to enable each sensor on immediate and filtered modes, as 1035 * described in MSRCTL1 and MONCTL0 registers below, respectively. 1036 */ 1037 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) }; 1038 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) }; 1039 1040 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ? 1041 sensor_imm_bitmap : sensor_filt_bitmap; 1042 1043 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) { 1044 1045 int dt_id = lvts_sensors[i].dt_id; 1046 1047 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], 1048 &lvts_ops); 1049 if (IS_ERR(tz)) { 1050 /* 1051 * This thermal zone is not described in the 1052 * device tree. It is not an error from the 1053 * thermal OF code POV, we just continue. 1054 */ 1055 if (PTR_ERR(tz) == -ENODEV) 1056 continue; 1057 1058 return PTR_ERR(tz); 1059 } 1060 1061 devm_thermal_add_hwmon_sysfs(dev, tz); 1062 1063 /* 1064 * The thermal zone pointer will be needed in the 1065 * interrupt handler, we store it in the sensor 1066 * structure. The thermal domain structure will be 1067 * passed to the interrupt handler private data as the 1068 * interrupt is shared for all the controller 1069 * belonging to the thermal domain. 1070 */ 1071 lvts_sensors[i].tz = tz; 1072 1073 /* 1074 * This sensor was correctly associated with a thermal 1075 * zone, let's set the corresponding bit in the sensor 1076 * map, so we can enable the temperature monitoring in 1077 * the hardware thermal controller. 1078 */ 1079 sensor_map |= sensor_bitmap[i]; 1080 } 1081 1082 /* 1083 * The initialization of the thermal zones give us 1084 * which sensor point to enable. If any thermal zone 1085 * was not described in the device tree, it won't be 1086 * enabled here in the sensor map. 1087 */ 1088 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { 1089 /* 1090 * LVTS_MSRCTL1 : Measurement control 1091 * 1092 * Bits: 1093 * 1094 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 1095 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 1096 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 1097 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 1098 * 1099 * That configuration will ignore the filtering and the delays 1100 * introduced in MONCTL1 and MONCTL2 1101 */ 1102 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base)); 1103 } else { 1104 /* 1105 * Bits: 1106 * 9: Single point access flow 1107 * 0-3: Enable sensing point 0-3 1108 */ 1109 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); 1110 } 1111 1112 return 0; 1113 } 1114 1115 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, 1116 const struct lvts_data *lvts_data) 1117 { 1118 struct lvts_ctrl *lvts_ctrl; 1119 int i, ret; 1120 1121 ret = lvts_ctrl_init(dev, lvts_td, lvts_data); 1122 if (ret) 1123 return ret; 1124 1125 ret = lvts_domain_reset(dev, lvts_td->reset); 1126 if (ret) { 1127 dev_dbg(dev, "Failed to reset domain"); 1128 return ret; 1129 } 1130 1131 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1132 1133 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 1134 1135 /* 1136 * Initialization steps: 1137 * 1138 * - Enable the clock 1139 * - Connect to the LVTS 1140 * - Initialize the LVTS 1141 * - Prepare the calibration data 1142 * - Select monitored sensors 1143 * [ Configure sampling ] 1144 * [ Configure the interrupt ] 1145 * - Start measurement 1146 */ 1147 ret = lvts_ctrl_set_enable(lvts_ctrl, true); 1148 if (ret) { 1149 dev_dbg(dev, "Failed to enable LVTS clock"); 1150 return ret; 1151 } 1152 1153 ret = lvts_ctrl_connect(dev, lvts_ctrl); 1154 if (ret) { 1155 dev_dbg(dev, "Failed to connect to LVTS controller"); 1156 return ret; 1157 } 1158 1159 ret = lvts_ctrl_initialize(dev, lvts_ctrl); 1160 if (ret) { 1161 dev_dbg(dev, "Failed to initialize controller"); 1162 return ret; 1163 } 1164 1165 ret = lvts_ctrl_calibrate(dev, lvts_ctrl); 1166 if (ret) { 1167 dev_dbg(dev, "Failed to calibrate controller"); 1168 return ret; 1169 } 1170 1171 ret = lvts_ctrl_configure(dev, lvts_ctrl); 1172 if (ret) { 1173 dev_dbg(dev, "Failed to configure controller"); 1174 return ret; 1175 } 1176 1177 ret = lvts_ctrl_start(dev, lvts_ctrl); 1178 if (ret) { 1179 dev_dbg(dev, "Failed to start controller"); 1180 return ret; 1181 } 1182 } 1183 1184 return lvts_debugfs_init(dev, lvts_td); 1185 } 1186 1187 static int lvts_probe(struct platform_device *pdev) 1188 { 1189 const struct lvts_data *lvts_data; 1190 struct lvts_domain *lvts_td; 1191 struct device *dev = &pdev->dev; 1192 struct resource *res; 1193 int irq, ret; 1194 1195 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); 1196 if (!lvts_td) 1197 return -ENOMEM; 1198 1199 lvts_data = of_device_get_match_data(dev); 1200 1201 lvts_td->clk = devm_clk_get_enabled(dev, NULL); 1202 if (IS_ERR(lvts_td->clk)) 1203 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); 1204 1205 res = platform_get_mem_or_io(pdev, 0); 1206 if (!res) 1207 return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); 1208 1209 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1210 if (IS_ERR(lvts_td->base)) 1211 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); 1212 1213 lvts_td->reset = devm_reset_control_get_by_index(dev, 0); 1214 if (IS_ERR(lvts_td->reset)) 1215 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); 1216 1217 irq = platform_get_irq(pdev, 0); 1218 if (irq < 0) 1219 return dev_err_probe(dev, irq, "No irq resource\n"); 1220 1221 ret = lvts_domain_init(dev, lvts_td, lvts_data); 1222 if (ret) 1223 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); 1224 1225 /* 1226 * At this point the LVTS is initialized and enabled. We can 1227 * safely enable the interrupt. 1228 */ 1229 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, 1230 IRQF_ONESHOT, dev_name(dev), lvts_td); 1231 if (ret) 1232 return dev_err_probe(dev, ret, "Failed to request interrupt\n"); 1233 1234 platform_set_drvdata(pdev, lvts_td); 1235 1236 return 0; 1237 } 1238 1239 static int lvts_remove(struct platform_device *pdev) 1240 { 1241 struct lvts_domain *lvts_td; 1242 int i; 1243 1244 lvts_td = platform_get_drvdata(pdev); 1245 1246 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1247 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1248 1249 lvts_debugfs_exit(lvts_td); 1250 1251 return 0; 1252 } 1253 1254 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { 1255 { 1256 .cal_offset = { 0x04, 0x07 }, 1257 .lvts_sensor = { 1258 { .dt_id = MT8195_MCU_BIG_CPU0 }, 1259 { .dt_id = MT8195_MCU_BIG_CPU1 } 1260 }, 1261 .num_lvts_sensor = 2, 1262 .offset = 0x0, 1263 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1264 }, 1265 { 1266 .cal_offset = { 0x0d, 0x10 }, 1267 .lvts_sensor = { 1268 { .dt_id = MT8195_MCU_BIG_CPU2 }, 1269 { .dt_id = MT8195_MCU_BIG_CPU3 } 1270 }, 1271 .num_lvts_sensor = 2, 1272 .offset = 0x100, 1273 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1274 }, 1275 { 1276 .cal_offset = { 0x16, 0x19, 0x1c, 0x1f }, 1277 .lvts_sensor = { 1278 { .dt_id = MT8195_MCU_LITTLE_CPU0 }, 1279 { .dt_id = MT8195_MCU_LITTLE_CPU1 }, 1280 { .dt_id = MT8195_MCU_LITTLE_CPU2 }, 1281 { .dt_id = MT8195_MCU_LITTLE_CPU3 } 1282 }, 1283 .num_lvts_sensor = 4, 1284 .offset = 0x200, 1285 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1286 } 1287 }; 1288 1289 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { 1290 { 1291 .cal_offset = { 0x25, 0x28 }, 1292 .lvts_sensor = { 1293 { .dt_id = MT8195_AP_VPU0 }, 1294 { .dt_id = MT8195_AP_VPU1 } 1295 }, 1296 .num_lvts_sensor = 2, 1297 .offset = 0x0, 1298 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1299 }, 1300 { 1301 .cal_offset = { 0x2e, 0x31 }, 1302 .lvts_sensor = { 1303 { .dt_id = MT8195_AP_GPU0 }, 1304 { .dt_id = MT8195_AP_GPU1 } 1305 }, 1306 .num_lvts_sensor = 2, 1307 .offset = 0x100, 1308 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1309 }, 1310 { 1311 .cal_offset = { 0x37, 0x3a, 0x3d }, 1312 .lvts_sensor = { 1313 { .dt_id = MT8195_AP_VDEC }, 1314 { .dt_id = MT8195_AP_IMG }, 1315 { .dt_id = MT8195_AP_INFRA }, 1316 }, 1317 .num_lvts_sensor = 3, 1318 .offset = 0x200, 1319 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1320 }, 1321 { 1322 .cal_offset = { 0x43, 0x46 }, 1323 .lvts_sensor = { 1324 { .dt_id = MT8195_AP_CAM0 }, 1325 { .dt_id = MT8195_AP_CAM1 } 1326 }, 1327 .num_lvts_sensor = 2, 1328 .offset = 0x300, 1329 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1330 } 1331 }; 1332 1333 static const struct lvts_data mt8195_lvts_mcu_data = { 1334 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, 1335 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), 1336 }; 1337 1338 static const struct lvts_data mt8195_lvts_ap_data = { 1339 .lvts_ctrl = mt8195_lvts_ap_data_ctrl, 1340 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), 1341 }; 1342 1343 static const struct of_device_id lvts_of_match[] = { 1344 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, 1345 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, 1346 {}, 1347 }; 1348 MODULE_DEVICE_TABLE(of, lvts_of_match); 1349 1350 static struct platform_driver lvts_driver = { 1351 .probe = lvts_probe, 1352 .remove = lvts_remove, 1353 .driver = { 1354 .name = "mtk-lvts-thermal", 1355 .of_match_table = lvts_of_match, 1356 }, 1357 }; 1358 module_platform_driver(lvts_driver); 1359 1360 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>"); 1361 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); 1362 MODULE_LICENSE("GPL"); 1363