1 /* 2 * SPDX-License-Identifier: GPL-2.0 3 * 4 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 5 * 6 * Authors: 7 * Md Sadre Alam <quic_mdalam@quicinc.com> 8 * Sricharan R <quic_srichara@quicinc.com> 9 * Varadarajan Narayanan <quic_varada@quicinc.com> 10 */ 11 #include <linux/bitops.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dmaengine.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/dma/qcom_adm.h> 17 #include <linux/dma/qcom_bam_dma.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 #include <linux/mtd/nand-qpic-common.h> 23 #include <linux/mtd/spinand.h> 24 #include <linux/bitfield.h> 25 26 #define NAND_FLASH_SPI_CFG 0xc0 27 #define NAND_NUM_ADDR_CYCLES 0xc4 28 #define NAND_BUSY_CHECK_WAIT_CNT 0xc8 29 #define NAND_FLASH_FEATURES 0xf64 30 31 /* QSPI NAND config reg bits */ 32 #define LOAD_CLK_CNTR_INIT_EN BIT(28) 33 #define CLK_CNTR_INIT_VAL_VEC 0x924 34 #define CLK_CNTR_INIT_VAL_VEC_MASK GENMASK(27, 16) 35 #define FEA_STATUS_DEV_ADDR 0xc0 36 #define FEA_STATUS_DEV_ADDR_MASK GENMASK(15, 8) 37 #define SPI_CFG BIT(0) 38 #define SPI_NUM_ADDR 0xDA4DB 39 #define SPI_WAIT_CNT 0x10 40 #define QPIC_QSPI_NUM_CS 1 41 #define SPI_TRANSFER_MODE_x1 BIT(29) 42 #define SPI_TRANSFER_MODE_x4 (3 << 29) 43 #define SPI_WP BIT(28) 44 #define SPI_HOLD BIT(27) 45 #define QPIC_SET_FEATURE BIT(31) 46 47 #define SPINAND_RESET 0xff 48 #define SPINAND_READID 0x9f 49 #define SPINAND_GET_FEATURE 0x0f 50 #define SPINAND_SET_FEATURE 0x1f 51 #define SPINAND_READ 0x13 52 #define SPINAND_ERASE 0xd8 53 #define SPINAND_WRITE_EN 0x06 54 #define SPINAND_PROGRAM_EXECUTE 0x10 55 #define SPINAND_PROGRAM_LOAD 0x84 56 57 #define ACC_FEATURE 0xe 58 #define BAD_BLOCK_MARKER_SIZE 0x2 59 #define OOB_BUF_SIZE 128 60 #define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng) 61 62 struct qpic_snand_op { 63 u32 cmd_reg; 64 u32 addr1_reg; 65 u32 addr2_reg; 66 }; 67 68 struct snandc_read_status { 69 __le32 snandc_flash; 70 __le32 snandc_buffer; 71 __le32 snandc_erased_cw; 72 }; 73 74 /* 75 * ECC state struct 76 * @corrected: ECC corrected 77 * @bitflips: Max bit flip 78 * @failed: ECC failed 79 */ 80 struct qcom_ecc_stats { 81 u32 corrected; 82 u32 bitflips; 83 u32 failed; 84 }; 85 86 struct qpic_ecc { 87 struct device *dev; 88 int ecc_bytes_hw; 89 int spare_bytes; 90 int bbm_size; 91 int ecc_mode; 92 int bytes; 93 int steps; 94 int step_size; 95 int strength; 96 int cw_size; 97 int cw_data; 98 u32 cfg0; 99 u32 cfg1; 100 u32 cfg0_raw; 101 u32 cfg1_raw; 102 u32 ecc_buf_cfg; 103 u32 ecc_bch_cfg; 104 u32 clrflashstatus; 105 u32 clrreadstatus; 106 bool bch_enabled; 107 }; 108 109 struct qpic_spi_nand { 110 struct qcom_nand_controller *snandc; 111 struct spi_controller *ctlr; 112 struct mtd_info *mtd; 113 struct clk *iomacro_clk; 114 struct qpic_ecc *ecc; 115 struct qcom_ecc_stats ecc_stats; 116 struct nand_ecc_engine ecc_eng; 117 u8 *data_buf; 118 u8 *oob_buf; 119 __le32 addr1; 120 __le32 addr2; 121 __le32 cmd; 122 u32 num_cw; 123 bool oob_rw; 124 bool page_rw; 125 bool raw_rw; 126 }; 127 128 static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc, 129 int reg, int cw_offset, int read_size, 130 int is_last_read_loc) 131 { 132 __le32 locreg_val; 133 u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) | 134 FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) | 135 FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc); 136 137 locreg_val = cpu_to_le32(val); 138 139 if (reg == NAND_READ_LOCATION_0) 140 snandc->regs->read_location0 = locreg_val; 141 else if (reg == NAND_READ_LOCATION_1) 142 snandc->regs->read_location1 = locreg_val; 143 else if (reg == NAND_READ_LOCATION_2) 144 snandc->regs->read_location2 = locreg_val; 145 else if (reg == NAND_READ_LOCATION_3) 146 snandc->regs->read_location3 = locreg_val; 147 } 148 149 static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc, 150 int reg, int cw_offset, int read_size, 151 int is_last_read_loc) 152 { 153 __le32 locreg_val; 154 u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) | 155 FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) | 156 FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc); 157 158 locreg_val = cpu_to_le32(val); 159 160 if (reg == NAND_READ_LOCATION_LAST_CW_0) 161 snandc->regs->read_location_last0 = locreg_val; 162 else if (reg == NAND_READ_LOCATION_LAST_CW_1) 163 snandc->regs->read_location_last1 = locreg_val; 164 else if (reg == NAND_READ_LOCATION_LAST_CW_2) 165 snandc->regs->read_location_last2 = locreg_val; 166 else if (reg == NAND_READ_LOCATION_LAST_CW_3) 167 snandc->regs->read_location_last3 = locreg_val; 168 } 169 170 static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand) 171 { 172 struct nand_ecc_engine *eng = nand->ecc.engine; 173 struct qpic_spi_nand *qspi = ecceng_to_qspi(eng); 174 175 return qspi->snandc; 176 } 177 178 static int qcom_spi_init(struct qcom_nand_controller *snandc) 179 { 180 u32 snand_cfg_val = 0x0; 181 int ret; 182 183 snand_cfg_val = FIELD_PREP(CLK_CNTR_INIT_VAL_VEC_MASK, CLK_CNTR_INIT_VAL_VEC) | 184 FIELD_PREP(LOAD_CLK_CNTR_INIT_EN, 0) | 185 FIELD_PREP(FEA_STATUS_DEV_ADDR_MASK, FEA_STATUS_DEV_ADDR) | 186 FIELD_PREP(SPI_CFG, 0); 187 188 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val); 189 snandc->regs->num_addr_cycle = cpu_to_le32(SPI_NUM_ADDR); 190 snandc->regs->busy_wait_cnt = cpu_to_le32(SPI_WAIT_CNT); 191 192 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0); 193 194 snand_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN; 195 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val); 196 197 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0); 198 199 qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_CYCLES, 1, 0); 200 qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_WAIT_CNT, 1, 201 NAND_BAM_NEXT_SGL); 202 203 ret = qcom_submit_descs(snandc); 204 if (ret) { 205 dev_err(snandc->dev, "failure in submitting spi init descriptor\n"); 206 return ret; 207 } 208 209 return ret; 210 } 211 212 static int qcom_spi_ooblayout_ecc(struct mtd_info *mtd, int section, 213 struct mtd_oob_region *oobregion) 214 { 215 struct nand_device *nand = mtd_to_nanddev(mtd); 216 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); 217 struct qpic_ecc *qecc = snandc->qspi->ecc; 218 219 if (section > 1) 220 return -ERANGE; 221 222 oobregion->length = qecc->ecc_bytes_hw + qecc->spare_bytes; 223 oobregion->offset = mtd->oobsize - oobregion->length; 224 225 return 0; 226 } 227 228 static int qcom_spi_ooblayout_free(struct mtd_info *mtd, int section, 229 struct mtd_oob_region *oobregion) 230 { 231 struct nand_device *nand = mtd_to_nanddev(mtd); 232 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); 233 struct qpic_ecc *qecc = snandc->qspi->ecc; 234 235 if (section) 236 return -ERANGE; 237 238 oobregion->length = qecc->steps * 4; 239 oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size; 240 241 return 0; 242 } 243 244 static const struct mtd_ooblayout_ops qcom_spi_ooblayout = { 245 .ecc = qcom_spi_ooblayout_ecc, 246 .free = qcom_spi_ooblayout_free, 247 }; 248 249 static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand) 250 { 251 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); 252 struct nand_ecc_props *reqs = &nand->ecc.requirements; 253 struct nand_ecc_props *user = &nand->ecc.user_conf; 254 struct nand_ecc_props *conf = &nand->ecc.ctx.conf; 255 struct mtd_info *mtd = nanddev_to_mtd(nand); 256 int cwperpage, bad_block_byte, ret; 257 struct qpic_ecc *ecc_cfg; 258 259 cwperpage = mtd->writesize / NANDC_STEP_SIZE; 260 snandc->qspi->num_cw = cwperpage; 261 262 ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL); 263 if (!ecc_cfg) 264 return -ENOMEM; 265 266 if (user->step_size && user->strength) { 267 ecc_cfg->step_size = user->step_size; 268 ecc_cfg->strength = user->strength; 269 } else if (reqs->step_size && reqs->strength) { 270 ecc_cfg->step_size = reqs->step_size; 271 ecc_cfg->strength = reqs->strength; 272 } else { 273 /* use defaults */ 274 ecc_cfg->step_size = NANDC_STEP_SIZE; 275 ecc_cfg->strength = 4; 276 } 277 278 if (ecc_cfg->step_size != NANDC_STEP_SIZE) { 279 dev_err(snandc->dev, 280 "only %u bytes ECC step size is supported\n", 281 NANDC_STEP_SIZE); 282 ret = -EOPNOTSUPP; 283 goto err_free_ecc_cfg; 284 } 285 286 if (ecc_cfg->strength != 4) { 287 dev_err(snandc->dev, 288 "only 4 bits ECC strength is supported\n"); 289 ret = -EOPNOTSUPP; 290 goto err_free_ecc_cfg; 291 } 292 293 snandc->qspi->oob_buf = kmalloc(mtd->writesize + mtd->oobsize, 294 GFP_KERNEL); 295 if (!snandc->qspi->oob_buf) { 296 ret = -ENOMEM; 297 goto err_free_ecc_cfg; 298 } 299 300 memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize); 301 302 nand->ecc.ctx.priv = ecc_cfg; 303 snandc->qspi->mtd = mtd; 304 305 ecc_cfg->ecc_bytes_hw = 7; 306 ecc_cfg->spare_bytes = 4; 307 ecc_cfg->bbm_size = 1; 308 ecc_cfg->bch_enabled = true; 309 ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size; 310 311 ecc_cfg->steps = 4; 312 ecc_cfg->cw_data = 516; 313 ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes; 314 bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1; 315 316 mtd_set_ooblayout(mtd, &qcom_spi_ooblayout); 317 318 ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | 319 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) | 320 FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 1) | 321 FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) | 322 FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) | 323 FIELD_PREP(STATUS_BFR_READ, 0) | 324 FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) | 325 FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes); 326 327 ecc_cfg->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) | 328 FIELD_PREP(CS_ACTIVE_BSY, 0) | 329 FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) | 330 FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) | 331 FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) | 332 FIELD_PREP(WIDE_FLASH, 0) | 333 FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled); 334 335 ecc_cfg->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | 336 FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) | 337 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) | 338 FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0); 339 340 ecc_cfg->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) | 341 FIELD_PREP(CS_ACTIVE_BSY, 0) | 342 FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) | 343 FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) | 344 FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) | 345 FIELD_PREP(WIDE_FLASH, 0) | 346 FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1); 347 348 ecc_cfg->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_enabled) | 349 FIELD_PREP(ECC_SW_RESET, 0) | 350 FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) | 351 FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) | 352 FIELD_PREP(ECC_MODE_MASK, 0) | 353 FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw); 354 355 ecc_cfg->ecc_buf_cfg = FIELD_PREP(NUM_STEPS_MASK, 0x203); 356 ecc_cfg->clrflashstatus = FS_READY_BSY_N; 357 ecc_cfg->clrreadstatus = 0xc0; 358 359 conf->step_size = ecc_cfg->step_size; 360 conf->strength = ecc_cfg->strength; 361 362 snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET); 363 snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET); 364 365 dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n", 366 ecc_cfg->strength, ecc_cfg->step_size); 367 368 return 0; 369 370 err_free_ecc_cfg: 371 kfree(ecc_cfg); 372 return ret; 373 } 374 375 static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand) 376 { 377 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand); 378 379 kfree(ecc_cfg); 380 } 381 382 static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand, 383 struct nand_page_io_req *req) 384 { 385 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); 386 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand); 387 388 snandc->qspi->ecc = ecc_cfg; 389 snandc->qspi->raw_rw = false; 390 snandc->qspi->oob_rw = false; 391 snandc->qspi->page_rw = false; 392 393 if (req->datalen) 394 snandc->qspi->page_rw = true; 395 396 if (req->ooblen) 397 snandc->qspi->oob_rw = true; 398 399 if (req->mode == MTD_OPS_RAW) 400 snandc->qspi->raw_rw = true; 401 402 return 0; 403 } 404 405 static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand, 406 struct nand_page_io_req *req) 407 { 408 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); 409 struct mtd_info *mtd = nanddev_to_mtd(nand); 410 411 if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ) 412 return 0; 413 414 if (snandc->qspi->ecc_stats.failed) 415 mtd->ecc_stats.failed += snandc->qspi->ecc_stats.failed; 416 else 417 mtd->ecc_stats.corrected += snandc->qspi->ecc_stats.corrected; 418 419 if (snandc->qspi->ecc_stats.failed) 420 return -EBADMSG; 421 else 422 return snandc->qspi->ecc_stats.bitflips; 423 } 424 425 static struct nand_ecc_engine_ops qcom_spi_ecc_engine_ops_pipelined = { 426 .init_ctx = qcom_spi_ecc_init_ctx_pipelined, 427 .cleanup_ctx = qcom_spi_ecc_cleanup_ctx_pipelined, 428 .prepare_io_req = qcom_spi_ecc_prepare_io_req_pipelined, 429 .finish_io_req = qcom_spi_ecc_finish_io_req_pipelined, 430 }; 431 432 /* helper to configure location register values */ 433 static void qcom_spi_set_read_loc(struct qcom_nand_controller *snandc, int cw, int reg, 434 int cw_offset, int read_size, int is_last_read_loc) 435 { 436 int reg_base = NAND_READ_LOCATION_0; 437 int num_cw = snandc->qspi->num_cw; 438 439 if (cw == (num_cw - 1)) 440 reg_base = NAND_READ_LOCATION_LAST_CW_0; 441 442 reg_base += reg * 4; 443 444 if (cw == (num_cw - 1)) 445 return qcom_spi_set_read_loc_last(snandc, reg_base, cw_offset, 446 read_size, is_last_read_loc); 447 else 448 return qcom_spi_set_read_loc_first(snandc, reg_base, cw_offset, 449 read_size, is_last_read_loc); 450 } 451 452 static void 453 qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int cw) 454 { 455 __le32 *reg = &snandc->regs->read_location0; 456 int num_cw = snandc->qspi->num_cw; 457 458 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL); 459 if (cw == (num_cw - 1)) { 460 reg = &snandc->regs->read_location_last0; 461 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, 462 NAND_BAM_NEXT_SGL); 463 } 464 465 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); 466 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); 467 468 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0); 469 qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1, 470 NAND_BAM_NEXT_SGL); 471 } 472 473 static int qcom_spi_block_erase(struct qcom_nand_controller *snandc) 474 { 475 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 476 int ret; 477 478 snandc->buf_count = 0; 479 snandc->buf_start = 0; 480 qcom_clear_read_regs(snandc); 481 qcom_clear_bam_transaction(snandc); 482 483 snandc->regs->cmd = snandc->qspi->cmd; 484 snandc->regs->addr0 = snandc->qspi->addr1; 485 snandc->regs->addr1 = snandc->qspi->addr2; 486 snandc->regs->cfg0 = cpu_to_le32((ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) | 487 FIELD_PREP(CW_PER_PAGE_MASK, 0)); 488 snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw); 489 snandc->regs->exec = cpu_to_le32(1); 490 491 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); 492 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); 493 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); 494 495 ret = qcom_submit_descs(snandc); 496 if (ret) { 497 dev_err(snandc->dev, "failure to erase block\n"); 498 return ret; 499 } 500 501 return 0; 502 } 503 504 static void qcom_spi_config_single_cw_page_read(struct qcom_nand_controller *snandc, 505 bool use_ecc, int cw) 506 { 507 __le32 *reg = &snandc->regs->read_location0; 508 int num_cw = snandc->qspi->num_cw; 509 510 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); 511 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); 512 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, 513 NAND_ERASED_CW_DETECT_CFG, 1, 0); 514 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, 515 NAND_ERASED_CW_DETECT_CFG, 1, 516 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); 517 518 if (cw == (num_cw - 1)) { 519 reg = &snandc->regs->read_location_last0; 520 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, NAND_BAM_NEXT_SGL); 521 } 522 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); 523 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); 524 525 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 0); 526 } 527 528 static int qcom_spi_check_raw_flash_errors(struct qcom_nand_controller *snandc, int cw_cnt) 529 { 530 int i; 531 532 qcom_nandc_dev_to_mem(snandc, true); 533 534 for (i = 0; i < cw_cnt; i++) { 535 u32 flash = le32_to_cpu(snandc->reg_read_buf[i]); 536 537 if (flash & (FS_OP_ERR | FS_MPU_ERR)) 538 return -EIO; 539 } 540 541 return 0; 542 } 543 544 static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc, 545 const struct spi_mem_op *op) 546 { 547 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 548 struct mtd_info *mtd = snandc->qspi->mtd; 549 int size, ret = 0; 550 int col, bbpos; 551 u32 cfg0, cfg1, ecc_bch_cfg; 552 u32 num_cw = snandc->qspi->num_cw; 553 554 qcom_clear_bam_transaction(snandc); 555 qcom_clear_read_regs(snandc); 556 557 size = ecc_cfg->cw_size; 558 col = ecc_cfg->cw_size * (num_cw - 1); 559 560 memset(snandc->data_buffer, 0xff, size); 561 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col)); 562 snandc->regs->addr1 = snandc->qspi->addr2; 563 564 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) | 565 FIELD_PREP(CW_PER_PAGE_MASK, 0); 566 cfg1 = ecc_cfg->cfg1_raw; 567 ecc_bch_cfg = ECC_CFG_ECC_DISABLE; 568 569 snandc->regs->cmd = snandc->qspi->cmd; 570 snandc->regs->cfg0 = cpu_to_le32(cfg0); 571 snandc->regs->cfg1 = cpu_to_le32(cfg1); 572 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 573 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); 574 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); 575 snandc->regs->exec = cpu_to_le32(1); 576 577 qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1); 578 579 qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1); 580 581 qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0); 582 583 ret = qcom_submit_descs(snandc); 584 if (ret) { 585 dev_err(snandc->dev, "failed to read last cw\n"); 586 return ret; 587 } 588 589 ret = qcom_spi_check_raw_flash_errors(snandc, 1); 590 if (ret) 591 return ret; 592 593 bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); 594 595 if (snandc->data_buffer[bbpos] == 0xff) 596 snandc->data_buffer[bbpos + 1] = 0xff; 597 if (snandc->data_buffer[bbpos] != 0xff) 598 snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos]; 599 600 memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes); 601 602 return ret; 603 } 604 605 static int qcom_spi_check_error(struct qcom_nand_controller *snandc) 606 { 607 struct snandc_read_status *buf; 608 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 609 int i, num_cw = snandc->qspi->num_cw; 610 bool flash_op_err = false, erased; 611 unsigned int max_bitflips = 0; 612 unsigned int uncorrectable_cws = 0; 613 614 snandc->qspi->ecc_stats.failed = 0; 615 snandc->qspi->ecc_stats.corrected = 0; 616 617 qcom_nandc_dev_to_mem(snandc, true); 618 buf = (struct snandc_read_status *)snandc->reg_read_buf; 619 620 for (i = 0; i < num_cw; i++, buf++) { 621 u32 flash, buffer, erased_cw; 622 623 flash = le32_to_cpu(buf->snandc_flash); 624 buffer = le32_to_cpu(buf->snandc_buffer); 625 erased_cw = le32_to_cpu(buf->snandc_erased_cw); 626 627 if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) { 628 if (ecc_cfg->bch_enabled) 629 erased = (erased_cw & ERASED_CW) == ERASED_CW; 630 else 631 erased = false; 632 633 if (!erased) 634 uncorrectable_cws |= BIT(i); 635 636 } else if (flash & (FS_OP_ERR | FS_MPU_ERR)) { 637 flash_op_err = true; 638 } else { 639 unsigned int stat; 640 641 stat = buffer & BS_CORRECTABLE_ERR_MSK; 642 snandc->qspi->ecc_stats.corrected += stat; 643 max_bitflips = max(max_bitflips, stat); 644 } 645 } 646 647 if (flash_op_err) 648 return -EIO; 649 650 if (!uncorrectable_cws) 651 snandc->qspi->ecc_stats.bitflips = max_bitflips; 652 else 653 snandc->qspi->ecc_stats.failed++; 654 655 return 0; 656 } 657 658 static int qcom_spi_read_cw_raw(struct qcom_nand_controller *snandc, u8 *data_buf, 659 u8 *oob_buf, int cw) 660 { 661 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 662 struct mtd_info *mtd = snandc->qspi->mtd; 663 int data_size1, data_size2, oob_size1, oob_size2; 664 int ret, reg_off = FLASH_BUF_ACC, read_loc = 0; 665 int raw_cw = cw; 666 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw; 667 int col; 668 669 snandc->buf_count = 0; 670 snandc->buf_start = 0; 671 qcom_clear_read_regs(snandc); 672 qcom_clear_bam_transaction(snandc); 673 raw_cw = num_cw - 1; 674 675 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) | 676 FIELD_PREP(CW_PER_PAGE_MASK, 0); 677 cfg1 = ecc_cfg->cfg1_raw; 678 ecc_bch_cfg = ECC_CFG_ECC_DISABLE; 679 680 col = ecc_cfg->cw_size * cw; 681 682 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col)); 683 snandc->regs->addr1 = snandc->qspi->addr2; 684 snandc->regs->cmd = snandc->qspi->cmd; 685 snandc->regs->cfg0 = cpu_to_le32(cfg0); 686 snandc->regs->cfg1 = cpu_to_le32(cfg1); 687 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 688 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); 689 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); 690 snandc->regs->exec = cpu_to_le32(1); 691 692 qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1); 693 694 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); 695 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); 696 qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0); 697 698 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, 699 NAND_ERASED_CW_DETECT_CFG, 1, 0); 700 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, 701 NAND_ERASED_CW_DETECT_CFG, 1, 702 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); 703 704 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); 705 oob_size1 = ecc_cfg->bbm_size; 706 707 if (cw == (num_cw - 1)) { 708 data_size2 = NANDC_STEP_SIZE - data_size1 - 709 ((num_cw - 1) * 4); 710 oob_size2 = (num_cw * 4) + ecc_cfg->ecc_bytes_hw + 711 ecc_cfg->spare_bytes; 712 } else { 713 data_size2 = ecc_cfg->cw_data - data_size1; 714 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; 715 } 716 717 qcom_spi_set_read_loc(snandc, cw, 0, read_loc, data_size1, 0); 718 read_loc += data_size1; 719 720 qcom_spi_set_read_loc(snandc, cw, 1, read_loc, oob_size1, 0); 721 read_loc += oob_size1; 722 723 qcom_spi_set_read_loc(snandc, cw, 2, read_loc, data_size2, 0); 724 read_loc += data_size2; 725 726 qcom_spi_set_read_loc(snandc, cw, 3, read_loc, oob_size2, 1); 727 728 qcom_spi_config_cw_read(snandc, false, raw_cw); 729 730 qcom_read_data_dma(snandc, reg_off, data_buf, data_size1, 0); 731 reg_off += data_size1; 732 733 qcom_read_data_dma(snandc, reg_off, oob_buf, oob_size1, 0); 734 reg_off += oob_size1; 735 736 qcom_read_data_dma(snandc, reg_off, data_buf + data_size1, data_size2, 0); 737 reg_off += data_size2; 738 739 qcom_read_data_dma(snandc, reg_off, oob_buf + oob_size1, oob_size2, 0); 740 741 ret = qcom_submit_descs(snandc); 742 if (ret) { 743 dev_err(snandc->dev, "failure to read raw cw %d\n", cw); 744 return ret; 745 } 746 747 return qcom_spi_check_raw_flash_errors(snandc, 1); 748 } 749 750 static int qcom_spi_read_page_raw(struct qcom_nand_controller *snandc, 751 const struct spi_mem_op *op) 752 { 753 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 754 u8 *data_buf = NULL, *oob_buf = NULL; 755 int ret, cw; 756 u32 num_cw = snandc->qspi->num_cw; 757 758 if (snandc->qspi->page_rw) 759 data_buf = op->data.buf.in; 760 761 oob_buf = snandc->qspi->oob_buf; 762 memset(oob_buf, 0xff, OOB_BUF_SIZE); 763 764 for (cw = 0; cw < num_cw; cw++) { 765 ret = qcom_spi_read_cw_raw(snandc, data_buf, oob_buf, cw); 766 if (ret) 767 return ret; 768 769 if (data_buf) 770 data_buf += ecc_cfg->cw_data; 771 if (oob_buf) 772 oob_buf += ecc_cfg->bytes; 773 } 774 775 return 0; 776 } 777 778 static int qcom_spi_read_page_ecc(struct qcom_nand_controller *snandc, 779 const struct spi_mem_op *op) 780 { 781 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 782 u8 *data_buf = NULL, *oob_buf = NULL; 783 int ret, i; 784 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw; 785 786 data_buf = op->data.buf.in; 787 oob_buf = snandc->qspi->oob_buf; 788 789 snandc->buf_count = 0; 790 snandc->buf_start = 0; 791 qcom_clear_read_regs(snandc); 792 793 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) | 794 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1); 795 cfg1 = ecc_cfg->cfg1; 796 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; 797 798 snandc->regs->addr0 = snandc->qspi->addr1; 799 snandc->regs->addr1 = snandc->qspi->addr2; 800 snandc->regs->cmd = snandc->qspi->cmd; 801 snandc->regs->cfg0 = cpu_to_le32(cfg0); 802 snandc->regs->cfg1 = cpu_to_le32(cfg1); 803 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 804 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); 805 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); 806 snandc->regs->exec = cpu_to_le32(1); 807 808 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); 809 810 qcom_clear_bam_transaction(snandc); 811 812 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); 813 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); 814 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, 815 NAND_ERASED_CW_DETECT_CFG, 1, 0); 816 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, 817 NAND_ERASED_CW_DETECT_CFG, 1, 818 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); 819 820 for (i = 0; i < num_cw; i++) { 821 int data_size, oob_size; 822 823 if (i == (num_cw - 1)) { 824 data_size = 512 - ((num_cw - 1) << 2); 825 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + 826 ecc_cfg->spare_bytes; 827 } else { 828 data_size = ecc_cfg->cw_data; 829 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; 830 } 831 832 if (data_buf && oob_buf) { 833 qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 0); 834 qcom_spi_set_read_loc(snandc, i, 1, data_size, oob_size, 1); 835 } else if (data_buf) { 836 qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 1); 837 } else { 838 qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1); 839 } 840 841 qcom_spi_config_cw_read(snandc, true, i); 842 843 if (data_buf) 844 qcom_read_data_dma(snandc, FLASH_BUF_ACC, data_buf, 845 data_size, 0); 846 if (oob_buf) { 847 int j; 848 849 for (j = 0; j < ecc_cfg->bbm_size; j++) 850 *oob_buf++ = 0xff; 851 852 qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size, 853 oob_buf, oob_size, 0); 854 } 855 856 if (data_buf) 857 data_buf += data_size; 858 if (oob_buf) 859 oob_buf += oob_size; 860 } 861 862 ret = qcom_submit_descs(snandc); 863 if (ret) { 864 dev_err(snandc->dev, "failure to read page\n"); 865 return ret; 866 } 867 868 return qcom_spi_check_error(snandc); 869 } 870 871 static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc, 872 const struct spi_mem_op *op) 873 { 874 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 875 u8 *oob_buf = NULL; 876 int ret, i; 877 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw; 878 879 oob_buf = op->data.buf.in; 880 881 snandc->buf_count = 0; 882 snandc->buf_start = 0; 883 qcom_clear_read_regs(snandc); 884 qcom_clear_bam_transaction(snandc); 885 886 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) | 887 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1); 888 cfg1 = ecc_cfg->cfg1; 889 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; 890 891 snandc->regs->addr0 = snandc->qspi->addr1; 892 snandc->regs->addr1 = snandc->qspi->addr2; 893 snandc->regs->cmd = snandc->qspi->cmd; 894 snandc->regs->cfg0 = cpu_to_le32(cfg0); 895 snandc->regs->cfg1 = cpu_to_le32(cfg1); 896 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 897 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); 898 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); 899 snandc->regs->exec = cpu_to_le32(1); 900 901 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); 902 903 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); 904 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); 905 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, 906 NAND_ERASED_CW_DETECT_CFG, 1, 0); 907 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, 908 NAND_ERASED_CW_DETECT_CFG, 1, 909 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); 910 911 for (i = 0; i < num_cw; i++) { 912 int data_size, oob_size; 913 914 if (i == (num_cw - 1)) { 915 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); 916 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + 917 ecc_cfg->spare_bytes; 918 } else { 919 data_size = ecc_cfg->cw_data; 920 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; 921 } 922 923 qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1); 924 925 qcom_spi_config_cw_read(snandc, true, i); 926 927 if (oob_buf) { 928 int j; 929 930 for (j = 0; j < ecc_cfg->bbm_size; j++) 931 *oob_buf++ = 0xff; 932 933 qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size, 934 oob_buf, oob_size, 0); 935 } 936 937 if (oob_buf) 938 oob_buf += oob_size; 939 } 940 941 ret = qcom_submit_descs(snandc); 942 if (ret) { 943 dev_err(snandc->dev, "failure to read oob\n"); 944 return ret; 945 } 946 947 return qcom_spi_check_error(snandc); 948 } 949 950 static int qcom_spi_read_page(struct qcom_nand_controller *snandc, 951 const struct spi_mem_op *op) 952 { 953 if (snandc->qspi->page_rw && snandc->qspi->raw_rw) 954 return qcom_spi_read_page_raw(snandc, op); 955 956 if (snandc->qspi->page_rw) 957 return qcom_spi_read_page_ecc(snandc, op); 958 959 if (snandc->qspi->oob_rw && snandc->qspi->raw_rw) 960 return qcom_spi_read_last_cw(snandc, op); 961 962 if (snandc->qspi->oob_rw) 963 return qcom_spi_read_page_oob(snandc, op); 964 965 return 0; 966 } 967 968 static void qcom_spi_config_page_write(struct qcom_nand_controller *snandc) 969 { 970 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); 971 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); 972 qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 973 1, NAND_BAM_NEXT_SGL); 974 } 975 976 static void qcom_spi_config_cw_write(struct qcom_nand_controller *snandc) 977 { 978 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); 979 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); 980 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); 981 982 qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0); 983 qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS, 1, 984 NAND_BAM_NEXT_SGL); 985 } 986 987 static int qcom_spi_program_raw(struct qcom_nand_controller *snandc, 988 const struct spi_mem_op *op) 989 { 990 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 991 struct mtd_info *mtd = snandc->qspi->mtd; 992 u8 *data_buf = NULL, *oob_buf = NULL; 993 int i, ret; 994 int num_cw = snandc->qspi->num_cw; 995 u32 cfg0, cfg1, ecc_bch_cfg; 996 997 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) | 998 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1); 999 cfg1 = ecc_cfg->cfg1_raw; 1000 ecc_bch_cfg = ECC_CFG_ECC_DISABLE; 1001 1002 data_buf = snandc->qspi->data_buf; 1003 1004 oob_buf = snandc->qspi->oob_buf; 1005 memset(oob_buf, 0xff, OOB_BUF_SIZE); 1006 1007 snandc->buf_count = 0; 1008 snandc->buf_start = 0; 1009 qcom_clear_read_regs(snandc); 1010 qcom_clear_bam_transaction(snandc); 1011 1012 snandc->regs->addr0 = snandc->qspi->addr1; 1013 snandc->regs->addr1 = snandc->qspi->addr2; 1014 snandc->regs->cmd = snandc->qspi->cmd; 1015 snandc->regs->cfg0 = cpu_to_le32(cfg0); 1016 snandc->regs->cfg1 = cpu_to_le32(cfg1); 1017 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 1018 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); 1019 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); 1020 snandc->regs->exec = cpu_to_le32(1); 1021 1022 qcom_spi_config_page_write(snandc); 1023 1024 for (i = 0; i < num_cw; i++) { 1025 int data_size1, data_size2, oob_size1, oob_size2; 1026 int reg_off = FLASH_BUF_ACC; 1027 1028 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); 1029 oob_size1 = ecc_cfg->bbm_size; 1030 1031 if (i == (num_cw - 1)) { 1032 data_size2 = NANDC_STEP_SIZE - data_size1 - 1033 ((num_cw - 1) << 2); 1034 oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + 1035 ecc_cfg->spare_bytes; 1036 } else { 1037 data_size2 = ecc_cfg->cw_data - data_size1; 1038 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; 1039 } 1040 1041 qcom_write_data_dma(snandc, reg_off, data_buf, data_size1, 1042 NAND_BAM_NO_EOT); 1043 reg_off += data_size1; 1044 data_buf += data_size1; 1045 1046 qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size1, 1047 NAND_BAM_NO_EOT); 1048 oob_buf += oob_size1; 1049 reg_off += oob_size1; 1050 1051 qcom_write_data_dma(snandc, reg_off, data_buf, data_size2, 1052 NAND_BAM_NO_EOT); 1053 reg_off += data_size2; 1054 data_buf += data_size2; 1055 1056 qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size2, 0); 1057 oob_buf += oob_size2; 1058 1059 qcom_spi_config_cw_write(snandc); 1060 } 1061 1062 ret = qcom_submit_descs(snandc); 1063 if (ret) { 1064 dev_err(snandc->dev, "failure to write raw page\n"); 1065 return ret; 1066 } 1067 1068 return 0; 1069 } 1070 1071 static int qcom_spi_program_ecc(struct qcom_nand_controller *snandc, 1072 const struct spi_mem_op *op) 1073 { 1074 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 1075 u8 *data_buf = NULL, *oob_buf = NULL; 1076 int i, ret; 1077 int num_cw = snandc->qspi->num_cw; 1078 u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg; 1079 1080 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) | 1081 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1); 1082 cfg1 = ecc_cfg->cfg1; 1083 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; 1084 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg; 1085 1086 if (snandc->qspi->data_buf) 1087 data_buf = snandc->qspi->data_buf; 1088 1089 oob_buf = snandc->qspi->oob_buf; 1090 1091 snandc->buf_count = 0; 1092 snandc->buf_start = 0; 1093 qcom_clear_read_regs(snandc); 1094 qcom_clear_bam_transaction(snandc); 1095 1096 snandc->regs->addr0 = snandc->qspi->addr1; 1097 snandc->regs->addr1 = snandc->qspi->addr2; 1098 snandc->regs->cmd = snandc->qspi->cmd; 1099 snandc->regs->cfg0 = cpu_to_le32(cfg0); 1100 snandc->regs->cfg1 = cpu_to_le32(cfg1); 1101 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 1102 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg); 1103 snandc->regs->exec = cpu_to_le32(1); 1104 1105 qcom_spi_config_page_write(snandc); 1106 1107 for (i = 0; i < num_cw; i++) { 1108 int data_size, oob_size; 1109 1110 if (i == (num_cw - 1)) { 1111 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); 1112 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + 1113 ecc_cfg->spare_bytes; 1114 } else { 1115 data_size = ecc_cfg->cw_data; 1116 oob_size = ecc_cfg->bytes; 1117 } 1118 1119 if (data_buf) 1120 qcom_write_data_dma(snandc, FLASH_BUF_ACC, data_buf, data_size, 1121 i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0); 1122 1123 if (i == (num_cw - 1)) { 1124 if (oob_buf) { 1125 oob_buf += ecc_cfg->bbm_size; 1126 qcom_write_data_dma(snandc, FLASH_BUF_ACC + data_size, 1127 oob_buf, oob_size, 0); 1128 } 1129 } 1130 1131 qcom_spi_config_cw_write(snandc); 1132 1133 if (data_buf) 1134 data_buf += data_size; 1135 if (oob_buf) 1136 oob_buf += oob_size; 1137 } 1138 1139 ret = qcom_submit_descs(snandc); 1140 if (ret) { 1141 dev_err(snandc->dev, "failure to write page\n"); 1142 return ret; 1143 } 1144 1145 return 0; 1146 } 1147 1148 static int qcom_spi_program_oob(struct qcom_nand_controller *snandc, 1149 const struct spi_mem_op *op) 1150 { 1151 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 1152 u8 *oob_buf = NULL; 1153 int ret, col, data_size, oob_size; 1154 int num_cw = snandc->qspi->num_cw; 1155 u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg; 1156 1157 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) | 1158 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1); 1159 cfg1 = ecc_cfg->cfg1; 1160 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; 1161 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg; 1162 1163 col = ecc_cfg->cw_size * (num_cw - 1); 1164 1165 oob_buf = snandc->qspi->data_buf; 1166 1167 snandc->buf_count = 0; 1168 snandc->buf_start = 0; 1169 qcom_clear_read_regs(snandc); 1170 qcom_clear_bam_transaction(snandc); 1171 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col)); 1172 snandc->regs->addr1 = snandc->qspi->addr2; 1173 snandc->regs->cmd = snandc->qspi->cmd; 1174 snandc->regs->cfg0 = cpu_to_le32(cfg0); 1175 snandc->regs->cfg1 = cpu_to_le32(cfg1); 1176 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 1177 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg); 1178 snandc->regs->exec = cpu_to_le32(1); 1179 1180 /* calculate the data and oob size for the last codeword/step */ 1181 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); 1182 oob_size = snandc->qspi->mtd->oobavail; 1183 1184 memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data); 1185 /* override new oob content to last codeword */ 1186 mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data_size, 1187 oob_buf, 0, snandc->qspi->mtd->oobavail); 1188 qcom_spi_config_page_write(snandc); 1189 qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size + oob_size, 0); 1190 qcom_spi_config_cw_write(snandc); 1191 1192 ret = qcom_submit_descs(snandc); 1193 if (ret) { 1194 dev_err(snandc->dev, "failure to write oob\n"); 1195 return ret; 1196 } 1197 1198 return 0; 1199 } 1200 1201 static int qcom_spi_program_execute(struct qcom_nand_controller *snandc, 1202 const struct spi_mem_op *op) 1203 { 1204 if (snandc->qspi->page_rw && snandc->qspi->raw_rw) 1205 return qcom_spi_program_raw(snandc, op); 1206 1207 if (snandc->qspi->page_rw) 1208 return qcom_spi_program_ecc(snandc, op); 1209 1210 if (snandc->qspi->oob_rw) 1211 return qcom_spi_program_oob(snandc, op); 1212 1213 return 0; 1214 } 1215 1216 static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, u32 *cmd) 1217 { 1218 switch (opcode) { 1219 case SPINAND_RESET: 1220 *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE); 1221 break; 1222 case SPINAND_READID: 1223 *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID); 1224 break; 1225 case SPINAND_GET_FEATURE: 1226 *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE); 1227 break; 1228 case SPINAND_SET_FEATURE: 1229 *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE | 1230 QPIC_SET_FEATURE); 1231 break; 1232 case SPINAND_READ: 1233 if (snandc->qspi->raw_rw) { 1234 *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | 1235 SPI_WP | SPI_HOLD | OP_PAGE_READ); 1236 } else { 1237 *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | 1238 SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC); 1239 } 1240 1241 break; 1242 case SPINAND_ERASE: 1243 *cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP | 1244 SPI_HOLD | SPI_TRANSFER_MODE_x1; 1245 break; 1246 case SPINAND_WRITE_EN: 1247 *cmd = SPINAND_WRITE_EN; 1248 break; 1249 case SPINAND_PROGRAM_EXECUTE: 1250 *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | 1251 SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE); 1252 break; 1253 case SPINAND_PROGRAM_LOAD: 1254 *cmd = SPINAND_PROGRAM_LOAD; 1255 break; 1256 default: 1257 dev_err(snandc->dev, "Opcode not supported: %u\n", opcode); 1258 return -EOPNOTSUPP; 1259 } 1260 1261 return 0; 1262 } 1263 1264 static int qcom_spi_write_page(struct qcom_nand_controller *snandc, 1265 const struct spi_mem_op *op) 1266 { 1267 int ret; 1268 u32 cmd; 1269 1270 ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); 1271 if (ret < 0) 1272 return ret; 1273 1274 if (op->cmd.opcode == SPINAND_PROGRAM_LOAD) 1275 snandc->qspi->data_buf = (u8 *)op->data.buf.out; 1276 1277 return 0; 1278 } 1279 1280 static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc, 1281 const struct spi_mem_op *op) 1282 { 1283 struct qpic_snand_op s_op = {}; 1284 u32 cmd; 1285 int ret, opcode; 1286 1287 ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); 1288 if (ret < 0) 1289 return ret; 1290 1291 s_op.cmd_reg = cmd; 1292 s_op.addr1_reg = op->addr.val; 1293 s_op.addr2_reg = 0; 1294 1295 opcode = op->cmd.opcode; 1296 1297 switch (opcode) { 1298 case SPINAND_WRITE_EN: 1299 return 0; 1300 case SPINAND_PROGRAM_EXECUTE: 1301 s_op.addr1_reg = op->addr.val << 16; 1302 s_op.addr2_reg = op->addr.val >> 16 & 0xff; 1303 snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg); 1304 snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg); 1305 snandc->qspi->cmd = cpu_to_le32(cmd); 1306 return qcom_spi_program_execute(snandc, op); 1307 case SPINAND_READ: 1308 s_op.addr1_reg = (op->addr.val << 16); 1309 s_op.addr2_reg = op->addr.val >> 16 & 0xff; 1310 snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg); 1311 snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg); 1312 snandc->qspi->cmd = cpu_to_le32(cmd); 1313 return 0; 1314 case SPINAND_ERASE: 1315 s_op.addr2_reg = (op->addr.val >> 16) & 0xffff; 1316 s_op.addr1_reg = op->addr.val; 1317 snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg << 16); 1318 snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg); 1319 snandc->qspi->cmd = cpu_to_le32(cmd); 1320 return qcom_spi_block_erase(snandc); 1321 default: 1322 break; 1323 } 1324 1325 snandc->buf_count = 0; 1326 snandc->buf_start = 0; 1327 qcom_clear_read_regs(snandc); 1328 qcom_clear_bam_transaction(snandc); 1329 1330 snandc->regs->cmd = cpu_to_le32(s_op.cmd_reg); 1331 snandc->regs->exec = cpu_to_le32(1); 1332 snandc->regs->addr0 = cpu_to_le32(s_op.addr1_reg); 1333 snandc->regs->addr1 = cpu_to_le32(s_op.addr2_reg); 1334 1335 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); 1336 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); 1337 1338 ret = qcom_submit_descs(snandc); 1339 if (ret) 1340 dev_err(snandc->dev, "failure in submitting cmd descriptor\n"); 1341 1342 return ret; 1343 } 1344 1345 static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struct spi_mem_op *op) 1346 { 1347 int ret, val, opcode; 1348 bool copy = false, copy_ftr = false; 1349 1350 ret = qcom_spi_send_cmdaddr(snandc, op); 1351 if (ret) 1352 return ret; 1353 1354 snandc->buf_count = 0; 1355 snandc->buf_start = 0; 1356 qcom_clear_read_regs(snandc); 1357 qcom_clear_bam_transaction(snandc); 1358 opcode = op->cmd.opcode; 1359 1360 switch (opcode) { 1361 case SPINAND_READID: 1362 snandc->buf_count = 4; 1363 qcom_read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); 1364 copy = true; 1365 break; 1366 case SPINAND_GET_FEATURE: 1367 snandc->buf_count = 4; 1368 qcom_read_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL); 1369 copy_ftr = true; 1370 break; 1371 case SPINAND_SET_FEATURE: 1372 snandc->regs->flash_feature = cpu_to_le32(*(u32 *)op->data.buf.out); 1373 qcom_write_reg_dma(snandc, &snandc->regs->flash_feature, 1374 NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL); 1375 break; 1376 case SPINAND_PROGRAM_EXECUTE: 1377 case SPINAND_WRITE_EN: 1378 case SPINAND_RESET: 1379 case SPINAND_ERASE: 1380 case SPINAND_READ: 1381 return 0; 1382 default: 1383 return -EOPNOTSUPP; 1384 } 1385 1386 ret = qcom_submit_descs(snandc); 1387 if (ret) { 1388 dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode); 1389 return ret; 1390 } 1391 1392 if (copy) { 1393 qcom_nandc_dev_to_mem(snandc, true); 1394 memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count); 1395 } 1396 1397 if (copy_ftr) { 1398 qcom_nandc_dev_to_mem(snandc, true); 1399 val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf); 1400 val >>= 8; 1401 memcpy(op->data.buf.in, &val, snandc->buf_count); 1402 } 1403 1404 return 0; 1405 } 1406 1407 static bool qcom_spi_is_page_op(const struct spi_mem_op *op) 1408 { 1409 if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4) 1410 return false; 1411 1412 if (op->data.dir == SPI_MEM_DATA_IN) { 1413 if (op->addr.buswidth == 4 && op->data.buswidth == 4) 1414 return true; 1415 1416 if (op->addr.nbytes == 2 && op->addr.buswidth == 1) 1417 return true; 1418 1419 } else if (op->data.dir == SPI_MEM_DATA_OUT) { 1420 if (op->data.buswidth == 4) 1421 return true; 1422 if (op->addr.nbytes == 2 && op->addr.buswidth == 1) 1423 return true; 1424 } 1425 1426 return false; 1427 } 1428 1429 static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) 1430 { 1431 if (!spi_mem_default_supports_op(mem, op)) 1432 return false; 1433 1434 if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1) 1435 return false; 1436 1437 if (qcom_spi_is_page_op(op)) 1438 return true; 1439 1440 return ((!op->addr.nbytes || op->addr.buswidth == 1) && 1441 (!op->dummy.nbytes || op->dummy.buswidth == 1) && 1442 (!op->data.nbytes || op->data.buswidth == 1)); 1443 } 1444 1445 static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 1446 { 1447 struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller); 1448 1449 dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode, 1450 op->addr.val, op->addr.buswidth, op->addr.nbytes, 1451 op->data.buswidth, op->data.nbytes); 1452 1453 if (qcom_spi_is_page_op(op)) { 1454 if (op->data.dir == SPI_MEM_DATA_IN) 1455 return qcom_spi_read_page(snandc, op); 1456 if (op->data.dir == SPI_MEM_DATA_OUT) 1457 return qcom_spi_write_page(snandc, op); 1458 } else { 1459 return qcom_spi_io_op(snandc, op); 1460 } 1461 1462 return 0; 1463 } 1464 1465 static const struct spi_controller_mem_ops qcom_spi_mem_ops = { 1466 .supports_op = qcom_spi_supports_op, 1467 .exec_op = qcom_spi_exec_op, 1468 }; 1469 1470 static const struct spi_controller_mem_caps qcom_spi_mem_caps = { 1471 .ecc = true, 1472 }; 1473 1474 static int qcom_spi_probe(struct platform_device *pdev) 1475 { 1476 struct device *dev = &pdev->dev; 1477 struct spi_controller *ctlr; 1478 struct qcom_nand_controller *snandc; 1479 struct qpic_spi_nand *qspi; 1480 struct qpic_ecc *ecc; 1481 struct resource *res; 1482 const void *dev_data; 1483 int ret; 1484 1485 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); 1486 if (!ecc) 1487 return -ENOMEM; 1488 1489 qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL); 1490 if (!qspi) 1491 return -ENOMEM; 1492 1493 ctlr = __devm_spi_alloc_controller(dev, sizeof(*snandc), false); 1494 if (!ctlr) 1495 return -ENOMEM; 1496 1497 platform_set_drvdata(pdev, ctlr); 1498 1499 snandc = spi_controller_get_devdata(ctlr); 1500 qspi->snandc = snandc; 1501 1502 snandc->dev = dev; 1503 snandc->qspi = qspi; 1504 snandc->qspi->ctlr = ctlr; 1505 snandc->qspi->ecc = ecc; 1506 1507 dev_data = of_device_get_match_data(dev); 1508 if (!dev_data) { 1509 dev_err(&pdev->dev, "failed to get device data\n"); 1510 return -ENODEV; 1511 } 1512 1513 snandc->props = dev_data; 1514 snandc->dev = &pdev->dev; 1515 1516 snandc->core_clk = devm_clk_get(dev, "core"); 1517 if (IS_ERR(snandc->core_clk)) 1518 return PTR_ERR(snandc->core_clk); 1519 1520 snandc->aon_clk = devm_clk_get(dev, "aon"); 1521 if (IS_ERR(snandc->aon_clk)) 1522 return PTR_ERR(snandc->aon_clk); 1523 1524 snandc->qspi->iomacro_clk = devm_clk_get(dev, "iom"); 1525 if (IS_ERR(snandc->qspi->iomacro_clk)) 1526 return PTR_ERR(snandc->qspi->iomacro_clk); 1527 1528 snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1529 if (IS_ERR(snandc->base)) 1530 return PTR_ERR(snandc->base); 1531 1532 snandc->base_phys = res->start; 1533 snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res), 1534 DMA_BIDIRECTIONAL, 0); 1535 if (dma_mapping_error(dev, snandc->base_dma)) 1536 return -ENXIO; 1537 1538 ret = clk_prepare_enable(snandc->core_clk); 1539 if (ret) 1540 goto err_dis_core_clk; 1541 1542 ret = clk_prepare_enable(snandc->aon_clk); 1543 if (ret) 1544 goto err_dis_aon_clk; 1545 1546 ret = clk_prepare_enable(snandc->qspi->iomacro_clk); 1547 if (ret) 1548 goto err_dis_iom_clk; 1549 1550 ret = qcom_nandc_alloc(snandc); 1551 if (ret) 1552 goto err_snand_alloc; 1553 1554 ret = qcom_spi_init(snandc); 1555 if (ret) 1556 goto err_spi_init; 1557 1558 /* setup ECC engine */ 1559 snandc->qspi->ecc_eng.dev = &pdev->dev; 1560 snandc->qspi->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED; 1561 snandc->qspi->ecc_eng.ops = &qcom_spi_ecc_engine_ops_pipelined; 1562 snandc->qspi->ecc_eng.priv = snandc; 1563 1564 ret = nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng); 1565 if (ret) { 1566 dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret); 1567 goto err_spi_init; 1568 } 1569 1570 ctlr->num_chipselect = QPIC_QSPI_NUM_CS; 1571 ctlr->mem_ops = &qcom_spi_mem_ops; 1572 ctlr->mem_caps = &qcom_spi_mem_caps; 1573 ctlr->dev.of_node = pdev->dev.of_node; 1574 ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL | 1575 SPI_TX_QUAD | SPI_RX_QUAD; 1576 1577 ret = spi_register_controller(ctlr); 1578 if (ret) { 1579 dev_err(&pdev->dev, "spi_register_controller failed.\n"); 1580 goto err_spi_init; 1581 } 1582 1583 return 0; 1584 1585 err_spi_init: 1586 qcom_nandc_unalloc(snandc); 1587 err_snand_alloc: 1588 clk_disable_unprepare(snandc->qspi->iomacro_clk); 1589 err_dis_iom_clk: 1590 clk_disable_unprepare(snandc->aon_clk); 1591 err_dis_aon_clk: 1592 clk_disable_unprepare(snandc->core_clk); 1593 err_dis_core_clk: 1594 dma_unmap_resource(dev, res->start, resource_size(res), 1595 DMA_BIDIRECTIONAL, 0); 1596 return ret; 1597 } 1598 1599 static void qcom_spi_remove(struct platform_device *pdev) 1600 { 1601 struct spi_controller *ctlr = platform_get_drvdata(pdev); 1602 struct qcom_nand_controller *snandc = spi_controller_get_devdata(ctlr); 1603 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1604 1605 spi_unregister_controller(ctlr); 1606 1607 qcom_nandc_unalloc(snandc); 1608 1609 clk_disable_unprepare(snandc->aon_clk); 1610 clk_disable_unprepare(snandc->core_clk); 1611 clk_disable_unprepare(snandc->qspi->iomacro_clk); 1612 1613 dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res), 1614 DMA_BIDIRECTIONAL, 0); 1615 } 1616 1617 static const struct qcom_nandc_props ipq9574_snandc_props = { 1618 .dev_cmd_reg_start = 0x7000, 1619 .bam_offset = 0x30000, 1620 .supports_bam = true, 1621 }; 1622 1623 static const struct of_device_id qcom_snandc_of_match[] = { 1624 { 1625 .compatible = "qcom,ipq9574-snand", 1626 .data = &ipq9574_snandc_props, 1627 }, 1628 {} 1629 }; 1630 MODULE_DEVICE_TABLE(of, qcom_snandc_of_match); 1631 1632 static struct platform_driver qcom_spi_driver = { 1633 .driver = { 1634 .name = "qcom_snand", 1635 .of_match_table = qcom_snandc_of_match, 1636 }, 1637 .probe = qcom_spi_probe, 1638 .remove = qcom_spi_remove, 1639 }; 1640 module_platform_driver(qcom_spi_driver); 1641 1642 MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores"); 1643 MODULE_AUTHOR("Md Sadre Alam <quic_mdalam@quicinc.com>"); 1644 MODULE_LICENSE("GPL"); 1645 1646