1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. 4 // http://www.samsung.com/ 5 // 6 // Exynos - CPU PMU(Power Management Unit) support 7 8 #include <linux/array_size.h> 9 #include <linux/arm-smccc.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/mfd/core.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 #include <linux/delay.h> 17 #include <linux/regmap.h> 18 19 #include <linux/soc/samsung/exynos-regs-pmu.h> 20 #include <linux/soc/samsung/exynos-pmu.h> 21 22 #include "exynos-pmu.h" 23 24 #define PMUALIVE_MASK GENMASK(13, 0) 25 #define TENSOR_SET_BITS (BIT(15) | BIT(14)) 26 #define TENSOR_CLR_BITS BIT(15) 27 #define TENSOR_SMC_PMU_SEC_REG 0x82000504 28 #define TENSOR_PMUREG_READ 0 29 #define TENSOR_PMUREG_WRITE 1 30 #define TENSOR_PMUREG_RMW 2 31 32 struct exynos_pmu_context { 33 struct device *dev; 34 const struct exynos_pmu_data *pmu_data; 35 struct regmap *pmureg; 36 }; 37 38 void __iomem *pmu_base_addr; 39 static struct exynos_pmu_context *pmu_context; 40 /* forward declaration */ 41 static struct platform_driver exynos_pmu_driver; 42 43 /* 44 * Tensor SoCs are configured so that PMU_ALIVE registers can only be written 45 * from EL3, but are still read accessible. As Linux needs to write some of 46 * these registers, the following functions are provided and exposed via 47 * regmap. 48 * 49 * Note: This SMC interface is known to be implemented on gs101 and derivative 50 * SoCs. 51 */ 52 53 /* Write to a protected PMU register. */ 54 static int tensor_sec_reg_write(void *context, unsigned int reg, 55 unsigned int val) 56 { 57 struct arm_smccc_res res; 58 unsigned long pmu_base = (unsigned long)context; 59 60 arm_smccc_smc(TENSOR_SMC_PMU_SEC_REG, pmu_base + reg, 61 TENSOR_PMUREG_WRITE, val, 0, 0, 0, 0, &res); 62 63 /* returns -EINVAL if access isn't allowed or 0 */ 64 if (res.a0) 65 pr_warn("%s(): SMC failed: %d\n", __func__, (int)res.a0); 66 67 return (int)res.a0; 68 } 69 70 /* Read/Modify/Write a protected PMU register. */ 71 static int tensor_sec_reg_rmw(void *context, unsigned int reg, 72 unsigned int mask, unsigned int val) 73 { 74 struct arm_smccc_res res; 75 unsigned long pmu_base = (unsigned long)context; 76 77 arm_smccc_smc(TENSOR_SMC_PMU_SEC_REG, pmu_base + reg, 78 TENSOR_PMUREG_RMW, mask, val, 0, 0, 0, &res); 79 80 /* returns -EINVAL if access isn't allowed or 0 */ 81 if (res.a0) 82 pr_warn("%s(): SMC failed: %d\n", __func__, (int)res.a0); 83 84 return (int)res.a0; 85 } 86 87 /* 88 * Read a protected PMU register. All PMU registers can be read by Linux. 89 * Note: The SMC read register is not used, as only registers that can be 90 * written are readable via SMC. 91 */ 92 static int tensor_sec_reg_read(void *context, unsigned int reg, 93 unsigned int *val) 94 { 95 *val = pmu_raw_readl(reg); 96 return 0; 97 } 98 99 /* 100 * For SoCs that have set/clear bit hardware this function can be used when 101 * the PMU register will be accessed by multiple masters. 102 * 103 * For example, to set bits 13:8 in PMU reg offset 0x3e80 104 * tensor_set_bits_atomic(ctx, 0x3e80, 0x3f00, 0x3f00); 105 * 106 * Set bit 8, and clear bits 13:9 PMU reg offset 0x3e80 107 * tensor_set_bits_atomic(0x3e80, 0x100, 0x3f00); 108 */ 109 static int tensor_set_bits_atomic(void *ctx, unsigned int offset, u32 val, 110 u32 mask) 111 { 112 int ret; 113 unsigned int i; 114 115 for (i = 0; i < 32; i++) { 116 if (!(mask & BIT(i))) 117 continue; 118 119 offset &= ~TENSOR_SET_BITS; 120 121 if (val & BIT(i)) 122 offset |= TENSOR_SET_BITS; 123 else 124 offset |= TENSOR_CLR_BITS; 125 126 ret = tensor_sec_reg_write(ctx, offset, i); 127 if (ret) 128 return ret; 129 } 130 return 0; 131 } 132 133 static bool tensor_is_atomic(unsigned int reg) 134 { 135 /* 136 * Use atomic operations for PMU_ALIVE registers (offset 0~0x3FFF) 137 * as the target registers can be accessed by multiple masters. SFRs 138 * that don't support atomic are added to the switch statement below. 139 */ 140 if (reg > PMUALIVE_MASK) 141 return false; 142 143 switch (reg) { 144 case GS101_SYSIP_DAT0: 145 case GS101_SYSTEM_CONFIGURATION: 146 return false; 147 default: 148 return true; 149 } 150 } 151 152 static int tensor_sec_update_bits(void *ctx, unsigned int reg, 153 unsigned int mask, unsigned int val) 154 { 155 156 if (!tensor_is_atomic(reg)) 157 return tensor_sec_reg_rmw(ctx, reg, mask, val); 158 159 return tensor_set_bits_atomic(ctx, reg, val, mask); 160 } 161 162 void pmu_raw_writel(u32 val, u32 offset) 163 { 164 writel_relaxed(val, pmu_base_addr + offset); 165 } 166 167 u32 pmu_raw_readl(u32 offset) 168 { 169 return readl_relaxed(pmu_base_addr + offset); 170 } 171 172 void exynos_sys_powerdown_conf(enum sys_powerdown mode) 173 { 174 unsigned int i; 175 const struct exynos_pmu_data *pmu_data; 176 177 if (!pmu_context || !pmu_context->pmu_data) 178 return; 179 180 pmu_data = pmu_context->pmu_data; 181 182 if (pmu_data->powerdown_conf) 183 pmu_data->powerdown_conf(mode); 184 185 if (pmu_data->pmu_config) { 186 for (i = 0; (pmu_data->pmu_config[i].offset != PMU_TABLE_END); i++) 187 pmu_raw_writel(pmu_data->pmu_config[i].val[mode], 188 pmu_data->pmu_config[i].offset); 189 } 190 191 if (pmu_data->powerdown_conf_extra) 192 pmu_data->powerdown_conf_extra(mode); 193 194 if (pmu_data->pmu_config_extra) { 195 for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++) 196 pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode], 197 pmu_data->pmu_config_extra[i].offset); 198 } 199 } 200 201 /* 202 * Split the data between ARM architectures because it is relatively big 203 * and useless on other arch. 204 */ 205 #ifdef CONFIG_EXYNOS_PMU_ARM_DRIVERS 206 #define exynos_pmu_data_arm_ptr(data) (&data) 207 #else 208 #define exynos_pmu_data_arm_ptr(data) NULL 209 #endif 210 211 static const struct regmap_config regmap_smccfg = { 212 .name = "pmu_regs", 213 .reg_bits = 32, 214 .reg_stride = 4, 215 .val_bits = 32, 216 .fast_io = true, 217 .use_single_read = true, 218 .use_single_write = true, 219 .reg_read = tensor_sec_reg_read, 220 .reg_write = tensor_sec_reg_write, 221 .reg_update_bits = tensor_sec_update_bits, 222 }; 223 224 static const struct exynos_pmu_data gs101_pmu_data = { 225 .pmu_secure = true 226 }; 227 228 /* 229 * PMU platform driver and devicetree bindings. 230 */ 231 static const struct of_device_id exynos_pmu_of_device_ids[] = { 232 { 233 .compatible = "google,gs101-pmu", 234 .data = &gs101_pmu_data, 235 }, { 236 .compatible = "samsung,exynos3250-pmu", 237 .data = exynos_pmu_data_arm_ptr(exynos3250_pmu_data), 238 }, { 239 .compatible = "samsung,exynos4210-pmu", 240 .data = exynos_pmu_data_arm_ptr(exynos4210_pmu_data), 241 }, { 242 .compatible = "samsung,exynos4212-pmu", 243 .data = exynos_pmu_data_arm_ptr(exynos4212_pmu_data), 244 }, { 245 .compatible = "samsung,exynos4412-pmu", 246 .data = exynos_pmu_data_arm_ptr(exynos4412_pmu_data), 247 }, { 248 .compatible = "samsung,exynos5250-pmu", 249 .data = exynos_pmu_data_arm_ptr(exynos5250_pmu_data), 250 }, { 251 .compatible = "samsung,exynos5410-pmu", 252 }, { 253 .compatible = "samsung,exynos5420-pmu", 254 .data = exynos_pmu_data_arm_ptr(exynos5420_pmu_data), 255 }, { 256 .compatible = "samsung,exynos5433-pmu", 257 }, { 258 .compatible = "samsung,exynos7-pmu", 259 }, { 260 .compatible = "samsung,exynos850-pmu", 261 }, 262 { /*sentinel*/ }, 263 }; 264 265 static const struct mfd_cell exynos_pmu_devs[] = { 266 { .name = "exynos-clkout", }, 267 }; 268 269 /** 270 * exynos_get_pmu_regmap() - Obtain pmureg regmap 271 * 272 * Find the pmureg regmap previously configured in probe() and return regmap 273 * pointer. 274 * 275 * Return: A pointer to regmap if found or ERR_PTR error value. 276 */ 277 struct regmap *exynos_get_pmu_regmap(void) 278 { 279 struct device_node *np = of_find_matching_node(NULL, 280 exynos_pmu_of_device_ids); 281 if (np) 282 return exynos_get_pmu_regmap_by_phandle(np, NULL); 283 return ERR_PTR(-ENODEV); 284 } 285 EXPORT_SYMBOL_GPL(exynos_get_pmu_regmap); 286 287 /** 288 * exynos_get_pmu_regmap_by_phandle() - Obtain pmureg regmap via phandle 289 * @np: Device node holding PMU phandle property 290 * @propname: Name of property holding phandle value 291 * 292 * Find the pmureg regmap previously configured in probe() and return regmap 293 * pointer. 294 * 295 * Return: A pointer to regmap if found or ERR_PTR error value. 296 */ 297 struct regmap *exynos_get_pmu_regmap_by_phandle(struct device_node *np, 298 const char *propname) 299 { 300 struct device_node *pmu_np; 301 struct device *dev; 302 303 if (propname) 304 pmu_np = of_parse_phandle(np, propname, 0); 305 else 306 pmu_np = np; 307 308 if (!pmu_np) 309 return ERR_PTR(-ENODEV); 310 311 /* 312 * Determine if exynos-pmu device has probed and therefore regmap 313 * has been created and can be returned to the caller. Otherwise we 314 * return -EPROBE_DEFER. 315 */ 316 dev = driver_find_device_by_of_node(&exynos_pmu_driver.driver, 317 (void *)pmu_np); 318 319 if (propname) 320 of_node_put(pmu_np); 321 322 if (!dev) 323 return ERR_PTR(-EPROBE_DEFER); 324 325 return syscon_node_to_regmap(pmu_np); 326 } 327 EXPORT_SYMBOL_GPL(exynos_get_pmu_regmap_by_phandle); 328 329 static int exynos_pmu_probe(struct platform_device *pdev) 330 { 331 struct device *dev = &pdev->dev; 332 struct regmap_config pmu_regmcfg; 333 struct regmap *regmap; 334 struct resource *res; 335 int ret; 336 337 pmu_base_addr = devm_platform_ioremap_resource(pdev, 0); 338 if (IS_ERR(pmu_base_addr)) 339 return PTR_ERR(pmu_base_addr); 340 341 pmu_context = devm_kzalloc(&pdev->dev, 342 sizeof(struct exynos_pmu_context), 343 GFP_KERNEL); 344 if (!pmu_context) 345 return -ENOMEM; 346 347 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 348 if (!res) 349 return -ENODEV; 350 351 pmu_context->pmu_data = of_device_get_match_data(dev); 352 353 /* For SoCs that secure PMU register writes use custom regmap */ 354 if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_secure) { 355 pmu_regmcfg = regmap_smccfg; 356 pmu_regmcfg.max_register = resource_size(res) - 357 pmu_regmcfg.reg_stride; 358 /* Need physical address for SMC call */ 359 regmap = devm_regmap_init(dev, NULL, 360 (void *)(uintptr_t)res->start, 361 &pmu_regmcfg); 362 363 if (IS_ERR(regmap)) 364 return dev_err_probe(&pdev->dev, PTR_ERR(regmap), 365 "regmap init failed\n"); 366 367 ret = of_syscon_register_regmap(dev->of_node, regmap); 368 if (ret) 369 return ret; 370 } else { 371 /* let syscon create mmio regmap */ 372 regmap = syscon_node_to_regmap(dev->of_node); 373 if (IS_ERR(regmap)) 374 return dev_err_probe(&pdev->dev, PTR_ERR(regmap), 375 "syscon_node_to_regmap failed\n"); 376 } 377 378 pmu_context->pmureg = regmap; 379 pmu_context->dev = dev; 380 381 if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_init) 382 pmu_context->pmu_data->pmu_init(); 383 384 platform_set_drvdata(pdev, pmu_context); 385 386 ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, exynos_pmu_devs, 387 ARRAY_SIZE(exynos_pmu_devs), NULL, 0, NULL); 388 if (ret) 389 return ret; 390 391 if (devm_of_platform_populate(dev)) 392 dev_err(dev, "Error populating children, reboot and poweroff might not work properly\n"); 393 394 dev_dbg(dev, "Exynos PMU Driver probe done\n"); 395 return 0; 396 } 397 398 static struct platform_driver exynos_pmu_driver = { 399 .driver = { 400 .name = "exynos-pmu", 401 .of_match_table = exynos_pmu_of_device_ids, 402 }, 403 .probe = exynos_pmu_probe, 404 }; 405 406 static int __init exynos_pmu_init(void) 407 { 408 return platform_driver_register(&exynos_pmu_driver); 409 410 } 411 postcore_initcall(exynos_pmu_init); 412