116a624a9SSascha Hauer /* 216a624a9SSascha Hauer * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de> 316a624a9SSascha Hauer * 416a624a9SSascha Hauer * This program is free software; you can redistribute it and/or modify 516a624a9SSascha Hauer * it under the terms of the GNU General Public License version 2 as 616a624a9SSascha Hauer * published by the Free Software Foundation. 716a624a9SSascha Hauer * 816a624a9SSascha Hauer * This program is distributed in the hope that it will be useful, 916a624a9SSascha Hauer * but WITHOUT ANY WARRANTY; without even the implied warranty of 1016a624a9SSascha Hauer * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1116a624a9SSascha Hauer * GNU General Public License for more details. 1216a624a9SSascha Hauer */ 1316a624a9SSascha Hauer 1416a624a9SSascha Hauer #include <linux/export.h> 1516a624a9SSascha Hauer #include <linux/jiffies.h> 1616a624a9SSascha Hauer #include <linux/regmap.h> 1716a624a9SSascha Hauer #include <linux/soc/mediatek/infracfg.h> 1816a624a9SSascha Hauer #include <asm/processor.h> 1916a624a9SSascha Hauer 20*090c6243SSean Wang #define MTK_POLL_DELAY_US 10 21*090c6243SSean Wang #define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ)) 22*090c6243SSean Wang 2316a624a9SSascha Hauer #define INFRA_TOPAXI_PROTECTEN 0x0220 2416a624a9SSascha Hauer #define INFRA_TOPAXI_PROTECTSTA1 0x0228 25fa7e843aSweiyi.lu@mediatek.com #define INFRA_TOPAXI_PROTECTEN_SET 0x0260 26fa7e843aSweiyi.lu@mediatek.com #define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 2716a624a9SSascha Hauer 2816a624a9SSascha Hauer /** 2916a624a9SSascha Hauer * mtk_infracfg_set_bus_protection - enable bus protection 3016a624a9SSascha Hauer * @regmap: The infracfg regmap 3116a624a9SSascha Hauer * @mask: The mask containing the protection bits to be enabled. 32fa7e843aSweiyi.lu@mediatek.com * @reg_update: The boolean flag determines to set the protection bits 33fa7e843aSweiyi.lu@mediatek.com * by regmap_update_bits with enable register(PROTECTEN) or 34fa7e843aSweiyi.lu@mediatek.com * by regmap_write with set register(PROTECTEN_SET). 3516a624a9SSascha Hauer * 3616a624a9SSascha Hauer * This function enables the bus protection bits for disabled power 3716a624a9SSascha Hauer * domains so that the system does not hang when some unit accesses the 3816a624a9SSascha Hauer * bus while in power down. 3916a624a9SSascha Hauer */ 40fa7e843aSweiyi.lu@mediatek.com int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, 41fa7e843aSweiyi.lu@mediatek.com bool reg_update) 4216a624a9SSascha Hauer { 4316a624a9SSascha Hauer u32 val; 4416a624a9SSascha Hauer int ret; 4516a624a9SSascha Hauer 46fa7e843aSweiyi.lu@mediatek.com if (reg_update) 47fa7e843aSweiyi.lu@mediatek.com regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 48fa7e843aSweiyi.lu@mediatek.com mask); 49fa7e843aSweiyi.lu@mediatek.com else 50fa7e843aSweiyi.lu@mediatek.com regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); 5116a624a9SSascha Hauer 52*090c6243SSean Wang ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, 53*090c6243SSean Wang val, (val & mask) == mask, 54*090c6243SSean Wang MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); 5516a624a9SSascha Hauer 5616a624a9SSascha Hauer return ret; 5716a624a9SSascha Hauer } 5816a624a9SSascha Hauer 5916a624a9SSascha Hauer /** 6016a624a9SSascha Hauer * mtk_infracfg_clear_bus_protection - disable bus protection 6116a624a9SSascha Hauer * @regmap: The infracfg regmap 6216a624a9SSascha Hauer * @mask: The mask containing the protection bits to be disabled. 63fa7e843aSweiyi.lu@mediatek.com * @reg_update: The boolean flag determines to clear the protection bits 64fa7e843aSweiyi.lu@mediatek.com * by regmap_update_bits with enable register(PROTECTEN) or 65fa7e843aSweiyi.lu@mediatek.com * by regmap_write with clear register(PROTECTEN_CLR). 6616a624a9SSascha Hauer * 6716a624a9SSascha Hauer * This function disables the bus protection bits previously enabled with 6816a624a9SSascha Hauer * mtk_infracfg_set_bus_protection. 6916a624a9SSascha Hauer */ 70fa7e843aSweiyi.lu@mediatek.com 71fa7e843aSweiyi.lu@mediatek.com int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, 72fa7e843aSweiyi.lu@mediatek.com bool reg_update) 7316a624a9SSascha Hauer { 7416a624a9SSascha Hauer int ret; 75*090c6243SSean Wang u32 val; 7616a624a9SSascha Hauer 77fa7e843aSweiyi.lu@mediatek.com if (reg_update) 7816a624a9SSascha Hauer regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); 79fa7e843aSweiyi.lu@mediatek.com else 80fa7e843aSweiyi.lu@mediatek.com regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); 8116a624a9SSascha Hauer 82*090c6243SSean Wang ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, 83*090c6243SSean Wang val, !(val & mask), 84*090c6243SSean Wang MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); 8516a624a9SSascha Hauer 8616a624a9SSascha Hauer return ret; 8716a624a9SSascha Hauer } 88