1*dfb99b05SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2*dfb99b05SThomas Gleixner /* Copyright 2014 Cisco Systems, Inc. All rights reserved. */ 3c8806b6cSNarsimhulu Musini 4c8806b6cSNarsimhulu Musini #ifndef _SNIC_IO_H 5c8806b6cSNarsimhulu Musini #define _SNIC_IO_H 6c8806b6cSNarsimhulu Musini 7c8806b6cSNarsimhulu Musini #define SNIC_DFLT_SG_DESC_CNT 32 /* Default descriptors for sgl */ 8c8806b6cSNarsimhulu Musini #define SNIC_MAX_SG_DESC_CNT 60 /* Max descriptor for sgl */ 9c8806b6cSNarsimhulu Musini #define SNIC_SG_DESC_ALIGN 16 /* Descriptor address alignment */ 10c8806b6cSNarsimhulu Musini 11c8806b6cSNarsimhulu Musini /* SG descriptor for snic */ 12c8806b6cSNarsimhulu Musini struct snic_sg_desc { 13c8806b6cSNarsimhulu Musini __le64 addr; 14c8806b6cSNarsimhulu Musini __le32 len; 15c8806b6cSNarsimhulu Musini u32 _resvd; 16c8806b6cSNarsimhulu Musini }; 17c8806b6cSNarsimhulu Musini 18c8806b6cSNarsimhulu Musini struct snic_dflt_sgl { 19c8806b6cSNarsimhulu Musini struct snic_sg_desc sg_desc[SNIC_DFLT_SG_DESC_CNT]; 20c8806b6cSNarsimhulu Musini }; 21c8806b6cSNarsimhulu Musini 22c8806b6cSNarsimhulu Musini struct snic_max_sgl { 23c8806b6cSNarsimhulu Musini struct snic_sg_desc sg_desc[SNIC_MAX_SG_DESC_CNT]; 24c8806b6cSNarsimhulu Musini }; 25c8806b6cSNarsimhulu Musini 26c8806b6cSNarsimhulu Musini enum snic_req_cache_type { 27c8806b6cSNarsimhulu Musini SNIC_REQ_CACHE_DFLT_SGL = 0, /* cache with default size sgl */ 28c8806b6cSNarsimhulu Musini SNIC_REQ_CACHE_MAX_SGL, /* cache with max size sgl */ 29c8806b6cSNarsimhulu Musini SNIC_REQ_TM_CACHE, /* cache for task mgmt reqs contains 30c8806b6cSNarsimhulu Musini snic_host_req objects only*/ 31c8806b6cSNarsimhulu Musini SNIC_REQ_MAX_CACHES /* number of sgl caches */ 32c8806b6cSNarsimhulu Musini }; 33c8806b6cSNarsimhulu Musini 34c8806b6cSNarsimhulu Musini /* Per IO internal state */ 35c8806b6cSNarsimhulu Musini struct snic_internal_io_state { 36c8806b6cSNarsimhulu Musini char *rqi; 37c8806b6cSNarsimhulu Musini u64 flags; 38c8806b6cSNarsimhulu Musini u32 state; 39c8806b6cSNarsimhulu Musini u32 abts_status; /* Abort completion status */ 40c8806b6cSNarsimhulu Musini u32 lr_status; /* device reset completion status */ 41c8806b6cSNarsimhulu Musini }; 42c8806b6cSNarsimhulu Musini 43c8806b6cSNarsimhulu Musini /* IO state machine */ 44c8806b6cSNarsimhulu Musini enum snic_ioreq_state { 45c8806b6cSNarsimhulu Musini SNIC_IOREQ_NOT_INITED = 0, 46c8806b6cSNarsimhulu Musini SNIC_IOREQ_PENDING, 47c8806b6cSNarsimhulu Musini SNIC_IOREQ_ABTS_PENDING, 48c8806b6cSNarsimhulu Musini SNIC_IOREQ_ABTS_COMPLETE, 49c8806b6cSNarsimhulu Musini SNIC_IOREQ_LR_PENDING, 50c8806b6cSNarsimhulu Musini SNIC_IOREQ_LR_COMPLETE, 51c8806b6cSNarsimhulu Musini SNIC_IOREQ_COMPLETE, 52c8806b6cSNarsimhulu Musini }; 53c8806b6cSNarsimhulu Musini 54c8806b6cSNarsimhulu Musini struct snic; 55c8806b6cSNarsimhulu Musini struct snic_host_req; 56c8806b6cSNarsimhulu Musini 57c8806b6cSNarsimhulu Musini /* 58c8806b6cSNarsimhulu Musini * snic_req_info : Contains info about IO, one per scsi command. 59c8806b6cSNarsimhulu Musini * Notes: Make sure that the structure is aligned to 16 B 60c8806b6cSNarsimhulu Musini * this helps in easy access to snic_req_info from snic_host_req 61c8806b6cSNarsimhulu Musini */ 62c8806b6cSNarsimhulu Musini struct snic_req_info { 63c8806b6cSNarsimhulu Musini struct list_head list; 64c8806b6cSNarsimhulu Musini struct snic_host_req *req; 65c8806b6cSNarsimhulu Musini u64 start_time; /* start time in jiffies */ 66c8806b6cSNarsimhulu Musini u16 rq_pool_type; /* noticion of request pool type */ 67c8806b6cSNarsimhulu Musini u16 req_len; /* buf len passing to fw (req + sgl)*/ 68c8806b6cSNarsimhulu Musini u32 tgt_id; 69c8806b6cSNarsimhulu Musini 70c8806b6cSNarsimhulu Musini u32 tm_tag; 71c8806b6cSNarsimhulu Musini u8 io_cmpl:1; /* sets to 1 when fw completes IO */ 72c8806b6cSNarsimhulu Musini u8 resvd[3]; 73c8806b6cSNarsimhulu Musini struct scsi_cmnd *sc; /* Associated scsi cmd */ 74c8806b6cSNarsimhulu Musini struct snic *snic; /* Associated snic */ 75c8806b6cSNarsimhulu Musini ulong sge_va; /* Pointer to Resp Buffer */ 76c8806b6cSNarsimhulu Musini u64 snsbuf_va; 77c8806b6cSNarsimhulu Musini 78c8806b6cSNarsimhulu Musini struct snic_host_req *abort_req; 79c8806b6cSNarsimhulu Musini struct completion *abts_done; 80c8806b6cSNarsimhulu Musini 81c8806b6cSNarsimhulu Musini struct snic_host_req *dr_req; 82c8806b6cSNarsimhulu Musini struct completion *dr_done; 83c8806b6cSNarsimhulu Musini }; 84c8806b6cSNarsimhulu Musini 85c8806b6cSNarsimhulu Musini 86c8806b6cSNarsimhulu Musini #define rqi_to_req(rqi) \ 87c8806b6cSNarsimhulu Musini ((struct snic_host_req *) (((struct snic_req_info *)rqi)->req)) 88c8806b6cSNarsimhulu Musini 89c8806b6cSNarsimhulu Musini #define req_to_rqi(req) \ 90c8806b6cSNarsimhulu Musini ((struct snic_req_info *) (((struct snic_host_req *)req)->hdr.init_ctx)) 91c8806b6cSNarsimhulu Musini 92c8806b6cSNarsimhulu Musini #define req_to_sgl(req) \ 93c8806b6cSNarsimhulu Musini ((struct snic_sg_desc *) (((struct snic_host_req *)req)+1)) 94c8806b6cSNarsimhulu Musini 95c8806b6cSNarsimhulu Musini struct snic_req_info * 96c8806b6cSNarsimhulu Musini snic_req_init(struct snic *, int sg_cnt); 97c8806b6cSNarsimhulu Musini void snic_req_free(struct snic *, struct snic_req_info *); 98c8806b6cSNarsimhulu Musini void snic_calc_io_process_time(struct snic *, struct snic_req_info *); 99c8806b6cSNarsimhulu Musini void snic_pci_unmap_rsp_buf(struct snic *, struct snic_req_info *); 100c8806b6cSNarsimhulu Musini struct snic_host_req * 101c8806b6cSNarsimhulu Musini snic_abort_req_init(struct snic *, struct snic_req_info *); 102c8806b6cSNarsimhulu Musini struct snic_host_req * 103c8806b6cSNarsimhulu Musini snic_dr_req_init(struct snic *, struct snic_req_info *); 104c8806b6cSNarsimhulu Musini #endif /* _SNIC_IO_H */ 105