1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/delay.h> 8 #include <linux/devm-helpers.h> 9 #include <linux/err.h> 10 #include <linux/kernel.h> 11 #include <linux/interrupt.h> 12 #include <linux/bitops.h> 13 #include <linux/slab.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/ktime.h> 18 #include <linux/regulator/driver.h> 19 #include <linux/regmap.h> 20 #include <linux/list.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/io.h> 23 24 /* Pin control enable input pins. */ 25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00 26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01 27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02 28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04 29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08 30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10 31 32 /* Pin control high power mode input pins. */ 33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00 34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01 35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02 36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04 37 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN3 0x08 38 #define SPMI_REGULATOR_PIN_CTRL_HPM_SLEEP_B 0x10 39 #define SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT 0x20 40 41 /* 42 * Used with enable parameters to specify that hardware default register values 43 * should be left unaltered. 44 */ 45 #define SPMI_REGULATOR_USE_HW_DEFAULT 2 46 47 /* Soft start strength of a voltage switch type regulator */ 48 enum spmi_vs_soft_start_str { 49 SPMI_VS_SOFT_START_STR_0P05_UA = 0, 50 SPMI_VS_SOFT_START_STR_0P25_UA, 51 SPMI_VS_SOFT_START_STR_0P55_UA, 52 SPMI_VS_SOFT_START_STR_0P75_UA, 53 SPMI_VS_SOFT_START_STR_HW_DEFAULT, 54 }; 55 56 /** 57 * struct spmi_regulator_init_data - spmi-regulator initialization data 58 * @pin_ctrl_enable: Bit mask specifying which hardware pins should be 59 * used to enable the regulator, if any 60 * Value should be an ORing of 61 * SPMI_REGULATOR_PIN_CTRL_ENABLE_* constants. If 62 * the bit specified by 63 * SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT is 64 * set, then pin control enable hardware registers 65 * will not be modified. 66 * @pin_ctrl_hpm: Bit mask specifying which hardware pins should be 67 * used to force the regulator into high power 68 * mode, if any 69 * Value should be an ORing of 70 * SPMI_REGULATOR_PIN_CTRL_HPM_* constants. If 71 * the bit specified by 72 * SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT is 73 * set, then pin control mode hardware registers 74 * will not be modified. 75 * @vs_soft_start_strength: This parameter sets the soft start strength for 76 * voltage switch type regulators. Its value 77 * should be one of SPMI_VS_SOFT_START_STR_*. If 78 * its value is SPMI_VS_SOFT_START_STR_HW_DEFAULT, 79 * then the soft start strength will be left at its 80 * default hardware value. 81 */ 82 struct spmi_regulator_init_data { 83 unsigned pin_ctrl_enable; 84 unsigned pin_ctrl_hpm; 85 enum spmi_vs_soft_start_str vs_soft_start_strength; 86 }; 87 88 /* These types correspond to unique register layouts. */ 89 enum spmi_regulator_logical_type { 90 SPMI_REGULATOR_LOGICAL_TYPE_SMPS, 91 SPMI_REGULATOR_LOGICAL_TYPE_LDO, 92 SPMI_REGULATOR_LOGICAL_TYPE_VS, 93 SPMI_REGULATOR_LOGICAL_TYPE_BOOST, 94 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS, 95 SPMI_REGULATOR_LOGICAL_TYPE_BOOST_BYP, 96 SPMI_REGULATOR_LOGICAL_TYPE_LN_LDO, 97 SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS, 98 SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS, 99 SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO, 100 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426, 101 SPMI_REGULATOR_LOGICAL_TYPE_HFS430, 102 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3, 103 SPMI_REGULATOR_LOGICAL_TYPE_LDO_510, 104 SPMI_REGULATOR_LOGICAL_TYPE_HFSMPS, 105 }; 106 107 enum spmi_regulator_type { 108 SPMI_REGULATOR_TYPE_BUCK = 0x03, 109 SPMI_REGULATOR_TYPE_LDO = 0x04, 110 SPMI_REGULATOR_TYPE_VS = 0x05, 111 SPMI_REGULATOR_TYPE_BOOST = 0x1b, 112 SPMI_REGULATOR_TYPE_FTS = 0x1c, 113 SPMI_REGULATOR_TYPE_BOOST_BYP = 0x1f, 114 SPMI_REGULATOR_TYPE_ULT_LDO = 0x21, 115 SPMI_REGULATOR_TYPE_ULT_BUCK = 0x22, 116 }; 117 118 enum spmi_regulator_subtype { 119 SPMI_REGULATOR_SUBTYPE_GP_CTL = 0x08, 120 SPMI_REGULATOR_SUBTYPE_RF_CTL = 0x09, 121 SPMI_REGULATOR_SUBTYPE_N50 = 0x01, 122 SPMI_REGULATOR_SUBTYPE_N150 = 0x02, 123 SPMI_REGULATOR_SUBTYPE_N300 = 0x03, 124 SPMI_REGULATOR_SUBTYPE_N600 = 0x04, 125 SPMI_REGULATOR_SUBTYPE_N1200 = 0x05, 126 SPMI_REGULATOR_SUBTYPE_N600_ST = 0x06, 127 SPMI_REGULATOR_SUBTYPE_N1200_ST = 0x07, 128 SPMI_REGULATOR_SUBTYPE_N900_ST = 0x14, 129 SPMI_REGULATOR_SUBTYPE_N300_ST = 0x15, 130 SPMI_REGULATOR_SUBTYPE_P50 = 0x08, 131 SPMI_REGULATOR_SUBTYPE_P150 = 0x09, 132 SPMI_REGULATOR_SUBTYPE_P300 = 0x0a, 133 SPMI_REGULATOR_SUBTYPE_P600 = 0x0b, 134 SPMI_REGULATOR_SUBTYPE_P1200 = 0x0c, 135 SPMI_REGULATOR_SUBTYPE_LN = 0x10, 136 SPMI_REGULATOR_SUBTYPE_LV_P50 = 0x28, 137 SPMI_REGULATOR_SUBTYPE_LV_P150 = 0x29, 138 SPMI_REGULATOR_SUBTYPE_LV_P300 = 0x2a, 139 SPMI_REGULATOR_SUBTYPE_LV_P600 = 0x2b, 140 SPMI_REGULATOR_SUBTYPE_LV_P1200 = 0x2c, 141 SPMI_REGULATOR_SUBTYPE_LV_P450 = 0x2d, 142 SPMI_REGULATOR_SUBTYPE_HT_N300_ST = 0x30, 143 SPMI_REGULATOR_SUBTYPE_HT_N600_ST = 0x31, 144 SPMI_REGULATOR_SUBTYPE_HT_N1200_ST = 0x32, 145 SPMI_REGULATOR_SUBTYPE_HT_LVP150 = 0x3b, 146 SPMI_REGULATOR_SUBTYPE_HT_LVP300 = 0x3c, 147 SPMI_REGULATOR_SUBTYPE_L660_N300_ST = 0x42, 148 SPMI_REGULATOR_SUBTYPE_L660_N600_ST = 0x43, 149 SPMI_REGULATOR_SUBTYPE_L660_P50 = 0x46, 150 SPMI_REGULATOR_SUBTYPE_L660_P150 = 0x47, 151 SPMI_REGULATOR_SUBTYPE_L660_P600 = 0x49, 152 SPMI_REGULATOR_SUBTYPE_L660_LVP150 = 0x4d, 153 SPMI_REGULATOR_SUBTYPE_L660_LVP600 = 0x4f, 154 SPMI_REGULATOR_SUBTYPE_LV100 = 0x01, 155 SPMI_REGULATOR_SUBTYPE_LV300 = 0x02, 156 SPMI_REGULATOR_SUBTYPE_MV300 = 0x08, 157 SPMI_REGULATOR_SUBTYPE_MV500 = 0x09, 158 SPMI_REGULATOR_SUBTYPE_HDMI = 0x10, 159 SPMI_REGULATOR_SUBTYPE_OTG = 0x11, 160 SPMI_REGULATOR_SUBTYPE_5V_BOOST = 0x01, 161 SPMI_REGULATOR_SUBTYPE_FTS_CTL = 0x08, 162 SPMI_REGULATOR_SUBTYPE_FTS2p5_CTL = 0x09, 163 SPMI_REGULATOR_SUBTYPE_FTS426_CTL = 0x0a, 164 SPMI_REGULATOR_SUBTYPE_BB_2A = 0x01, 165 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1 = 0x0d, 166 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 0x0e, 167 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f, 168 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, 169 SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, 170 SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35, 171 SPMI_REGULATOR_SUBTYPE_HT_P600 = 0x3d, 172 SPMI_REGULATOR_SUBTYPE_HFSMPS_510 = 0x0a, 173 SPMI_REGULATOR_SUBTYPE_FTSMPS_510 = 0x0b, 174 SPMI_REGULATOR_SUBTYPE_LV_P150_510 = 0x71, 175 SPMI_REGULATOR_SUBTYPE_LV_P300_510 = 0x72, 176 SPMI_REGULATOR_SUBTYPE_LV_P600_510 = 0x73, 177 SPMI_REGULATOR_SUBTYPE_N300_510 = 0x6a, 178 SPMI_REGULATOR_SUBTYPE_N600_510 = 0x6b, 179 SPMI_REGULATOR_SUBTYPE_N1200_510 = 0x6c, 180 SPMI_REGULATOR_SUBTYPE_MV_P50_510 = 0x7a, 181 SPMI_REGULATOR_SUBTYPE_MV_P150_510 = 0x7b, 182 SPMI_REGULATOR_SUBTYPE_MV_P600_510 = 0x7d, 183 }; 184 185 enum spmi_common_regulator_registers { 186 SPMI_COMMON_REG_DIG_MAJOR_REV = 0x01, 187 SPMI_COMMON_REG_TYPE = 0x04, 188 SPMI_COMMON_REG_SUBTYPE = 0x05, 189 SPMI_COMMON_REG_VOLTAGE_RANGE = 0x40, 190 SPMI_COMMON_REG_VOLTAGE_SET = 0x41, 191 SPMI_COMMON_REG_MODE = 0x45, 192 SPMI_COMMON_REG_ENABLE = 0x46, 193 SPMI_COMMON_REG_PULL_DOWN = 0x48, 194 SPMI_COMMON_REG_SOFT_START = 0x4c, 195 SPMI_COMMON_REG_STEP_CTRL = 0x61, 196 }; 197 198 /* 199 * Second common register layout used by newer devices starting with ftsmps426 200 * Note that some of the registers from the first common layout remain 201 * unchanged and their definition is not duplicated. 202 */ 203 enum spmi_ftsmps426_regulator_registers { 204 SPMI_FTSMPS426_REG_VOLTAGE_LSB = 0x40, 205 SPMI_FTSMPS426_REG_VOLTAGE_MSB = 0x41, 206 SPMI_FTSMPS426_REG_VOLTAGE_ULS_LSB = 0x68, 207 SPMI_FTSMPS426_REG_VOLTAGE_ULS_MSB = 0x69, 208 }; 209 210 /* 211 * Third common register layout 212 */ 213 enum spmi_hfsmps_regulator_registers { 214 SPMI_HFSMPS_REG_STEP_CTRL = 0x3c, 215 SPMI_HFSMPS_REG_PULL_DOWN = 0xa0, 216 }; 217 218 enum spmi_vs_registers { 219 SPMI_VS_REG_OCP = 0x4a, 220 SPMI_VS_REG_SOFT_START = 0x4c, 221 }; 222 223 enum spmi_boost_registers { 224 SPMI_BOOST_REG_CURRENT_LIMIT = 0x4a, 225 }; 226 227 enum spmi_boost_byp_registers { 228 SPMI_BOOST_BYP_REG_CURRENT_LIMIT = 0x4b, 229 }; 230 231 enum spmi_saw3_registers { 232 SAW3_SECURE = 0x00, 233 SAW3_ID = 0x04, 234 SAW3_SPM_STS = 0x0C, 235 SAW3_AVS_STS = 0x10, 236 SAW3_PMIC_STS = 0x14, 237 SAW3_RST = 0x18, 238 SAW3_VCTL = 0x1C, 239 SAW3_AVS_CTL = 0x20, 240 SAW3_AVS_LIMIT = 0x24, 241 SAW3_AVS_DLY = 0x28, 242 SAW3_AVS_HYSTERESIS = 0x2C, 243 SAW3_SPM_STS2 = 0x38, 244 SAW3_SPM_PMIC_DATA_3 = 0x4C, 245 SAW3_VERSION = 0xFD0, 246 }; 247 248 /* Used for indexing into ctrl_reg. These are offsets from 0x40 */ 249 enum spmi_common_control_register_index { 250 SPMI_COMMON_IDX_VOLTAGE_RANGE = 0, 251 SPMI_COMMON_IDX_VOLTAGE_SET = 1, 252 SPMI_COMMON_IDX_MODE = 5, 253 SPMI_COMMON_IDX_ENABLE = 6, 254 }; 255 256 /* Common regulator control register layout */ 257 #define SPMI_COMMON_ENABLE_MASK 0x80 258 #define SPMI_COMMON_ENABLE 0x80 259 #define SPMI_COMMON_DISABLE 0x00 260 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN3_MASK 0x08 261 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN2_MASK 0x04 262 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN1_MASK 0x02 263 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN0_MASK 0x01 264 #define SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK 0x0f 265 266 /* Common regulator mode register layout */ 267 #define SPMI_COMMON_MODE_HPM_MASK 0x80 268 #define SPMI_COMMON_MODE_AUTO_MASK 0x40 269 #define SPMI_COMMON_MODE_BYPASS_MASK 0x20 270 #define SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK 0x10 271 #define SPMI_COMMON_MODE_FOLLOW_HW_EN3_MASK 0x08 272 #define SPMI_COMMON_MODE_FOLLOW_HW_EN2_MASK 0x04 273 #define SPMI_COMMON_MODE_FOLLOW_HW_EN1_MASK 0x02 274 #define SPMI_COMMON_MODE_FOLLOW_HW_EN0_MASK 0x01 275 #define SPMI_COMMON_MODE_FOLLOW_ALL_MASK 0x1f 276 277 #define SPMI_FTSMPS426_MODE_BYPASS_MASK 3 278 #define SPMI_FTSMPS426_MODE_RETENTION_MASK 4 279 #define SPMI_FTSMPS426_MODE_LPM_MASK 5 280 #define SPMI_FTSMPS426_MODE_AUTO_MASK 6 281 #define SPMI_FTSMPS426_MODE_HPM_MASK 7 282 283 #define SPMI_FTSMPS426_MODE_MASK 0x07 284 285 /* Third common regulator mode register values */ 286 #define SPMI_HFSMPS_MODE_BYPASS_MASK 2 287 #define SPMI_HFSMPS_MODE_RETENTION_MASK 3 288 #define SPMI_HFSMPS_MODE_LPM_MASK 4 289 #define SPMI_HFSMPS_MODE_AUTO_MASK 6 290 #define SPMI_HFSMPS_MODE_HPM_MASK 7 291 292 #define SPMI_HFSMPS_MODE_MASK 0x07 293 294 /* Common regulator pull down control register layout */ 295 #define SPMI_COMMON_PULL_DOWN_ENABLE_MASK 0x80 296 297 /* LDO regulator current limit control register layout */ 298 #define SPMI_LDO_CURRENT_LIMIT_ENABLE_MASK 0x80 299 300 /* LDO regulator soft start control register layout */ 301 #define SPMI_LDO_SOFT_START_ENABLE_MASK 0x80 302 303 /* VS regulator over current protection control register layout */ 304 #define SPMI_VS_OCP_OVERRIDE 0x01 305 #define SPMI_VS_OCP_NO_OVERRIDE 0x00 306 307 /* VS regulator soft start control register layout */ 308 #define SPMI_VS_SOFT_START_ENABLE_MASK 0x80 309 #define SPMI_VS_SOFT_START_SEL_MASK 0x03 310 311 /* Boost regulator current limit control register layout */ 312 #define SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK 0x80 313 #define SPMI_BOOST_CURRENT_LIMIT_MASK 0x07 314 315 #define SPMI_VS_OCP_DEFAULT_MAX_RETRIES 10 316 #define SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS 30 317 #define SPMI_VS_OCP_FALL_DELAY_US 90 318 #define SPMI_VS_OCP_FAULT_DELAY_US 20000 319 320 #define SPMI_FTSMPS_STEP_CTRL_STEP_MASK 0x18 321 #define SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT 3 322 #define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07 323 #define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0 324 325 /* Clock rate in kHz of the FTSMPS regulator reference clock. */ 326 #define SPMI_FTSMPS_CLOCK_RATE 19200 327 328 /* Minimum voltage stepper delay for each step. */ 329 #define SPMI_FTSMPS_STEP_DELAY 8 330 #define SPMI_DEFAULT_STEP_DELAY 20 331 332 /* 333 * The ratio SPMI_FTSMPS_STEP_MARGIN_NUM/SPMI_FTSMPS_STEP_MARGIN_DEN is used to 334 * adjust the step rate in order to account for oscillator variance. 335 */ 336 #define SPMI_FTSMPS_STEP_MARGIN_NUM 4 337 #define SPMI_FTSMPS_STEP_MARGIN_DEN 5 338 339 /* slew_rate has units of uV/us. */ 340 #define SPMI_HFSMPS_SLEW_RATE_38p4 38400 341 342 #define SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK 0x03 343 #define SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT 0 344 345 /* Clock rate in kHz of the FTSMPS426 regulator reference clock. */ 346 #define SPMI_FTSMPS426_CLOCK_RATE 4800 347 348 #define SPMI_HFS430_CLOCK_RATE 1600 349 350 /* Minimum voltage stepper delay for each step. */ 351 #define SPMI_FTSMPS426_STEP_DELAY 2 352 353 /* 354 * The ratio SPMI_FTSMPS426_STEP_MARGIN_NUM/SPMI_FTSMPS426_STEP_MARGIN_DEN is 355 * used to adjust the step rate in order to account for oscillator variance. 356 */ 357 #define SPMI_FTSMPS426_STEP_MARGIN_NUM 10 358 #define SPMI_FTSMPS426_STEP_MARGIN_DEN 11 359 360 361 /* VSET value to decide the range of ULT SMPS */ 362 #define ULT_SMPS_RANGE_SPLIT 0x60 363 364 /** 365 * struct spmi_voltage_range - regulator set point voltage mapping description 366 * @min_uV: Minimum programmable output voltage resulting from 367 * set point register value 0x00 368 * @max_uV: Maximum programmable output voltage 369 * @step_uV: Output voltage increase resulting from the set point 370 * register value increasing by 1 371 * @set_point_min_uV: Minimum allowed voltage 372 * @set_point_max_uV: Maximum allowed voltage. This may be tweaked in order 373 * to pick which range should be used in the case of 374 * overlapping set points. 375 * @n_voltages: Number of preferred voltage set points present in this 376 * range 377 * @range_sel: Voltage range register value corresponding to this range 378 * 379 * The following relationships must be true for the values used in this struct: 380 * (max_uV - min_uV) % step_uV == 0 381 * (set_point_min_uV - min_uV) % step_uV == 0* 382 * (set_point_max_uV - min_uV) % step_uV == 0* 383 * n_voltages = (set_point_max_uV - set_point_min_uV) / step_uV + 1 384 * 385 * *Note, set_point_min_uV == set_point_max_uV == 0 is allowed in order to 386 * specify that the voltage range has meaning, but is not preferred. 387 */ 388 struct spmi_voltage_range { 389 int min_uV; 390 int max_uV; 391 int step_uV; 392 int set_point_min_uV; 393 int set_point_max_uV; 394 unsigned n_voltages; 395 u8 range_sel; 396 }; 397 398 /* 399 * The ranges specified in the spmi_voltage_set_points struct must be listed 400 * so that range[i].set_point_max_uV < range[i+1].set_point_min_uV. 401 */ 402 struct spmi_voltage_set_points { 403 const struct spmi_voltage_range *range; 404 int count; 405 unsigned n_voltages; 406 }; 407 408 struct spmi_regulator { 409 struct regulator_desc desc; 410 struct device *dev; 411 struct delayed_work ocp_work; 412 struct regmap *regmap; 413 struct spmi_voltage_set_points *set_points; 414 enum spmi_regulator_logical_type logical_type; 415 int ocp_irq; 416 int ocp_count; 417 int ocp_max_retries; 418 int ocp_retry_delay_ms; 419 int hpm_min_load; 420 int slew_rate; 421 ktime_t vs_enable_time; 422 u16 base; 423 struct list_head node; 424 }; 425 426 struct spmi_regulator_mapping { 427 enum spmi_regulator_type type; 428 enum spmi_regulator_subtype subtype; 429 enum spmi_regulator_logical_type logical_type; 430 u32 revision_min; 431 u32 revision_max; 432 const struct regulator_ops *ops; 433 struct spmi_voltage_set_points *set_points; 434 int hpm_min_load; 435 }; 436 437 struct spmi_regulator_data { 438 const char *name; 439 u16 base; 440 const char *supply; 441 const char *ocp; 442 u16 force_type; 443 }; 444 445 #define SPMI_VREG(_type, _subtype, _dig_major_min, _dig_major_max, \ 446 _logical_type, _ops_val, _set_points_val, _hpm_min_load) \ 447 { \ 448 .type = SPMI_REGULATOR_TYPE_##_type, \ 449 .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \ 450 .revision_min = _dig_major_min, \ 451 .revision_max = _dig_major_max, \ 452 .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_##_logical_type, \ 453 .ops = &spmi_##_ops_val##_ops, \ 454 .set_points = &_set_points_val##_set_points, \ 455 .hpm_min_load = _hpm_min_load, \ 456 } 457 458 #define SPMI_VREG_VS(_subtype, _dig_major_min, _dig_major_max) \ 459 { \ 460 .type = SPMI_REGULATOR_TYPE_VS, \ 461 .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \ 462 .revision_min = _dig_major_min, \ 463 .revision_max = _dig_major_max, \ 464 .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_VS, \ 465 .ops = &spmi_vs_ops, \ 466 } 467 468 #define SPMI_VOLTAGE_RANGE(_range_sel, _min_uV, _set_point_min_uV, \ 469 _set_point_max_uV, _max_uV, _step_uV) \ 470 { \ 471 .min_uV = _min_uV, \ 472 .max_uV = _max_uV, \ 473 .set_point_min_uV = _set_point_min_uV, \ 474 .set_point_max_uV = _set_point_max_uV, \ 475 .step_uV = _step_uV, \ 476 .range_sel = _range_sel, \ 477 .n_voltages = (_set_point_max_uV != 0) ? \ 478 ((_set_point_max_uV - _set_point_min_uV) / _step_uV) + 1 : \ 479 0, \ 480 } 481 482 #define DEFINE_SPMI_SET_POINTS(name) \ 483 struct spmi_voltage_set_points name##_set_points = { \ 484 .range = name##_ranges, \ 485 .count = ARRAY_SIZE(name##_ranges), \ 486 } 487 488 /* 489 * These tables contain the physically available PMIC regulator voltage setpoint 490 * ranges. Where two ranges overlap in hardware, one of the ranges is trimmed 491 * to ensure that the setpoints available to software are monotonically 492 * increasing and unique. The set_voltage callback functions expect these 493 * properties to hold. 494 */ 495 static const struct spmi_voltage_range pldo_ranges[] = { 496 SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500), 497 SPMI_VOLTAGE_RANGE(3, 1500000, 1550000, 3075000, 3075000, 25000), 498 SPMI_VOLTAGE_RANGE(4, 1750000, 3100000, 4900000, 4900000, 50000), 499 }; 500 501 static const struct spmi_voltage_range nldo1_ranges[] = { 502 SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500), 503 }; 504 505 static const struct spmi_voltage_range nldo2_ranges[] = { 506 SPMI_VOLTAGE_RANGE(0, 375000, 0, 0, 1537500, 12500), 507 SPMI_VOLTAGE_RANGE(1, 375000, 375000, 768750, 768750, 6250), 508 SPMI_VOLTAGE_RANGE(2, 750000, 775000, 1537500, 1537500, 12500), 509 }; 510 511 static const struct spmi_voltage_range nldo3_ranges[] = { 512 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500), 513 SPMI_VOLTAGE_RANGE(1, 375000, 0, 0, 1537500, 12500), 514 SPMI_VOLTAGE_RANGE(2, 750000, 0, 0, 1537500, 12500), 515 }; 516 517 static const struct spmi_voltage_range ln_ldo_ranges[] = { 518 SPMI_VOLTAGE_RANGE(1, 690000, 690000, 1110000, 1110000, 60000), 519 SPMI_VOLTAGE_RANGE(0, 1380000, 1380000, 2220000, 2220000, 120000), 520 }; 521 522 static const struct spmi_voltage_range smps_ranges[] = { 523 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), 524 SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000), 525 }; 526 527 static const struct spmi_voltage_range ftsmps_ranges[] = { 528 SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000), 529 SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000), 530 }; 531 532 static const struct spmi_voltage_range ftsmps2p5_ranges[] = { 533 SPMI_VOLTAGE_RANGE(0, 80000, 350000, 1355000, 1355000, 5000), 534 SPMI_VOLTAGE_RANGE(1, 160000, 1360000, 2200000, 2200000, 10000), 535 }; 536 537 static const struct spmi_voltage_range ftsmps426_ranges[] = { 538 SPMI_VOLTAGE_RANGE(0, 0, 320000, 1352000, 1352000, 4000), 539 }; 540 541 static const struct spmi_voltage_range boost_ranges[] = { 542 SPMI_VOLTAGE_RANGE(0, 4000000, 4000000, 5550000, 5550000, 50000), 543 }; 544 545 static const struct spmi_voltage_range boost_byp_ranges[] = { 546 SPMI_VOLTAGE_RANGE(0, 2500000, 2500000, 5200000, 5650000, 50000), 547 }; 548 549 static const struct spmi_voltage_range ult_lo_smps_ranges[] = { 550 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), 551 SPMI_VOLTAGE_RANGE(1, 750000, 0, 0, 1525000, 25000), 552 }; 553 554 static const struct spmi_voltage_range ult_ho_smps_ranges[] = { 555 SPMI_VOLTAGE_RANGE(0, 1550000, 1550000, 2325000, 2325000, 25000), 556 }; 557 558 static const struct spmi_voltage_range ult_nldo_ranges[] = { 559 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500), 560 }; 561 562 static const struct spmi_voltage_range ult_pldo_ranges[] = { 563 SPMI_VOLTAGE_RANGE(0, 1750000, 1750000, 3337500, 3337500, 12500), 564 }; 565 566 static const struct spmi_voltage_range pldo660_ranges[] = { 567 SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 3544000, 3544000, 8000), 568 }; 569 570 static const struct spmi_voltage_range nldo660_ranges[] = { 571 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000), 572 }; 573 574 static const struct spmi_voltage_range ht_lvpldo_ranges[] = { 575 SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 2000000, 2000000, 8000), 576 }; 577 578 static const struct spmi_voltage_range ht_nldo_ranges[] = { 579 SPMI_VOLTAGE_RANGE(0, 312000, 312000, 1304000, 1304000, 8000), 580 }; 581 582 static const struct spmi_voltage_range hfs430_ranges[] = { 583 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000), 584 }; 585 586 static const struct spmi_voltage_range ht_p150_ranges[] = { 587 SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000), 588 }; 589 590 static const struct spmi_voltage_range ht_p600_ranges[] = { 591 SPMI_VOLTAGE_RANGE(0, 1704000, 1704000, 1896000, 1896000, 8000), 592 }; 593 594 static const struct spmi_voltage_range nldo_510_ranges[] = { 595 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000), 596 }; 597 598 static const struct spmi_voltage_range ftsmps510_ranges[] = { 599 SPMI_VOLTAGE_RANGE(0, 300000, 300000, 1372000, 1372000, 4000), 600 }; 601 602 static DEFINE_SPMI_SET_POINTS(pldo); 603 static DEFINE_SPMI_SET_POINTS(nldo1); 604 static DEFINE_SPMI_SET_POINTS(nldo2); 605 static DEFINE_SPMI_SET_POINTS(nldo3); 606 static DEFINE_SPMI_SET_POINTS(ln_ldo); 607 static DEFINE_SPMI_SET_POINTS(smps); 608 static DEFINE_SPMI_SET_POINTS(ftsmps); 609 static DEFINE_SPMI_SET_POINTS(ftsmps2p5); 610 static DEFINE_SPMI_SET_POINTS(ftsmps426); 611 static DEFINE_SPMI_SET_POINTS(boost); 612 static DEFINE_SPMI_SET_POINTS(boost_byp); 613 static DEFINE_SPMI_SET_POINTS(ult_lo_smps); 614 static DEFINE_SPMI_SET_POINTS(ult_ho_smps); 615 static DEFINE_SPMI_SET_POINTS(ult_nldo); 616 static DEFINE_SPMI_SET_POINTS(ult_pldo); 617 static DEFINE_SPMI_SET_POINTS(pldo660); 618 static DEFINE_SPMI_SET_POINTS(nldo660); 619 static DEFINE_SPMI_SET_POINTS(ht_lvpldo); 620 static DEFINE_SPMI_SET_POINTS(ht_nldo); 621 static DEFINE_SPMI_SET_POINTS(hfs430); 622 static DEFINE_SPMI_SET_POINTS(ht_p150); 623 static DEFINE_SPMI_SET_POINTS(ht_p600); 624 static DEFINE_SPMI_SET_POINTS(nldo_510); 625 static DEFINE_SPMI_SET_POINTS(ftsmps510); 626 627 static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf, 628 int len) 629 { 630 return regmap_bulk_read(vreg->regmap, vreg->base + addr, buf, len); 631 } 632 633 static inline int spmi_vreg_write(struct spmi_regulator *vreg, u16 addr, 634 u8 *buf, int len) 635 { 636 return regmap_bulk_write(vreg->regmap, vreg->base + addr, buf, len); 637 } 638 639 static int spmi_vreg_update_bits(struct spmi_regulator *vreg, u16 addr, u8 val, 640 u8 mask) 641 { 642 return regmap_update_bits(vreg->regmap, vreg->base + addr, mask, val); 643 } 644 645 static int spmi_regulator_vs_enable(struct regulator_dev *rdev) 646 { 647 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 648 649 if (vreg->ocp_irq) { 650 vreg->ocp_count = 0; 651 vreg->vs_enable_time = ktime_get(); 652 } 653 654 return regulator_enable_regmap(rdev); 655 } 656 657 static int spmi_regulator_vs_ocp(struct regulator_dev *rdev, int lim_uA, 658 int severity, bool enable) 659 { 660 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 661 u8 reg = SPMI_VS_OCP_OVERRIDE; 662 663 if (lim_uA || !enable || severity != REGULATOR_SEVERITY_PROT) 664 return -EINVAL; 665 666 return spmi_vreg_write(vreg, SPMI_VS_REG_OCP, ®, 1); 667 } 668 669 static int spmi_regulator_select_voltage(struct spmi_regulator *vreg, 670 int min_uV, int max_uV) 671 { 672 const struct spmi_voltage_range *range; 673 int uV = min_uV; 674 int lim_min_uV, lim_max_uV, i, range_id, range_max_uV; 675 int selector, voltage_sel; 676 677 /* Check if request voltage is outside of physically settable range. */ 678 lim_min_uV = vreg->set_points->range[0].set_point_min_uV; 679 lim_max_uV = 680 vreg->set_points->range[vreg->set_points->count - 1].set_point_max_uV; 681 682 if (uV < lim_min_uV && max_uV >= lim_min_uV) 683 uV = lim_min_uV; 684 685 if (uV < lim_min_uV || uV > lim_max_uV) { 686 dev_err(vreg->dev, 687 "request v=[%d, %d] is outside possible v=[%d, %d]\n", 688 min_uV, max_uV, lim_min_uV, lim_max_uV); 689 return -EINVAL; 690 } 691 692 /* Find the range which uV is inside of. */ 693 for (i = vreg->set_points->count - 1; i > 0; i--) { 694 range_max_uV = vreg->set_points->range[i - 1].set_point_max_uV; 695 if (uV > range_max_uV && range_max_uV > 0) 696 break; 697 } 698 699 range_id = i; 700 range = &vreg->set_points->range[range_id]; 701 702 /* 703 * Force uV to be an allowed set point by applying a ceiling function to 704 * the uV value. 705 */ 706 voltage_sel = DIV_ROUND_UP(uV - range->min_uV, range->step_uV); 707 uV = voltage_sel * range->step_uV + range->min_uV; 708 709 if (uV > max_uV) { 710 dev_err(vreg->dev, 711 "request v=[%d, %d] cannot be met by any set point; " 712 "next set point: %d\n", 713 min_uV, max_uV, uV); 714 return -EINVAL; 715 } 716 717 selector = 0; 718 for (i = 0; i < range_id; i++) 719 selector += vreg->set_points->range[i].n_voltages; 720 selector += (uV - range->set_point_min_uV) / range->step_uV; 721 722 return selector; 723 } 724 725 static int spmi_sw_selector_to_hw(struct spmi_regulator *vreg, 726 unsigned selector, u8 *range_sel, 727 u8 *voltage_sel) 728 { 729 const struct spmi_voltage_range *range, *end; 730 unsigned offset; 731 732 range = vreg->set_points->range; 733 end = range + vreg->set_points->count; 734 735 for (; range < end; range++) { 736 if (selector < range->n_voltages) { 737 /* 738 * hardware selectors between set point min and real 739 * min are invalid so we ignore them 740 */ 741 offset = range->set_point_min_uV - range->min_uV; 742 offset /= range->step_uV; 743 *voltage_sel = selector + offset; 744 *range_sel = range->range_sel; 745 return 0; 746 } 747 748 selector -= range->n_voltages; 749 } 750 751 return -EINVAL; 752 } 753 754 static int spmi_hw_selector_to_sw(struct spmi_regulator *vreg, u8 hw_sel, 755 const struct spmi_voltage_range *range) 756 { 757 unsigned sw_sel = 0; 758 unsigned offset, max_hw_sel; 759 const struct spmi_voltage_range *r = vreg->set_points->range; 760 const struct spmi_voltage_range *end = r + vreg->set_points->count; 761 762 for (; r < end; r++) { 763 if (r == range && range->n_voltages) { 764 /* 765 * hardware selectors between set point min and real 766 * min and between set point max and real max are 767 * invalid so we return an error if they're 768 * programmed into the hardware 769 */ 770 offset = range->set_point_min_uV - range->min_uV; 771 offset /= range->step_uV; 772 if (hw_sel < offset) 773 return -EINVAL; 774 775 max_hw_sel = range->set_point_max_uV - range->min_uV; 776 max_hw_sel /= range->step_uV; 777 if (hw_sel > max_hw_sel) 778 return -EINVAL; 779 780 return sw_sel + hw_sel - offset; 781 } 782 sw_sel += r->n_voltages; 783 } 784 785 return -EINVAL; 786 } 787 788 static const struct spmi_voltage_range * 789 spmi_regulator_find_range(struct spmi_regulator *vreg) 790 { 791 u8 range_sel; 792 const struct spmi_voltage_range *range, *end; 793 794 range = vreg->set_points->range; 795 end = range + vreg->set_points->count; 796 797 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, &range_sel, 1); 798 799 for (; range < end; range++) 800 if (range->range_sel == range_sel) 801 return range; 802 803 return NULL; 804 } 805 806 static int spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg, 807 int min_uV, int max_uV) 808 { 809 const struct spmi_voltage_range *range; 810 int uV = min_uV; 811 int i, selector; 812 813 range = spmi_regulator_find_range(vreg); 814 if (!range) 815 goto different_range; 816 817 if (uV < range->min_uV && max_uV >= range->min_uV) 818 uV = range->min_uV; 819 820 if (uV < range->min_uV || uV > range->max_uV) { 821 /* Current range doesn't support the requested voltage. */ 822 goto different_range; 823 } 824 825 /* 826 * Force uV to be an allowed set point by applying a ceiling function to 827 * the uV value. 828 */ 829 uV = DIV_ROUND_UP(uV - range->min_uV, range->step_uV); 830 uV = uV * range->step_uV + range->min_uV; 831 832 if (uV > max_uV) { 833 /* 834 * No set point in the current voltage range is within the 835 * requested min_uV to max_uV range. 836 */ 837 goto different_range; 838 } 839 840 selector = 0; 841 for (i = 0; i < vreg->set_points->count; i++) { 842 if (uV >= vreg->set_points->range[i].set_point_min_uV 843 && uV <= vreg->set_points->range[i].set_point_max_uV) { 844 selector += 845 (uV - vreg->set_points->range[i].set_point_min_uV) 846 / vreg->set_points->range[i].step_uV; 847 break; 848 } 849 850 selector += vreg->set_points->range[i].n_voltages; 851 } 852 853 if (selector >= vreg->set_points->n_voltages) 854 goto different_range; 855 856 return selector; 857 858 different_range: 859 return spmi_regulator_select_voltage(vreg, min_uV, max_uV); 860 } 861 862 static int spmi_regulator_common_map_voltage(struct regulator_dev *rdev, 863 int min_uV, int max_uV) 864 { 865 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 866 867 /* 868 * Favor staying in the current voltage range if possible. This avoids 869 * voltage spikes that occur when changing the voltage range. 870 */ 871 return spmi_regulator_select_voltage_same_range(vreg, min_uV, max_uV); 872 } 873 874 static int 875 spmi_regulator_common_set_voltage(struct regulator_dev *rdev, unsigned selector) 876 { 877 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 878 int ret; 879 u8 buf[2]; 880 u8 range_sel, voltage_sel; 881 882 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); 883 if (ret) 884 return ret; 885 886 buf[0] = range_sel; 887 buf[1] = voltage_sel; 888 return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, buf, 2); 889 } 890 891 static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev, 892 unsigned selector); 893 894 static int spmi_regulator_ftsmps426_set_voltage(struct regulator_dev *rdev, 895 unsigned selector) 896 { 897 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 898 u8 buf[2]; 899 int mV; 900 901 mV = spmi_regulator_common_list_voltage(rdev, selector) / 1000; 902 903 buf[0] = mV & 0xff; 904 buf[1] = mV >> 8; 905 return spmi_vreg_write(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2); 906 } 907 908 static int spmi_regulator_set_voltage_time_sel(struct regulator_dev *rdev, 909 unsigned int old_selector, unsigned int new_selector) 910 { 911 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 912 int diff_uV; 913 914 diff_uV = abs(spmi_regulator_common_list_voltage(rdev, new_selector) - 915 spmi_regulator_common_list_voltage(rdev, old_selector)); 916 917 return DIV_ROUND_UP(diff_uV, vreg->slew_rate); 918 } 919 920 static int spmi_regulator_common_get_voltage(struct regulator_dev *rdev) 921 { 922 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 923 const struct spmi_voltage_range *range; 924 u8 voltage_sel; 925 926 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1); 927 928 range = spmi_regulator_find_range(vreg); 929 if (!range) 930 return -EINVAL; 931 932 return spmi_hw_selector_to_sw(vreg, voltage_sel, range); 933 } 934 935 static int spmi_regulator_ftsmps426_get_voltage(struct regulator_dev *rdev) 936 { 937 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 938 const struct spmi_voltage_range *range; 939 u8 buf[2]; 940 int uV; 941 942 spmi_vreg_read(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2); 943 944 uV = (((unsigned int)buf[1] << 8) | (unsigned int)buf[0]) * 1000; 945 range = vreg->set_points->range; 946 947 return (uV - range->set_point_min_uV) / range->step_uV; 948 } 949 950 static int spmi_regulator_single_map_voltage(struct regulator_dev *rdev, 951 int min_uV, int max_uV) 952 { 953 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 954 955 return spmi_regulator_select_voltage(vreg, min_uV, max_uV); 956 } 957 958 static int spmi_regulator_single_range_set_voltage(struct regulator_dev *rdev, 959 unsigned selector) 960 { 961 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 962 u8 sel = selector; 963 964 /* 965 * Certain types of regulators do not have a range select register so 966 * only voltage set register needs to be written. 967 */ 968 return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &sel, 1); 969 } 970 971 static int spmi_regulator_single_range_get_voltage(struct regulator_dev *rdev) 972 { 973 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 974 u8 selector; 975 int ret; 976 977 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &selector, 1); 978 if (ret) 979 return ret; 980 981 return selector; 982 } 983 984 static int spmi_regulator_ult_lo_smps_set_voltage(struct regulator_dev *rdev, 985 unsigned selector) 986 { 987 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 988 int ret; 989 u8 range_sel, voltage_sel; 990 991 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); 992 if (ret) 993 return ret; 994 995 /* 996 * Calculate VSET based on range 997 * In case of range 0: voltage_sel is a 7 bit value, can be written 998 * witout any modification. 999 * In case of range 1: voltage_sel is a 5 bit value, bits[7-5] set to 1000 * [011]. 1001 */ 1002 if (range_sel == 1) 1003 voltage_sel |= ULT_SMPS_RANGE_SPLIT; 1004 1005 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_VOLTAGE_SET, 1006 voltage_sel, 0xff); 1007 } 1008 1009 static int spmi_regulator_ult_lo_smps_get_voltage(struct regulator_dev *rdev) 1010 { 1011 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1012 const struct spmi_voltage_range *range; 1013 u8 voltage_sel; 1014 1015 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1); 1016 1017 range = spmi_regulator_find_range(vreg); 1018 if (!range) 1019 return -EINVAL; 1020 1021 if (range->range_sel == 1) 1022 voltage_sel &= ~ULT_SMPS_RANGE_SPLIT; 1023 1024 return spmi_hw_selector_to_sw(vreg, voltage_sel, range); 1025 } 1026 1027 static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev, 1028 unsigned selector) 1029 { 1030 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1031 int uV = 0; 1032 int i; 1033 1034 if (selector >= vreg->set_points->n_voltages) 1035 return 0; 1036 1037 for (i = 0; i < vreg->set_points->count; i++) { 1038 if (selector < vreg->set_points->range[i].n_voltages) { 1039 uV = selector * vreg->set_points->range[i].step_uV 1040 + vreg->set_points->range[i].set_point_min_uV; 1041 break; 1042 } 1043 1044 selector -= vreg->set_points->range[i].n_voltages; 1045 } 1046 1047 return uV; 1048 } 1049 1050 static int 1051 spmi_regulator_common_set_bypass(struct regulator_dev *rdev, bool enable) 1052 { 1053 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1054 u8 mask = SPMI_COMMON_MODE_BYPASS_MASK; 1055 u8 val = 0; 1056 1057 if (enable) 1058 val = mask; 1059 1060 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); 1061 } 1062 1063 static int 1064 spmi_regulator_common_get_bypass(struct regulator_dev *rdev, bool *enable) 1065 { 1066 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1067 u8 val; 1068 int ret; 1069 1070 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &val, 1); 1071 *enable = val & SPMI_COMMON_MODE_BYPASS_MASK; 1072 1073 return ret; 1074 } 1075 1076 static unsigned int spmi_regulator_common_get_mode(struct regulator_dev *rdev) 1077 { 1078 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1079 u8 reg; 1080 1081 spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); 1082 1083 reg &= SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK; 1084 1085 switch (reg) { 1086 case SPMI_COMMON_MODE_HPM_MASK: 1087 return REGULATOR_MODE_NORMAL; 1088 case SPMI_COMMON_MODE_AUTO_MASK: 1089 return REGULATOR_MODE_FAST; 1090 default: 1091 return REGULATOR_MODE_IDLE; 1092 } 1093 } 1094 1095 static unsigned int spmi_regulator_ftsmps426_get_mode(struct regulator_dev *rdev) 1096 { 1097 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1098 u8 reg; 1099 1100 spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); 1101 1102 switch (reg) { 1103 case SPMI_FTSMPS426_MODE_HPM_MASK: 1104 return REGULATOR_MODE_NORMAL; 1105 case SPMI_FTSMPS426_MODE_AUTO_MASK: 1106 return REGULATOR_MODE_FAST; 1107 default: 1108 return REGULATOR_MODE_IDLE; 1109 } 1110 } 1111 1112 static unsigned int spmi_regulator_hfsmps_get_mode(struct regulator_dev *rdev) 1113 { 1114 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1115 u8 reg; 1116 1117 spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); 1118 1119 switch (reg) { 1120 case SPMI_HFSMPS_MODE_HPM_MASK: 1121 return REGULATOR_MODE_NORMAL; 1122 case SPMI_HFSMPS_MODE_AUTO_MASK: 1123 return REGULATOR_MODE_FAST; 1124 default: 1125 return REGULATOR_MODE_IDLE; 1126 } 1127 } 1128 1129 static int 1130 spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode) 1131 { 1132 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1133 u8 mask = SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK; 1134 u8 val; 1135 1136 switch (mode) { 1137 case REGULATOR_MODE_NORMAL: 1138 val = SPMI_COMMON_MODE_HPM_MASK; 1139 break; 1140 case REGULATOR_MODE_FAST: 1141 val = SPMI_COMMON_MODE_AUTO_MASK; 1142 break; 1143 default: 1144 val = 0; 1145 break; 1146 } 1147 1148 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); 1149 } 1150 1151 static int 1152 spmi_regulator_ftsmps426_set_mode(struct regulator_dev *rdev, unsigned int mode) 1153 { 1154 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1155 u8 mask = SPMI_FTSMPS426_MODE_MASK; 1156 u8 val; 1157 1158 switch (mode) { 1159 case REGULATOR_MODE_NORMAL: 1160 val = SPMI_FTSMPS426_MODE_HPM_MASK; 1161 break; 1162 case REGULATOR_MODE_FAST: 1163 val = SPMI_FTSMPS426_MODE_AUTO_MASK; 1164 break; 1165 case REGULATOR_MODE_IDLE: 1166 val = SPMI_FTSMPS426_MODE_LPM_MASK; 1167 break; 1168 default: 1169 return -EINVAL; 1170 } 1171 1172 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); 1173 } 1174 1175 static int 1176 spmi_regulator_hfsmps_set_mode(struct regulator_dev *rdev, unsigned int mode) 1177 { 1178 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1179 u8 mask = SPMI_HFSMPS_MODE_MASK; 1180 u8 val; 1181 1182 switch (mode) { 1183 case REGULATOR_MODE_NORMAL: 1184 val = SPMI_HFSMPS_MODE_HPM_MASK; 1185 break; 1186 case REGULATOR_MODE_FAST: 1187 val = SPMI_HFSMPS_MODE_AUTO_MASK; 1188 break; 1189 case REGULATOR_MODE_IDLE: 1190 val = vreg->logical_type == 1191 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3 ? 1192 SPMI_HFSMPS_MODE_RETENTION_MASK : 1193 SPMI_HFSMPS_MODE_LPM_MASK; 1194 break; 1195 default: 1196 return -EINVAL; 1197 } 1198 1199 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); 1200 } 1201 1202 static int 1203 spmi_regulator_common_set_load(struct regulator_dev *rdev, int load_uA) 1204 { 1205 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1206 unsigned int mode; 1207 1208 if (load_uA >= vreg->hpm_min_load) 1209 mode = REGULATOR_MODE_NORMAL; 1210 else 1211 mode = REGULATOR_MODE_IDLE; 1212 1213 return spmi_regulator_common_set_mode(rdev, mode); 1214 } 1215 1216 static int spmi_regulator_common_set_pull_down(struct regulator_dev *rdev) 1217 { 1218 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1219 unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK; 1220 1221 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_PULL_DOWN, 1222 mask, mask); 1223 } 1224 1225 static int spmi_regulator_hfsmps_set_pull_down(struct regulator_dev *rdev) 1226 { 1227 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1228 unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK; 1229 1230 return spmi_vreg_update_bits(vreg, SPMI_HFSMPS_REG_PULL_DOWN, 1231 mask, mask); 1232 } 1233 1234 static int spmi_regulator_common_set_soft_start(struct regulator_dev *rdev) 1235 { 1236 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1237 unsigned int mask = SPMI_LDO_SOFT_START_ENABLE_MASK; 1238 1239 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_SOFT_START, 1240 mask, mask); 1241 } 1242 1243 static int spmi_regulator_set_ilim(struct regulator_dev *rdev, int ilim_uA) 1244 { 1245 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1246 enum spmi_regulator_logical_type type = vreg->logical_type; 1247 unsigned int current_reg; 1248 u8 reg; 1249 u8 mask = SPMI_BOOST_CURRENT_LIMIT_MASK | 1250 SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK; 1251 int max = (SPMI_BOOST_CURRENT_LIMIT_MASK + 1) * 500; 1252 1253 if (type == SPMI_REGULATOR_LOGICAL_TYPE_BOOST) 1254 current_reg = SPMI_BOOST_REG_CURRENT_LIMIT; 1255 else 1256 current_reg = SPMI_BOOST_BYP_REG_CURRENT_LIMIT; 1257 1258 if (ilim_uA > max || ilim_uA <= 0) 1259 return -EINVAL; 1260 1261 reg = (ilim_uA - 1) / 500; 1262 reg |= SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK; 1263 1264 return spmi_vreg_update_bits(vreg, current_reg, reg, mask); 1265 } 1266 1267 static int spmi_regulator_vs_clear_ocp(struct spmi_regulator *vreg) 1268 { 1269 int ret; 1270 1271 ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE, 1272 SPMI_COMMON_DISABLE, SPMI_COMMON_ENABLE_MASK); 1273 1274 vreg->vs_enable_time = ktime_get(); 1275 1276 ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE, 1277 SPMI_COMMON_ENABLE, SPMI_COMMON_ENABLE_MASK); 1278 1279 return ret; 1280 } 1281 1282 static void spmi_regulator_vs_ocp_work(struct work_struct *work) 1283 { 1284 struct delayed_work *dwork = to_delayed_work(work); 1285 struct spmi_regulator *vreg 1286 = container_of(dwork, struct spmi_regulator, ocp_work); 1287 1288 spmi_regulator_vs_clear_ocp(vreg); 1289 } 1290 1291 static irqreturn_t spmi_regulator_vs_ocp_isr(int irq, void *data) 1292 { 1293 struct spmi_regulator *vreg = data; 1294 ktime_t ocp_irq_time; 1295 s64 ocp_trigger_delay_us; 1296 1297 ocp_irq_time = ktime_get(); 1298 ocp_trigger_delay_us = ktime_us_delta(ocp_irq_time, 1299 vreg->vs_enable_time); 1300 1301 /* 1302 * Reset the OCP count if there is a large delay between switch enable 1303 * and when OCP triggers. This is indicative of a hotplug event as 1304 * opposed to a fault. 1305 */ 1306 if (ocp_trigger_delay_us > SPMI_VS_OCP_FAULT_DELAY_US) 1307 vreg->ocp_count = 0; 1308 1309 /* Wait for switch output to settle back to 0 V after OCP triggered. */ 1310 udelay(SPMI_VS_OCP_FALL_DELAY_US); 1311 1312 vreg->ocp_count++; 1313 1314 if (vreg->ocp_count == 1) { 1315 /* Immediately clear the over current condition. */ 1316 spmi_regulator_vs_clear_ocp(vreg); 1317 } else if (vreg->ocp_count <= vreg->ocp_max_retries) { 1318 /* Schedule the over current clear task to run later. */ 1319 schedule_delayed_work(&vreg->ocp_work, 1320 msecs_to_jiffies(vreg->ocp_retry_delay_ms) + 1); 1321 } else { 1322 dev_err(vreg->dev, 1323 "OCP triggered %d times; no further retries\n", 1324 vreg->ocp_count); 1325 } 1326 1327 return IRQ_HANDLED; 1328 } 1329 1330 #define SAW3_VCTL_DATA_MASK 0xFF 1331 #define SAW3_VCTL_CLEAR_MASK 0x700FF 1332 #define SAW3_AVS_CTL_EN_MASK 0x1 1333 #define SAW3_AVS_CTL_TGGL_MASK 0x8000000 1334 #define SAW3_AVS_CTL_CLEAR_MASK 0x7efc00 1335 1336 static struct regmap *saw_regmap; 1337 1338 static void spmi_saw_set_vdd(void *data) 1339 { 1340 u32 vctl, data3, avs_ctl, pmic_sts; 1341 bool avs_enabled = false; 1342 unsigned long timeout; 1343 u8 voltage_sel = *(u8 *)data; 1344 1345 regmap_read(saw_regmap, SAW3_AVS_CTL, &avs_ctl); 1346 regmap_read(saw_regmap, SAW3_VCTL, &vctl); 1347 regmap_read(saw_regmap, SAW3_SPM_PMIC_DATA_3, &data3); 1348 1349 /* select the band */ 1350 vctl &= ~SAW3_VCTL_CLEAR_MASK; 1351 vctl |= (u32)voltage_sel; 1352 1353 data3 &= ~SAW3_VCTL_CLEAR_MASK; 1354 data3 |= (u32)voltage_sel; 1355 1356 /* If AVS is enabled, switch it off during the voltage change */ 1357 avs_enabled = SAW3_AVS_CTL_EN_MASK & avs_ctl; 1358 if (avs_enabled) { 1359 avs_ctl &= ~SAW3_AVS_CTL_TGGL_MASK; 1360 regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl); 1361 } 1362 1363 regmap_write(saw_regmap, SAW3_RST, 1); 1364 regmap_write(saw_regmap, SAW3_VCTL, vctl); 1365 regmap_write(saw_regmap, SAW3_SPM_PMIC_DATA_3, data3); 1366 1367 timeout = jiffies + usecs_to_jiffies(100); 1368 do { 1369 regmap_read(saw_regmap, SAW3_PMIC_STS, &pmic_sts); 1370 pmic_sts &= SAW3_VCTL_DATA_MASK; 1371 if (pmic_sts == (u32)voltage_sel) 1372 break; 1373 1374 cpu_relax(); 1375 1376 } while (time_before(jiffies, timeout)); 1377 1378 /* After successful voltage change, switch the AVS back on */ 1379 if (avs_enabled) { 1380 pmic_sts &= 0x3f; 1381 avs_ctl &= ~SAW3_AVS_CTL_CLEAR_MASK; 1382 avs_ctl |= ((pmic_sts - 4) << 10); 1383 avs_ctl |= (pmic_sts << 17); 1384 avs_ctl |= SAW3_AVS_CTL_TGGL_MASK; 1385 regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl); 1386 } 1387 } 1388 1389 static int 1390 spmi_regulator_saw_set_voltage(struct regulator_dev *rdev, unsigned selector) 1391 { 1392 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1393 int ret; 1394 u8 range_sel, voltage_sel; 1395 1396 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); 1397 if (ret) 1398 return ret; 1399 1400 if (0 != range_sel) { 1401 dev_dbg(&rdev->dev, "range_sel = %02X voltage_sel = %02X", \ 1402 range_sel, voltage_sel); 1403 return -EINVAL; 1404 } 1405 1406 /* Always do the SAW register writes on the first CPU */ 1407 return smp_call_function_single(0, spmi_saw_set_vdd, \ 1408 &voltage_sel, true); 1409 } 1410 1411 static struct regulator_ops spmi_saw_ops = {}; 1412 1413 static const struct regulator_ops spmi_smps_ops = { 1414 .enable = regulator_enable_regmap, 1415 .disable = regulator_disable_regmap, 1416 .is_enabled = regulator_is_enabled_regmap, 1417 .set_voltage_sel = spmi_regulator_common_set_voltage, 1418 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1419 .get_voltage_sel = spmi_regulator_common_get_voltage, 1420 .map_voltage = spmi_regulator_common_map_voltage, 1421 .list_voltage = spmi_regulator_common_list_voltage, 1422 .set_mode = spmi_regulator_common_set_mode, 1423 .get_mode = spmi_regulator_common_get_mode, 1424 .set_load = spmi_regulator_common_set_load, 1425 .set_pull_down = spmi_regulator_common_set_pull_down, 1426 }; 1427 1428 static const struct regulator_ops spmi_ldo_ops = { 1429 .enable = regulator_enable_regmap, 1430 .disable = regulator_disable_regmap, 1431 .is_enabled = regulator_is_enabled_regmap, 1432 .set_voltage_sel = spmi_regulator_common_set_voltage, 1433 .get_voltage_sel = spmi_regulator_common_get_voltage, 1434 .map_voltage = spmi_regulator_common_map_voltage, 1435 .list_voltage = spmi_regulator_common_list_voltage, 1436 .set_mode = spmi_regulator_common_set_mode, 1437 .get_mode = spmi_regulator_common_get_mode, 1438 .set_load = spmi_regulator_common_set_load, 1439 .set_bypass = spmi_regulator_common_set_bypass, 1440 .get_bypass = spmi_regulator_common_get_bypass, 1441 .set_pull_down = spmi_regulator_common_set_pull_down, 1442 .set_soft_start = spmi_regulator_common_set_soft_start, 1443 }; 1444 1445 static const struct regulator_ops spmi_ln_ldo_ops = { 1446 .enable = regulator_enable_regmap, 1447 .disable = regulator_disable_regmap, 1448 .is_enabled = regulator_is_enabled_regmap, 1449 .set_voltage_sel = spmi_regulator_common_set_voltage, 1450 .get_voltage_sel = spmi_regulator_common_get_voltage, 1451 .map_voltage = spmi_regulator_common_map_voltage, 1452 .list_voltage = spmi_regulator_common_list_voltage, 1453 .set_bypass = spmi_regulator_common_set_bypass, 1454 .get_bypass = spmi_regulator_common_get_bypass, 1455 }; 1456 1457 static const struct regulator_ops spmi_vs_ops = { 1458 .enable = spmi_regulator_vs_enable, 1459 .disable = regulator_disable_regmap, 1460 .is_enabled = regulator_is_enabled_regmap, 1461 .set_pull_down = spmi_regulator_common_set_pull_down, 1462 .set_soft_start = spmi_regulator_common_set_soft_start, 1463 .set_over_current_protection = spmi_regulator_vs_ocp, 1464 .set_mode = spmi_regulator_common_set_mode, 1465 .get_mode = spmi_regulator_common_get_mode, 1466 }; 1467 1468 static const struct regulator_ops spmi_boost_ops = { 1469 .enable = regulator_enable_regmap, 1470 .disable = regulator_disable_regmap, 1471 .is_enabled = regulator_is_enabled_regmap, 1472 .set_voltage_sel = spmi_regulator_single_range_set_voltage, 1473 .get_voltage_sel = spmi_regulator_single_range_get_voltage, 1474 .map_voltage = spmi_regulator_single_map_voltage, 1475 .list_voltage = spmi_regulator_common_list_voltage, 1476 .set_input_current_limit = spmi_regulator_set_ilim, 1477 }; 1478 1479 static const struct regulator_ops spmi_ftsmps_ops = { 1480 .enable = regulator_enable_regmap, 1481 .disable = regulator_disable_regmap, 1482 .is_enabled = regulator_is_enabled_regmap, 1483 .set_voltage_sel = spmi_regulator_common_set_voltage, 1484 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1485 .get_voltage_sel = spmi_regulator_common_get_voltage, 1486 .map_voltage = spmi_regulator_common_map_voltage, 1487 .list_voltage = spmi_regulator_common_list_voltage, 1488 .set_mode = spmi_regulator_common_set_mode, 1489 .get_mode = spmi_regulator_common_get_mode, 1490 .set_load = spmi_regulator_common_set_load, 1491 .set_pull_down = spmi_regulator_common_set_pull_down, 1492 }; 1493 1494 static const struct regulator_ops spmi_ult_lo_smps_ops = { 1495 .enable = regulator_enable_regmap, 1496 .disable = regulator_disable_regmap, 1497 .is_enabled = regulator_is_enabled_regmap, 1498 .set_voltage_sel = spmi_regulator_ult_lo_smps_set_voltage, 1499 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1500 .get_voltage_sel = spmi_regulator_ult_lo_smps_get_voltage, 1501 .list_voltage = spmi_regulator_common_list_voltage, 1502 .set_mode = spmi_regulator_common_set_mode, 1503 .get_mode = spmi_regulator_common_get_mode, 1504 .set_load = spmi_regulator_common_set_load, 1505 .set_pull_down = spmi_regulator_common_set_pull_down, 1506 }; 1507 1508 static const struct regulator_ops spmi_ult_ho_smps_ops = { 1509 .enable = regulator_enable_regmap, 1510 .disable = regulator_disable_regmap, 1511 .is_enabled = regulator_is_enabled_regmap, 1512 .set_voltage_sel = spmi_regulator_single_range_set_voltage, 1513 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1514 .get_voltage_sel = spmi_regulator_single_range_get_voltage, 1515 .map_voltage = spmi_regulator_single_map_voltage, 1516 .list_voltage = spmi_regulator_common_list_voltage, 1517 .set_mode = spmi_regulator_common_set_mode, 1518 .get_mode = spmi_regulator_common_get_mode, 1519 .set_load = spmi_regulator_common_set_load, 1520 .set_pull_down = spmi_regulator_common_set_pull_down, 1521 }; 1522 1523 static const struct regulator_ops spmi_ult_ldo_ops = { 1524 .enable = regulator_enable_regmap, 1525 .disable = regulator_disable_regmap, 1526 .is_enabled = regulator_is_enabled_regmap, 1527 .set_voltage_sel = spmi_regulator_single_range_set_voltage, 1528 .get_voltage_sel = spmi_regulator_single_range_get_voltage, 1529 .map_voltage = spmi_regulator_single_map_voltage, 1530 .list_voltage = spmi_regulator_common_list_voltage, 1531 .set_mode = spmi_regulator_common_set_mode, 1532 .get_mode = spmi_regulator_common_get_mode, 1533 .set_load = spmi_regulator_common_set_load, 1534 .set_bypass = spmi_regulator_common_set_bypass, 1535 .get_bypass = spmi_regulator_common_get_bypass, 1536 .set_pull_down = spmi_regulator_common_set_pull_down, 1537 .set_soft_start = spmi_regulator_common_set_soft_start, 1538 }; 1539 1540 static const struct regulator_ops spmi_ftsmps426_ops = { 1541 .enable = regulator_enable_regmap, 1542 .disable = regulator_disable_regmap, 1543 .is_enabled = regulator_is_enabled_regmap, 1544 .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage, 1545 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1546 .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage, 1547 .map_voltage = spmi_regulator_single_map_voltage, 1548 .list_voltage = spmi_regulator_common_list_voltage, 1549 .set_mode = spmi_regulator_ftsmps426_set_mode, 1550 .get_mode = spmi_regulator_ftsmps426_get_mode, 1551 .set_load = spmi_regulator_common_set_load, 1552 .set_pull_down = spmi_regulator_common_set_pull_down, 1553 }; 1554 1555 static const struct regulator_ops spmi_hfs430_ops = { 1556 .enable = regulator_enable_regmap, 1557 .disable = regulator_disable_regmap, 1558 .is_enabled = regulator_is_enabled_regmap, 1559 .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage, 1560 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1561 .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage, 1562 .map_voltage = spmi_regulator_single_map_voltage, 1563 .list_voltage = spmi_regulator_common_list_voltage, 1564 .set_mode = spmi_regulator_ftsmps426_set_mode, 1565 .get_mode = spmi_regulator_ftsmps426_get_mode, 1566 }; 1567 1568 static const struct regulator_ops spmi_hfsmps_ops = { 1569 .enable = regulator_enable_regmap, 1570 .disable = regulator_disable_regmap, 1571 .is_enabled = regulator_is_enabled_regmap, 1572 .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage, 1573 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1574 .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage, 1575 .map_voltage = spmi_regulator_single_map_voltage, 1576 .list_voltage = spmi_regulator_common_list_voltage, 1577 .set_mode = spmi_regulator_hfsmps_set_mode, 1578 .get_mode = spmi_regulator_hfsmps_get_mode, 1579 .set_load = spmi_regulator_common_set_load, 1580 .set_pull_down = spmi_regulator_hfsmps_set_pull_down, 1581 }; 1582 1583 /* Maximum possible digital major revision value */ 1584 #define INF 0xFF 1585 1586 static const struct spmi_regulator_mapping supported_regulators[] = { 1587 /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ 1588 SPMI_VREG(LDO, HT_P600, 0, INF, HFS430, hfs430, ht_p600, 10000), 1589 SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000), 1590 SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), 1591 SPMI_VREG(BUCK, HFS430, 0, 3, HFS430, hfs430, hfs430, 10000), 1592 SPMI_VREG(BUCK, HFSMPS_510, 4, INF, HFSMPS, hfsmps, hfs430, 100000), 1593 SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000), 1594 SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000), 1595 SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000), 1596 SPMI_VREG(LDO, N600, 1, INF, LDO, ldo, nldo3, 10000), 1597 SPMI_VREG(LDO, N1200, 1, INF, LDO, ldo, nldo3, 10000), 1598 SPMI_VREG(LDO, N600_ST, 0, 0, LDO, ldo, nldo2, 10000), 1599 SPMI_VREG(LDO, N1200_ST, 0, 0, LDO, ldo, nldo2, 10000), 1600 SPMI_VREG(LDO, N600_ST, 1, INF, LDO, ldo, nldo3, 10000), 1601 SPMI_VREG(LDO, N1200_ST, 1, INF, LDO, ldo, nldo3, 10000), 1602 SPMI_VREG(LDO, P50, 0, INF, LDO, ldo, pldo, 5000), 1603 SPMI_VREG(LDO, P150, 0, INF, LDO, ldo, pldo, 10000), 1604 SPMI_VREG(LDO, P300, 0, INF, LDO, ldo, pldo, 10000), 1605 SPMI_VREG(LDO, P600, 0, INF, LDO, ldo, pldo, 10000), 1606 SPMI_VREG(LDO, P1200, 0, INF, LDO, ldo, pldo, 10000), 1607 SPMI_VREG(LDO, LN, 0, INF, LN_LDO, ln_ldo, ln_ldo, 0), 1608 SPMI_VREG(LDO, LV_P50, 0, INF, LDO, ldo, pldo, 5000), 1609 SPMI_VREG(LDO, LV_P150, 0, INF, LDO, ldo, pldo, 10000), 1610 SPMI_VREG(LDO, LV_P300, 0, INF, LDO, ldo, pldo, 10000), 1611 SPMI_VREG(LDO, LV_P600, 0, INF, LDO, ldo, pldo, 10000), 1612 SPMI_VREG(LDO, LV_P1200, 0, INF, LDO, ldo, pldo, 10000), 1613 SPMI_VREG(LDO, HT_N300_ST, 0, INF, FTSMPS426, ftsmps426, 1614 ht_nldo, 30000), 1615 SPMI_VREG(LDO, HT_N600_ST, 0, INF, FTSMPS426, ftsmps426, 1616 ht_nldo, 30000), 1617 SPMI_VREG(LDO, HT_N1200_ST, 0, INF, FTSMPS426, ftsmps426, 1618 ht_nldo, 30000), 1619 SPMI_VREG(LDO, HT_LVP150, 0, INF, FTSMPS426, ftsmps426, 1620 ht_lvpldo, 10000), 1621 SPMI_VREG(LDO, HT_LVP300, 0, INF, FTSMPS426, ftsmps426, 1622 ht_lvpldo, 10000), 1623 SPMI_VREG(LDO, L660_N300_ST, 0, INF, FTSMPS426, ftsmps426, 1624 nldo660, 10000), 1625 SPMI_VREG(LDO, L660_N600_ST, 0, INF, FTSMPS426, ftsmps426, 1626 nldo660, 10000), 1627 SPMI_VREG(LDO, L660_P50, 0, INF, FTSMPS426, ftsmps426, 1628 pldo660, 10000), 1629 SPMI_VREG(LDO, L660_P150, 0, INF, FTSMPS426, ftsmps426, 1630 pldo660, 10000), 1631 SPMI_VREG(LDO, L660_P600, 0, INF, FTSMPS426, ftsmps426, 1632 pldo660, 10000), 1633 SPMI_VREG(LDO, L660_LVP150, 0, INF, FTSMPS426, ftsmps426, 1634 ht_lvpldo, 10000), 1635 SPMI_VREG(LDO, L660_LVP600, 0, INF, FTSMPS426, ftsmps426, 1636 ht_lvpldo, 10000), 1637 SPMI_VREG_VS(LV100, 0, INF), 1638 SPMI_VREG_VS(LV300, 0, INF), 1639 SPMI_VREG_VS(MV300, 0, INF), 1640 SPMI_VREG_VS(MV500, 0, INF), 1641 SPMI_VREG_VS(HDMI, 0, INF), 1642 SPMI_VREG_VS(OTG, 0, INF), 1643 SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST, boost, boost, 0), 1644 SPMI_VREG(FTS, FTS_CTL, 0, INF, FTSMPS, ftsmps, ftsmps, 100000), 1645 SPMI_VREG(FTS, FTS2p5_CTL, 0, INF, FTSMPS, ftsmps, ftsmps2p5, 100000), 1646 SPMI_VREG(FTS, FTS426_CTL, 0, INF, FTSMPS426, ftsmps426, ftsmps426, 100000), 1647 SPMI_VREG(BOOST_BYP, BB_2A, 0, INF, BOOST_BYP, boost, boost_byp, 0), 1648 SPMI_VREG(ULT_BUCK, ULT_HF_CTL1, 0, INF, ULT_LO_SMPS, ult_lo_smps, 1649 ult_lo_smps, 100000), 1650 SPMI_VREG(ULT_BUCK, ULT_HF_CTL2, 0, INF, ULT_LO_SMPS, ult_lo_smps, 1651 ult_lo_smps, 100000), 1652 SPMI_VREG(ULT_BUCK, ULT_HF_CTL3, 0, INF, ULT_LO_SMPS, ult_lo_smps, 1653 ult_lo_smps, 100000), 1654 SPMI_VREG(ULT_BUCK, ULT_HF_CTL4, 0, INF, ULT_HO_SMPS, ult_ho_smps, 1655 ult_ho_smps, 100000), 1656 SPMI_VREG(ULT_LDO, N300_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), 1657 SPMI_VREG(ULT_LDO, N600_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), 1658 SPMI_VREG(ULT_LDO, N900_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), 1659 SPMI_VREG(ULT_LDO, N1200_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), 1660 SPMI_VREG(ULT_LDO, LV_P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1661 SPMI_VREG(ULT_LDO, LV_P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1662 SPMI_VREG(ULT_LDO, LV_P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1663 SPMI_VREG(ULT_LDO, LV_P450, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1664 SPMI_VREG(ULT_LDO, P600, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1665 SPMI_VREG(ULT_LDO, P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1666 SPMI_VREG(ULT_LDO, P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1667 SPMI_VREG(ULT_LDO, P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 5000), 1668 SPMI_VREG(LDO, LV_P150_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000), 1669 SPMI_VREG(LDO, LV_P300_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000), 1670 SPMI_VREG(LDO, LV_P600_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000), 1671 SPMI_VREG(LDO, MV_P50_510, 0, INF, LDO_510, hfsmps, pldo660, 10000), 1672 SPMI_VREG(LDO, MV_P150_510, 0, INF, LDO_510, hfsmps, pldo660, 10000), 1673 SPMI_VREG(LDO, MV_P600_510, 0, INF, LDO_510, hfsmps, pldo660, 10000), 1674 SPMI_VREG(LDO, N300_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000), 1675 SPMI_VREG(LDO, N600_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000), 1676 SPMI_VREG(LDO, N1200_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000), 1677 SPMI_VREG(FTS, FTSMPS_510, 0, INF, FTSMPS3, hfsmps, ftsmps510, 100000), 1678 }; 1679 1680 static void spmi_calculate_num_voltages(struct spmi_voltage_set_points *points) 1681 { 1682 const struct spmi_voltage_range *range = points->range; 1683 1684 for (; range < points->range + points->count; range++) 1685 points->n_voltages += range->n_voltages; 1686 } 1687 1688 static int spmi_regulator_match(struct spmi_regulator *vreg, u16 force_type) 1689 { 1690 const struct spmi_regulator_mapping *mapping; 1691 int ret, i; 1692 u32 dig_major_rev; 1693 u8 version[SPMI_COMMON_REG_SUBTYPE - SPMI_COMMON_REG_DIG_MAJOR_REV + 1]; 1694 u8 type, subtype; 1695 1696 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_DIG_MAJOR_REV, version, 1697 ARRAY_SIZE(version)); 1698 if (ret) { 1699 dev_dbg(vreg->dev, "could not read version registers\n"); 1700 return ret; 1701 } 1702 dig_major_rev = version[SPMI_COMMON_REG_DIG_MAJOR_REV 1703 - SPMI_COMMON_REG_DIG_MAJOR_REV]; 1704 1705 if (!force_type) { 1706 type = version[SPMI_COMMON_REG_TYPE - 1707 SPMI_COMMON_REG_DIG_MAJOR_REV]; 1708 subtype = version[SPMI_COMMON_REG_SUBTYPE - 1709 SPMI_COMMON_REG_DIG_MAJOR_REV]; 1710 } else { 1711 type = force_type >> 8; 1712 subtype = force_type; 1713 } 1714 1715 for (i = 0; i < ARRAY_SIZE(supported_regulators); i++) { 1716 mapping = &supported_regulators[i]; 1717 if (mapping->type == type && mapping->subtype == subtype 1718 && mapping->revision_min <= dig_major_rev 1719 && mapping->revision_max >= dig_major_rev) 1720 goto found; 1721 } 1722 1723 dev_err(vreg->dev, 1724 "unsupported regulator: name=%s type=0x%02X, subtype=0x%02X, dig major rev=0x%02X\n", 1725 vreg->desc.name, type, subtype, dig_major_rev); 1726 1727 return -ENODEV; 1728 1729 found: 1730 vreg->logical_type = mapping->logical_type; 1731 vreg->set_points = mapping->set_points; 1732 vreg->hpm_min_load = mapping->hpm_min_load; 1733 vreg->desc.ops = mapping->ops; 1734 1735 if (mapping->set_points) { 1736 if (!mapping->set_points->n_voltages) 1737 spmi_calculate_num_voltages(mapping->set_points); 1738 vreg->desc.n_voltages = mapping->set_points->n_voltages; 1739 } 1740 1741 return 0; 1742 } 1743 1744 static int spmi_regulator_init_slew_rate(struct spmi_regulator *vreg) 1745 { 1746 int ret; 1747 u8 reg = 0; 1748 int step, delay, slew_rate, step_delay; 1749 const struct spmi_voltage_range *range; 1750 1751 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1); 1752 if (ret) { 1753 dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); 1754 return ret; 1755 } 1756 1757 range = spmi_regulator_find_range(vreg); 1758 if (!range) 1759 return -EINVAL; 1760 1761 switch (vreg->logical_type) { 1762 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS: 1763 step_delay = SPMI_FTSMPS_STEP_DELAY; 1764 break; 1765 default: 1766 step_delay = SPMI_DEFAULT_STEP_DELAY; 1767 break; 1768 } 1769 1770 step = reg & SPMI_FTSMPS_STEP_CTRL_STEP_MASK; 1771 step >>= SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT; 1772 1773 delay = reg & SPMI_FTSMPS_STEP_CTRL_DELAY_MASK; 1774 delay >>= SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT; 1775 1776 /* slew_rate has units of uV/us */ 1777 slew_rate = SPMI_FTSMPS_CLOCK_RATE * range->step_uV * (1 << step); 1778 slew_rate /= 1000 * (step_delay << delay); 1779 slew_rate *= SPMI_FTSMPS_STEP_MARGIN_NUM; 1780 slew_rate /= SPMI_FTSMPS_STEP_MARGIN_DEN; 1781 1782 /* Ensure that the slew rate is greater than 0 */ 1783 vreg->slew_rate = max(slew_rate, 1); 1784 1785 return ret; 1786 } 1787 1788 static int spmi_regulator_init_slew_rate_ftsmps426(struct spmi_regulator *vreg, 1789 int clock_rate) 1790 { 1791 int ret; 1792 u8 reg = 0; 1793 int delay, slew_rate; 1794 const struct spmi_voltage_range *range = &vreg->set_points->range[0]; 1795 1796 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1); 1797 if (ret) { 1798 dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); 1799 return ret; 1800 } 1801 1802 delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK; 1803 delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT; 1804 1805 /* slew_rate has units of uV/us */ 1806 slew_rate = clock_rate * range->step_uV; 1807 slew_rate /= 1000 * (SPMI_FTSMPS426_STEP_DELAY << delay); 1808 slew_rate *= SPMI_FTSMPS426_STEP_MARGIN_NUM; 1809 slew_rate /= SPMI_FTSMPS426_STEP_MARGIN_DEN; 1810 1811 /* Ensure that the slew rate is greater than 0 */ 1812 vreg->slew_rate = max(slew_rate, 1); 1813 1814 return ret; 1815 } 1816 1817 static int spmi_regulator_init_slew_rate_hfsmps(struct spmi_regulator *vreg) 1818 { 1819 int ret; 1820 u8 reg = 0; 1821 int delay; 1822 1823 ret = spmi_vreg_read(vreg, SPMI_HFSMPS_REG_STEP_CTRL, ®, 1); 1824 if (ret) { 1825 dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); 1826 return ret; 1827 } 1828 1829 delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK; 1830 delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT; 1831 1832 vreg->slew_rate = SPMI_HFSMPS_SLEW_RATE_38p4 >> delay; 1833 1834 return ret; 1835 } 1836 1837 static int spmi_regulator_init_registers(struct spmi_regulator *vreg, 1838 const struct spmi_regulator_init_data *data) 1839 { 1840 int ret; 1841 enum spmi_regulator_logical_type type; 1842 u8 ctrl_reg[8], reg, mask; 1843 1844 type = vreg->logical_type; 1845 1846 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8); 1847 if (ret) 1848 return ret; 1849 1850 /* Set up enable pin control. */ 1851 if (!(data->pin_ctrl_enable & SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT)) { 1852 switch (type) { 1853 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS: 1854 case SPMI_REGULATOR_LOGICAL_TYPE_LDO: 1855 case SPMI_REGULATOR_LOGICAL_TYPE_VS: 1856 ctrl_reg[SPMI_COMMON_IDX_ENABLE] &= 1857 ~SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK; 1858 ctrl_reg[SPMI_COMMON_IDX_ENABLE] |= 1859 data->pin_ctrl_enable & SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK; 1860 break; 1861 default: 1862 break; 1863 } 1864 } 1865 1866 /* Set up mode pin control. */ 1867 if (!(data->pin_ctrl_hpm & SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) { 1868 switch (type) { 1869 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS: 1870 case SPMI_REGULATOR_LOGICAL_TYPE_LDO: 1871 ctrl_reg[SPMI_COMMON_IDX_MODE] &= 1872 ~SPMI_COMMON_MODE_FOLLOW_ALL_MASK; 1873 ctrl_reg[SPMI_COMMON_IDX_MODE] |= 1874 data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_ALL_MASK; 1875 break; 1876 case SPMI_REGULATOR_LOGICAL_TYPE_VS: 1877 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS: 1878 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS: 1879 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO: 1880 ctrl_reg[SPMI_COMMON_IDX_MODE] &= 1881 ~SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK; 1882 ctrl_reg[SPMI_COMMON_IDX_MODE] |= 1883 data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK; 1884 break; 1885 default: 1886 break; 1887 } 1888 } 1889 1890 /* Write back any control register values that were modified. */ 1891 ret = spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8); 1892 if (ret) 1893 return ret; 1894 1895 /* Set soft start strength and over current protection for VS. */ 1896 if (type == SPMI_REGULATOR_LOGICAL_TYPE_VS) { 1897 if (data->vs_soft_start_strength 1898 != SPMI_VS_SOFT_START_STR_HW_DEFAULT) { 1899 reg = data->vs_soft_start_strength 1900 & SPMI_VS_SOFT_START_SEL_MASK; 1901 mask = SPMI_VS_SOFT_START_SEL_MASK; 1902 return spmi_vreg_update_bits(vreg, 1903 SPMI_VS_REG_SOFT_START, 1904 reg, mask); 1905 } 1906 } 1907 1908 return 0; 1909 } 1910 1911 static void spmi_regulator_get_dt_config(struct spmi_regulator *vreg, 1912 struct device_node *node, struct spmi_regulator_init_data *data) 1913 { 1914 /* 1915 * Initialize configuration parameters to use hardware default in case 1916 * no value is specified via device tree. 1917 */ 1918 data->pin_ctrl_enable = SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT; 1919 data->pin_ctrl_hpm = SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT; 1920 data->vs_soft_start_strength = SPMI_VS_SOFT_START_STR_HW_DEFAULT; 1921 1922 /* These bindings are optional, so it is okay if they aren't found. */ 1923 of_property_read_u32(node, "qcom,ocp-max-retries", 1924 &vreg->ocp_max_retries); 1925 of_property_read_u32(node, "qcom,ocp-retry-delay", 1926 &vreg->ocp_retry_delay_ms); 1927 of_property_read_u32(node, "qcom,pin-ctrl-enable", 1928 &data->pin_ctrl_enable); 1929 of_property_read_u32(node, "qcom,pin-ctrl-hpm", &data->pin_ctrl_hpm); 1930 of_property_read_u32(node, "qcom,vs-soft-start-strength", 1931 &data->vs_soft_start_strength); 1932 } 1933 1934 static unsigned int spmi_regulator_of_map_mode(unsigned int mode) 1935 { 1936 if (mode == 1) 1937 return REGULATOR_MODE_NORMAL; 1938 if (mode == 2) 1939 return REGULATOR_MODE_FAST; 1940 1941 return REGULATOR_MODE_IDLE; 1942 } 1943 1944 static int spmi_regulator_of_parse(struct device_node *node, 1945 const struct regulator_desc *desc, 1946 struct regulator_config *config) 1947 { 1948 struct spmi_regulator_init_data data = { }; 1949 struct spmi_regulator *vreg = config->driver_data; 1950 struct device *dev = config->dev; 1951 int ret; 1952 1953 spmi_regulator_get_dt_config(vreg, node, &data); 1954 1955 if (!vreg->ocp_max_retries) 1956 vreg->ocp_max_retries = SPMI_VS_OCP_DEFAULT_MAX_RETRIES; 1957 if (!vreg->ocp_retry_delay_ms) 1958 vreg->ocp_retry_delay_ms = SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS; 1959 1960 ret = spmi_regulator_init_registers(vreg, &data); 1961 if (ret) { 1962 dev_err(dev, "common initialization failed, ret=%d\n", ret); 1963 return ret; 1964 } 1965 1966 switch (vreg->logical_type) { 1967 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS: 1968 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS: 1969 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS: 1970 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS: 1971 ret = spmi_regulator_init_slew_rate(vreg); 1972 if (ret) 1973 return ret; 1974 break; 1975 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426: 1976 ret = spmi_regulator_init_slew_rate_ftsmps426(vreg, 1977 SPMI_FTSMPS426_CLOCK_RATE); 1978 if (ret) 1979 return ret; 1980 break; 1981 case SPMI_REGULATOR_LOGICAL_TYPE_HFS430: 1982 ret = spmi_regulator_init_slew_rate_ftsmps426(vreg, 1983 SPMI_HFS430_CLOCK_RATE); 1984 if (ret) 1985 return ret; 1986 break; 1987 case SPMI_REGULATOR_LOGICAL_TYPE_HFSMPS: 1988 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3: 1989 ret = spmi_regulator_init_slew_rate_hfsmps(vreg); 1990 if (ret) 1991 return ret; 1992 break; 1993 default: 1994 break; 1995 } 1996 1997 if (vreg->logical_type != SPMI_REGULATOR_LOGICAL_TYPE_VS) 1998 vreg->ocp_irq = 0; 1999 2000 if (vreg->ocp_irq) { 2001 ret = devm_request_irq(dev, vreg->ocp_irq, 2002 spmi_regulator_vs_ocp_isr, IRQF_TRIGGER_RISING, "ocp", 2003 vreg); 2004 if (ret < 0) { 2005 dev_err(dev, "failed to request irq %d, ret=%d\n", 2006 vreg->ocp_irq, ret); 2007 return ret; 2008 } 2009 2010 ret = devm_delayed_work_autocancel(dev, &vreg->ocp_work, 2011 spmi_regulator_vs_ocp_work); 2012 if (ret) 2013 return ret; 2014 } 2015 2016 return 0; 2017 } 2018 2019 static const struct spmi_regulator_data pm6125_regulators[] = { 2020 { "s1", 0x1400, "vdd_s1" }, 2021 { "s2", 0x1700, "vdd_s2" }, 2022 { "s3", 0x1a00, "vdd_s3" }, 2023 { "s4", 0x1d00, "vdd_s4" }, 2024 { "s5", 0x2000, "vdd_s5" }, 2025 { "s6", 0x2300, "vdd_s6" }, 2026 { "s7", 0x2600, "vdd_s7" }, 2027 { "s8", 0x2900, "vdd_s8" }, 2028 { "l1", 0x4000, "vdd_l1_l7_l17_l18" }, 2029 { "l2", 0x4100, "vdd_l2_l3_l4" }, 2030 { "l3", 0x4200, "vdd_l2_l3_l4" }, 2031 { "l4", 0x4300, "vdd_l2_l3_l4" }, 2032 { "l5", 0x4400, "vdd_l5_l15_l19_l20_l21_l22" }, 2033 { "l6", 0x4500, "vdd_l6_l8" }, 2034 { "l7", 0x4600, "vdd_l1_l7_l17_l18" }, 2035 { "l8", 0x4700, "vdd_l6_l8" }, 2036 { "l9", 0x4800, "vdd_l9_l11" }, 2037 { "l10", 0x4900, "vdd_l10_l13_l14" }, 2038 { "l11", 0x4a00, "vdd_l9_l11" }, 2039 { "l12", 0x4b00, "vdd_l12_l16" }, 2040 { "l13", 0x4c00, "vdd_l10_l13_l14" }, 2041 { "l14", 0x4d00, "vdd_l10_l13_l14" }, 2042 { "l15", 0x4e00, "vdd_l5_l15_l19_l20_l21_l22" }, 2043 { "l16", 0x4f00, "vdd_l12_l16" }, 2044 { "l17", 0x5000, "vdd_l1_l7_l17_l18" }, 2045 { "l18", 0x5100, "vdd_l1_l7_l17_l18" }, 2046 { "l19", 0x5200, "vdd_l5_l15_l19_l20_l21_l22" }, 2047 { "l20", 0x5300, "vdd_l5_l15_l19_l20_l21_l22" }, 2048 { "l21", 0x5400, "vdd_l5_l15_l19_l20_l21_l22" }, 2049 { "l22", 0x5500, "vdd_l5_l15_l19_l20_l21_l22" }, 2050 { "l23", 0x5600, "vdd_l23_l24" }, 2051 { "l24", 0x5700, "vdd_l23_l24" }, 2052 }; 2053 2054 static const struct spmi_regulator_data pm660_regulators[] = { 2055 { "s1", 0x1400, "vdd_s1", }, 2056 { "s2", 0x1700, "vdd_s2", }, 2057 { "s3", 0x1a00, "vdd_s3", }, 2058 { "s4", 0x1d00, "vdd_s3", }, 2059 { "s5", 0x2000, "vdd_s5", }, 2060 { "s6", 0x2300, "vdd_s6", }, 2061 { "l1", 0x4000, "vdd_l1_l6_l7", }, 2062 { "l2", 0x4100, "vdd_l2_l3", }, 2063 { "l3", 0x4200, "vdd_l2_l3", }, 2064 /* l4 is unaccessible on PM660 */ 2065 { "l5", 0x4400, "vdd_l5", }, 2066 { "l6", 0x4500, "vdd_l1_l6_l7", }, 2067 { "l7", 0x4600, "vdd_l1_l6_l7", }, 2068 { "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2069 { "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2070 { "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2071 { "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2072 { "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2073 { "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2074 { "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2075 { "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", }, 2076 { "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", }, 2077 { "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", }, 2078 { "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", }, 2079 { "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", }, 2080 { } 2081 }; 2082 2083 static const struct spmi_regulator_data pm660l_regulators[] = { 2084 { "s1", 0x1400, "vdd_s1", }, 2085 { "s2", 0x1700, "vdd_s2", }, 2086 { "s3", 0x1a00, "vdd_s3", }, 2087 { "s4", 0x1d00, "vdd_s4", }, 2088 { "s5", 0x2000, "vdd_s5", }, 2089 { "l1", 0x4000, "vdd_l1_l9_l10", }, 2090 { "l2", 0x4100, "vdd_l2", }, 2091 { "l3", 0x4200, "vdd_l3_l5_l7_l8", }, 2092 { "l4", 0x4300, "vdd_l4_l6", }, 2093 { "l5", 0x4400, "vdd_l3_l5_l7_l8", }, 2094 { "l6", 0x4500, "vdd_l4_l6", }, 2095 { "l7", 0x4600, "vdd_l3_l5_l7_l8", }, 2096 { "l8", 0x4700, "vdd_l3_l5_l7_l8", }, 2097 { "l9", 0x4800, "vdd_l1_l9_l10", }, 2098 { "l10", 0x4900, "vdd_l1_l9_l10", }, 2099 { } 2100 }; 2101 2102 static const struct spmi_regulator_data pm8004_regulators[] = { 2103 { "s2", 0x1700, "vdd_s2", }, 2104 { "s5", 0x2000, "vdd_s5", }, 2105 { } 2106 }; 2107 2108 static const struct spmi_regulator_data pm8005_regulators[] = { 2109 { "s1", 0x1400, "vdd_s1", }, 2110 { "s2", 0x1700, "vdd_s2", }, 2111 { "s3", 0x1a00, "vdd_s3", }, 2112 { "s4", 0x1d00, "vdd_s4", }, 2113 { } 2114 }; 2115 2116 static const struct spmi_regulator_data pm8019_regulators[] = { 2117 { "s1", 0x1400, "vdd_s1", }, 2118 { "s2", 0x1700, "vdd_s2", }, 2119 { "s3", 0x1a00, "vdd_s3", }, 2120 { "s4", 0x1d00, "vdd_s4", }, 2121 { "l1", 0x4000, "vdd_l1", }, 2122 { "l2", 0x4100, "vdd_l2_l3", }, 2123 { "l3", 0x4200, "vdd_l2_l3", }, 2124 { "l4", 0x4300, "vdd_l4_l5_l6", }, 2125 { "l5", 0x4400, "vdd_l4_l5_l6", }, 2126 { "l6", 0x4500, "vdd_l4_l5_l6", }, 2127 { "l7", 0x4600, "vdd_l7_l8_l11", }, 2128 { "l8", 0x4700, "vdd_l7_l8_l11", }, 2129 { "l9", 0x4800, "vdd_l9", }, 2130 { "l10", 0x4900, "vdd_l10", }, 2131 { "l11", 0x4a00, "vdd_l7_l8_l11", }, 2132 { "l12", 0x4b00, "vdd_l12", }, 2133 { "l13", 0x4c00, "vdd_l13_l14", }, 2134 { "l14", 0x4d00, "vdd_l13_l14", }, 2135 { } 2136 }; 2137 2138 static const struct spmi_regulator_data pm8226_regulators[] = { 2139 { "s1", 0x1400, "vdd_s1", }, 2140 { "s2", 0x1700, "vdd_s2", }, 2141 { "s3", 0x1a00, "vdd_s3", }, 2142 { "s4", 0x1d00, "vdd_s4", }, 2143 { "s5", 0x2000, "vdd_s5", }, 2144 { "l1", 0x4000, "vdd_l1_l2_l4_l5", }, 2145 { "l2", 0x4100, "vdd_l1_l2_l4_l5", }, 2146 { "l3", 0x4200, "vdd_l3_l24_l26", }, 2147 { "l4", 0x4300, "vdd_l1_l2_l4_l5", }, 2148 { "l5", 0x4400, "vdd_l1_l2_l4_l5", }, 2149 { "l6", 0x4500, "vdd_l6_l7_l8_l9_l27", }, 2150 { "l7", 0x4600, "vdd_l6_l7_l8_l9_l27", }, 2151 { "l8", 0x4700, "vdd_l6_l7_l8_l9_l27", }, 2152 { "l9", 0x4800, "vdd_l6_l7_l8_l9_l27", }, 2153 { "l10", 0x4900, "vdd_l10_l11_l13", }, 2154 { "l11", 0x4a00, "vdd_l10_l11_l13", }, 2155 { "l12", 0x4b00, "vdd_l12_l14", }, 2156 { "l13", 0x4c00, "vdd_l10_l11_l13", }, 2157 { "l14", 0x4d00, "vdd_l12_l14", }, 2158 { "l15", 0x4e00, "vdd_l15_l16_l17_l18", }, 2159 { "l16", 0x4f00, "vdd_l15_l16_l17_l18", }, 2160 { "l17", 0x5000, "vdd_l15_l16_l17_l18", }, 2161 { "l18", 0x5100, "vdd_l15_l16_l17_l18", }, 2162 { "l19", 0x5200, "vdd_l19_l20_l21_l22_l23_l28", }, 2163 { "l20", 0x5300, "vdd_l19_l20_l21_l22_l23_l28", }, 2164 { "l21", 0x5400, "vdd_l19_l20_l21_l22_l23_l28", }, 2165 { "l22", 0x5500, "vdd_l19_l20_l21_l22_l23_l28", }, 2166 { "l23", 0x5600, "vdd_l19_l20_l21_l22_l23_l28", }, 2167 { "l24", 0x5700, "vdd_l3_l24_l26", }, 2168 { "l25", 0x5800, "vdd_l25", }, 2169 { "l26", 0x5900, "vdd_l3_l24_l26", }, 2170 { "l27", 0x5a00, "vdd_l6_l7_l8_l9_l27", }, 2171 { "l28", 0x5b00, "vdd_l19_l20_l21_l22_l23_l28", }, 2172 { "lvs1", 0x8000, "vdd_lvs1", }, 2173 { } 2174 }; 2175 2176 static const struct spmi_regulator_data pm8841_regulators[] = { 2177 { "s1", 0x1400, "vdd_s1", }, 2178 { "s2", 0x1700, "vdd_s2", NULL, 0x1c08 }, 2179 { "s3", 0x1a00, "vdd_s3", }, 2180 { "s4", 0x1d00, "vdd_s4", NULL, 0x1c08 }, 2181 { "s5", 0x2000, "vdd_s5", NULL, 0x1c08 }, 2182 { "s6", 0x2300, "vdd_s6", NULL, 0x1c08 }, 2183 { "s7", 0x2600, "vdd_s7", NULL, 0x1c08 }, 2184 { "s8", 0x2900, "vdd_s8", NULL, 0x1c08 }, 2185 { } 2186 }; 2187 2188 static const struct spmi_regulator_data pm8909_regulators[] = { 2189 { "s1", 0x1400, "vdd_s1", }, 2190 { "s2", 0x1700, "vdd_s2", }, 2191 { "l1", 0x4000, "vdd_l1", }, 2192 { "l2", 0x4100, "vdd_l2_l5", }, 2193 { "l3", 0x4200, "vdd_l3_l6_l10", }, 2194 { "l4", 0x4300, "vdd_l4_l7", }, 2195 { "l5", 0x4400, "vdd_l2_l5", }, 2196 { "l6", 0x4500, "vdd_l3_l6_l10", }, 2197 { "l7", 0x4600, "vdd_l4_l7", }, 2198 { "l8", 0x4700, "vdd_l8_l11_l15_l18", }, 2199 { "l9", 0x4800, "vdd_l9_l12_l14_l17", }, 2200 { "l10", 0x4900, "vdd_l3_l6_l10", }, 2201 { "l11", 0x4a00, "vdd_l8_l11_l15_l18", }, 2202 { "l12", 0x4b00, "vdd_l9_l12_l14_l17", }, 2203 { "l13", 0x4c00, "vdd_l13", }, 2204 { "l14", 0x4d00, "vdd_l9_l12_l14_l17", }, 2205 { "l15", 0x4e00, "vdd_l8_l11_l15_l18", }, 2206 { "l17", 0x5000, "vdd_l9_l12_l14_l17", }, 2207 { "l18", 0x5100, "vdd_l8_l11_l15_l18", }, 2208 { } 2209 }; 2210 2211 static const struct spmi_regulator_data pm8916_regulators[] = { 2212 { "s1", 0x1400, "vdd_s1", }, 2213 { "s2", 0x1700, "vdd_s2", }, 2214 { "s3", 0x1a00, "vdd_s3", }, 2215 { "s4", 0x1d00, "vdd_s4", }, 2216 { "l1", 0x4000, "vdd_l1_l3", }, 2217 { "l2", 0x4100, "vdd_l2", }, 2218 { "l3", 0x4200, "vdd_l1_l3", }, 2219 { "l4", 0x4300, "vdd_l4_l5_l6", }, 2220 { "l5", 0x4400, "vdd_l4_l5_l6", }, 2221 { "l6", 0x4500, "vdd_l4_l5_l6", }, 2222 { "l7", 0x4600, "vdd_l7", }, 2223 { "l8", 0x4700, "vdd_l8_l11_l14_l15_l16", }, 2224 { "l9", 0x4800, "vdd_l9_l10_l12_l13_l17_l18", }, 2225 { "l10", 0x4900, "vdd_l9_l10_l12_l13_l17_l18", }, 2226 { "l11", 0x4a00, "vdd_l8_l11_l14_l15_l16", }, 2227 { "l12", 0x4b00, "vdd_l9_l10_l12_l13_l17_l18", }, 2228 { "l13", 0x4c00, "vdd_l9_l10_l12_l13_l17_l18", }, 2229 { "l14", 0x4d00, "vdd_l8_l11_l14_l15_l16", }, 2230 { "l15", 0x4e00, "vdd_l8_l11_l14_l15_l16", }, 2231 { "l16", 0x4f00, "vdd_l8_l11_l14_l15_l16", }, 2232 { "l17", 0x5000, "vdd_l9_l10_l12_l13_l17_l18", }, 2233 { "l18", 0x5100, "vdd_l9_l10_l12_l13_l17_l18", }, 2234 { } 2235 }; 2236 2237 static const struct spmi_regulator_data pm8937_regulators[] = { 2238 { "s1", 0x1400, "vdd_s1", }, 2239 { "s2", 0x1700, "vdd_s2", }, 2240 { "s3", 0x1a00, "vdd_s3", }, 2241 { "s4", 0x1d00, "vdd_s4", }, 2242 { "s5", 0x2000, "vdd_s5", }, 2243 { "s6", 0x2300, "vdd_s6", }, 2244 { "l1", 0x4000, "vdd_l1_l19", }, 2245 { "l2", 0x4100, "vdd_l2_l23", }, 2246 { "l3", 0x4200, "vdd_l3", }, 2247 { "l4", 0x4300, "vdd_l4_l5_l6_l7_l16", }, 2248 { "l5", 0x4400, "vdd_l4_l5_l6_l7_l16", }, 2249 { "l6", 0x4500, "vdd_l4_l5_l6_l7_l16", }, 2250 { "l7", 0x4600, "vdd_l4_l5_l6_l7_l16", }, 2251 { "l8", 0x4700, "vdd_l8_l11_l12_l17_l22", }, 2252 { "l9", 0x4800, "vdd_l9_l10_l13_l14_l15_l18", }, 2253 { "l10", 0x4900, "vdd_l9_l10_l13_l14_l15_l18", }, 2254 { "l11", 0x4a00, "vdd_l8_l11_l12_l17_l22", }, 2255 { "l12", 0x4b00, "vdd_l8_l11_l12_l17_l22", }, 2256 { "l13", 0x4c00, "vdd_l9_l10_l13_l14_l15_l18", }, 2257 { "l14", 0x4d00, "vdd_l9_l10_l13_l14_l15_l18", }, 2258 { "l15", 0x4e00, "vdd_l9_l10_l13_l14_l15_l18", }, 2259 { "l16", 0x4f00, "vdd_l4_l5_l6_l7_l16", }, 2260 { "l17", 0x5000, "vdd_l8_l11_l12_l17_l22", }, 2261 { "l18", 0x5100, "vdd_l9_l10_l13_l14_l15_l18", }, 2262 { "l19", 0x5200, "vdd_l1_l19", }, 2263 { "l20", 0x5300, "vdd_l20_l21", }, 2264 { "l21", 0x5400, "vdd_l21_l21", }, 2265 { "l22", 0x5500, "vdd_l8_l11_l12_l17_l22", }, 2266 { "l23", 0x5600, "vdd_l2_l23", }, 2267 { } 2268 }; 2269 2270 static const struct spmi_regulator_data pm8941_regulators[] = { 2271 { "s1", 0x1400, "vdd_s1", }, 2272 { "s2", 0x1700, "vdd_s2", }, 2273 { "s3", 0x1a00, "vdd_s3", }, 2274 { "s4", 0xa000, }, 2275 { "l1", 0x4000, "vdd_l1_l3", }, 2276 { "l2", 0x4100, "vdd_l2_lvs_1_2_3", }, 2277 { "l3", 0x4200, "vdd_l1_l3", }, 2278 { "l4", 0x4300, "vdd_l4_l11", }, 2279 { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 }, 2280 { "l6", 0x4500, "vdd_l6_l12_l14_l15", }, 2281 { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 }, 2282 { "l8", 0x4700, "vdd_l8_l16_l18_19", }, 2283 { "l9", 0x4800, "vdd_l9_l10_l17_l22", }, 2284 { "l10", 0x4900, "vdd_l9_l10_l17_l22", }, 2285 { "l11", 0x4a00, "vdd_l4_l11", }, 2286 { "l12", 0x4b00, "vdd_l6_l12_l14_l15", }, 2287 { "l13", 0x4c00, "vdd_l13_l20_l23_l24", }, 2288 { "l14", 0x4d00, "vdd_l6_l12_l14_l15", }, 2289 { "l15", 0x4e00, "vdd_l6_l12_l14_l15", }, 2290 { "l16", 0x4f00, "vdd_l8_l16_l18_19", }, 2291 { "l17", 0x5000, "vdd_l9_l10_l17_l22", }, 2292 { "l18", 0x5100, "vdd_l8_l16_l18_19", }, 2293 { "l19", 0x5200, "vdd_l8_l16_l18_19", }, 2294 { "l20", 0x5300, "vdd_l13_l20_l23_l24", }, 2295 { "l21", 0x5400, "vdd_l21", }, 2296 { "l22", 0x5500, "vdd_l9_l10_l17_l22", }, 2297 { "l23", 0x5600, "vdd_l13_l20_l23_l24", }, 2298 { "l24", 0x5700, "vdd_l13_l20_l23_l24", }, 2299 { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", }, 2300 { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", }, 2301 { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", }, 2302 { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", }, 2303 { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", }, 2304 { } 2305 }; 2306 2307 static const struct spmi_regulator_data pm8950_regulators[] = { 2308 { "s1", 0x1400, "vdd_s1", }, 2309 { "s2", 0x1700, "vdd_s2", }, 2310 { "s3", 0x1a00, "vdd_s3", }, 2311 { "s4", 0x1d00, "vdd_s4", }, 2312 { "s5", 0x2000, "vdd_s5", }, 2313 { "s6", 0x2300, "vdd_s6", }, 2314 { "l1", 0x4000, "vdd_l1_l19", }, 2315 { "l2", 0x4100, "vdd_l2_l23", }, 2316 { "l3", 0x4200, "vdd_l3", }, 2317 { "l4", 0x4300, "vdd_l4_l5_l6_l7_l16", }, 2318 { "l5", 0x4400, "vdd_l4_l5_l6_l7_l16", }, 2319 { "l6", 0x4500, "vdd_l4_l5_l6_l7_l16", }, 2320 { "l7", 0x4600, "vdd_l4_l5_l6_l7_l16", }, 2321 { "l8", 0x4700, "vdd_l8_l11_l12_l17_l22", }, 2322 { "l9", 0x4800, "vdd_l9_l10_l13_l14_l15_l18", }, 2323 { "l10", 0x4900, "vdd_l9_l10_l13_l14_l15_l18", }, 2324 { "l11", 0x4a00, "vdd_l8_l11_l12_l17_l22", }, 2325 { "l12", 0x4b00, "vdd_l8_l11_l12_l17_l22", }, 2326 { "l13", 0x4c00, "vdd_l9_l10_l13_l14_l15_l18", }, 2327 { "l14", 0x4d00, "vdd_l9_l10_l13_l14_l15_l18", }, 2328 { "l15", 0x4e00, "vdd_l9_l10_l13_l14_l15_l18", }, 2329 { "l16", 0x4f00, "vdd_l4_l5_l6_l7_l16", }, 2330 { "l17", 0x5000, "vdd_l8_l11_l12_l17_l22", }, 2331 { "l18", 0x5100, "vdd_l9_l10_l13_l14_l15_l18", }, 2332 { "l19", 0x5200, "vdd_l1_l19", }, 2333 { "l20", 0x5300, "vdd_l20", }, 2334 { "l21", 0x5400, "vdd_l21", }, 2335 { "l22", 0x5500, "vdd_l8_l11_l12_l17_l22", }, 2336 { "l23", 0x5600, "vdd_l2_l23", }, 2337 { } 2338 }; 2339 2340 static const struct spmi_regulator_data pm8994_regulators[] = { 2341 { "s1", 0x1400, "vdd_s1", }, 2342 { "s2", 0x1700, "vdd_s2", }, 2343 { "s3", 0x1a00, "vdd_s3", }, 2344 { "s4", 0x1d00, "vdd_s4", }, 2345 { "s5", 0x2000, "vdd_s5", }, 2346 { "s6", 0x2300, "vdd_s6", }, 2347 { "s7", 0x2600, "vdd_s7", }, 2348 { "s8", 0x2900, "vdd_s8", }, 2349 { "s9", 0x2c00, "vdd_s9", }, 2350 { "s10", 0x2f00, "vdd_s10", }, 2351 { "s11", 0x3200, "vdd_s11", }, 2352 { "s12", 0x3500, "vdd_s12", }, 2353 { "l1", 0x4000, "vdd_l1", }, 2354 { "l2", 0x4100, "vdd_l2_l26_l28", }, 2355 { "l3", 0x4200, "vdd_l3_l11", }, 2356 { "l4", 0x4300, "vdd_l4_l27_l31", }, 2357 { "l5", 0x4400, "vdd_l5_l7", }, 2358 { "l6", 0x4500, "vdd_l6_l12_l32", }, 2359 { "l7", 0x4600, "vdd_l5_l7", }, 2360 { "l8", 0x4700, "vdd_l8_l16_l30", }, 2361 { "l9", 0x4800, "vdd_l9_l10_l18_l22", }, 2362 { "l10", 0x4900, "vdd_l9_l10_l18_l22", }, 2363 { "l11", 0x4a00, "vdd_l3_l11", }, 2364 { "l12", 0x4b00, "vdd_l6_l12_l32", }, 2365 { "l13", 0x4c00, "vdd_l13_l19_l23_l24", }, 2366 { "l14", 0x4d00, "vdd_l14_l15", }, 2367 { "l15", 0x4e00, "vdd_l14_l15", }, 2368 { "l16", 0x4f00, "vdd_l8_l16_l30", }, 2369 { "l17", 0x5000, "vdd_l17_l29", }, 2370 { "l18", 0x5100, "vdd_l9_l10_l18_l22", }, 2371 { "l19", 0x5200, "vdd_l13_l19_l23_l24", }, 2372 { "l20", 0x5300, "vdd_l20_l21", }, 2373 { "l21", 0x5400, "vdd_l20_l21", }, 2374 { "l22", 0x5500, "vdd_l9_l10_l18_l22", }, 2375 { "l23", 0x5600, "vdd_l13_l19_l23_l24", }, 2376 { "l24", 0x5700, "vdd_l13_l19_l23_l24", }, 2377 { "l25", 0x5800, "vdd_l25", }, 2378 { "l26", 0x5900, "vdd_l2_l26_l28", }, 2379 { "l27", 0x5a00, "vdd_l4_l27_l31", }, 2380 { "l28", 0x5b00, "vdd_l2_l26_l28", }, 2381 { "l29", 0x5c00, "vdd_l17_l29", }, 2382 { "l30", 0x5d00, "vdd_l8_l16_l30", }, 2383 { "l31", 0x5e00, "vdd_l4_l27_l31", }, 2384 { "l32", 0x5f00, "vdd_l6_l12_l32", }, 2385 { "lvs1", 0x8000, "vdd_lvs_1_2", }, 2386 { "lvs2", 0x8100, "vdd_lvs_1_2", }, 2387 { } 2388 }; 2389 2390 static const struct spmi_regulator_data pma8084_regulators[] = { 2391 { "s1", 0x1400, "vdd_s1", }, 2392 { "s2", 0x1700, "vdd_s2", }, 2393 { "s3", 0x1a00, "vdd_s3", }, 2394 { "s4", 0x1d00, "vdd_s4", }, 2395 { "s5", 0x2000, "vdd_s5", }, 2396 { "s6", 0x2300, "vdd_s6", }, 2397 { "s7", 0x2600, "vdd_s7", }, 2398 { "s8", 0x2900, "vdd_s8", }, 2399 { "s9", 0x2c00, "vdd_s9", }, 2400 { "s10", 0x2f00, "vdd_s10", }, 2401 { "s11", 0x3200, "vdd_s11", }, 2402 { "s12", 0x3500, "vdd_s12", }, 2403 { "l1", 0x4000, "vdd_l1_l11", }, 2404 { "l2", 0x4100, "vdd_l2_l3_l4_l27", }, 2405 { "l3", 0x4200, "vdd_l2_l3_l4_l27", }, 2406 { "l4", 0x4300, "vdd_l2_l3_l4_l27", }, 2407 { "l5", 0x4400, "vdd_l5_l7", }, 2408 { "l6", 0x4500, "vdd_l6_l12_l14_l15_l26", }, 2409 { "l7", 0x4600, "vdd_l5_l7", }, 2410 { "l8", 0x4700, "vdd_l8", }, 2411 { "l9", 0x4800, "vdd_l9_l10_l13_l20_l23_l24", }, 2412 { "l10", 0x4900, "vdd_l9_l10_l13_l20_l23_l24", }, 2413 { "l11", 0x4a00, "vdd_l1_l11", }, 2414 { "l12", 0x4b00, "vdd_l6_l12_l14_l15_l26", }, 2415 { "l13", 0x4c00, "vdd_l9_l10_l13_l20_l23_l24", }, 2416 { "l14", 0x4d00, "vdd_l6_l12_l14_l15_l26", }, 2417 { "l15", 0x4e00, "vdd_l6_l12_l14_l15_l26", }, 2418 { "l16", 0x4f00, "vdd_l16_l25", }, 2419 { "l17", 0x5000, "vdd_l17", }, 2420 { "l18", 0x5100, "vdd_l18", }, 2421 { "l19", 0x5200, "vdd_l19", }, 2422 { "l20", 0x5300, "vdd_l9_l10_l13_l20_l23_l24", }, 2423 { "l21", 0x5400, "vdd_l21", }, 2424 { "l22", 0x5500, "vdd_l22", }, 2425 { "l23", 0x5600, "vdd_l9_l10_l13_l20_l23_l24", }, 2426 { "l24", 0x5700, "vdd_l9_l10_l13_l20_l23_l24", }, 2427 { "l25", 0x5800, "vdd_l16_l25", }, 2428 { "l26", 0x5900, "vdd_l6_l12_l14_l15_l26", }, 2429 { "l27", 0x5a00, "vdd_l2_l3_l4_l27", }, 2430 { "lvs1", 0x8000, "vdd_lvs1_2", }, 2431 { "lvs2", 0x8100, "vdd_lvs1_2", }, 2432 { "lvs3", 0x8200, "vdd_lvs3_4", }, 2433 { "lvs4", 0x8300, "vdd_lvs3_4", }, 2434 { "5vs1", 0x8400, "vdd_5vs1", }, 2435 { } 2436 }; 2437 2438 static const struct spmi_regulator_data pmi8994_regulators[] = { 2439 { "s1", 0x1400, "vdd_s1", }, 2440 { "s2", 0x1700, "vdd_s2", }, 2441 { "s3", 0x1a00, "vdd_s3", }, 2442 { "l1", 0x4000, "vdd_l1", }, 2443 { } 2444 }; 2445 2446 static const struct spmi_regulator_data pmp8074_regulators[] = { 2447 { "s1", 0x1400, "vdd_s1"}, 2448 { "s2", 0x1700, "vdd_s2"}, 2449 { "s3", 0x1a00, "vdd_s3"}, 2450 { "s4", 0x1d00, "vdd_s4"}, 2451 { "s5", 0x2000, "vdd_s5"}, 2452 { "l1", 0x4000, "vdd_l1_l2"}, 2453 { "l2", 0x4100, "vdd_l1_l2"}, 2454 { "l3", 0x4200, "vdd_l3_l8"}, 2455 { "l4", 0x4300, "vdd_l4"}, 2456 { "l5", 0x4400, "vdd_l5_l6_l15"}, 2457 { "l6", 0x4500, "vdd_l5_l6_l15"}, 2458 { "l7", 0x4600, "vdd_l7"}, 2459 { "l8", 0x4700, "vdd_l3_l8"}, 2460 { "l9", 0x4800, "vdd_l9"}, 2461 /* l10 is currently unsupported HT_P50 */ 2462 { "l11", 0x4a00, "vdd_l10_l11_l12_l13"}, 2463 { "l12", 0x4b00, "vdd_l10_l11_l12_l13"}, 2464 { "l13", 0x4c00, "vdd_l10_l11_l12_l13"}, 2465 { } 2466 }; 2467 2468 static const struct spmi_regulator_data pms405_regulators[] = { 2469 { "s3", 0x1a00, "vdd_s3"}, 2470 { } 2471 }; 2472 2473 static const struct of_device_id qcom_spmi_regulator_match[] = { 2474 { .compatible = "qcom,pm6125-regulators", .data = &pm6125_regulators }, 2475 { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators }, 2476 { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators }, 2477 { .compatible = "qcom,pm8004-regulators", .data = &pm8004_regulators }, 2478 { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators }, 2479 { .compatible = "qcom,pm8019-regulators", .data = &pm8019_regulators }, 2480 { .compatible = "qcom,pm8226-regulators", .data = &pm8226_regulators }, 2481 { .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators }, 2482 { .compatible = "qcom,pm8909-regulators", .data = &pm8909_regulators }, 2483 { .compatible = "qcom,pm8916-regulators", .data = &pm8916_regulators }, 2484 { .compatible = "qcom,pm8937-regulators", .data = &pm8937_regulators }, 2485 { .compatible = "qcom,pm8941-regulators", .data = &pm8941_regulators }, 2486 { .compatible = "qcom,pm8950-regulators", .data = &pm8950_regulators }, 2487 { .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators }, 2488 { .compatible = "qcom,pma8084-regulators", .data = &pma8084_regulators }, 2489 { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators }, 2490 { .compatible = "qcom,pmp8074-regulators", .data = &pmp8074_regulators }, 2491 { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators }, 2492 { } 2493 }; 2494 MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match); 2495 2496 static int qcom_spmi_regulator_probe(struct platform_device *pdev) 2497 { 2498 const struct spmi_regulator_data *reg; 2499 const struct spmi_voltage_range *range; 2500 struct regulator_config config = { }; 2501 struct regulator_dev *rdev; 2502 struct spmi_regulator *vreg; 2503 struct regmap *regmap; 2504 const char *name; 2505 struct device *dev = &pdev->dev; 2506 struct device_node *node = pdev->dev.of_node; 2507 struct device_node *syscon, *reg_node; 2508 struct property *reg_prop; 2509 int ret, lenp; 2510 struct list_head *vreg_list; 2511 2512 vreg_list = devm_kzalloc(dev, sizeof(*vreg_list), GFP_KERNEL); 2513 if (!vreg_list) 2514 return -ENOMEM; 2515 INIT_LIST_HEAD(vreg_list); 2516 platform_set_drvdata(pdev, vreg_list); 2517 2518 regmap = dev_get_regmap(dev->parent, NULL); 2519 if (!regmap) 2520 return -ENODEV; 2521 2522 reg = device_get_match_data(&pdev->dev); 2523 if (!reg) 2524 return -ENODEV; 2525 2526 syscon = of_parse_phandle(node, "qcom,saw-reg", 0); 2527 if (syscon) { 2528 saw_regmap = syscon_node_to_regmap(syscon); 2529 of_node_put(syscon); 2530 if (IS_ERR(saw_regmap)) 2531 dev_err(dev, "ERROR reading SAW regmap\n"); 2532 } 2533 2534 for (; reg->name; reg++) { 2535 2536 if (saw_regmap) { 2537 reg_node = of_get_child_by_name(node, reg->name); 2538 reg_prop = of_find_property(reg_node, "qcom,saw-slave", 2539 &lenp); 2540 of_node_put(reg_node); 2541 if (reg_prop) 2542 continue; 2543 } 2544 2545 vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); 2546 if (!vreg) 2547 return -ENOMEM; 2548 2549 vreg->dev = dev; 2550 vreg->base = reg->base; 2551 vreg->regmap = regmap; 2552 if (reg->ocp) { 2553 vreg->ocp_irq = platform_get_irq_byname(pdev, reg->ocp); 2554 if (vreg->ocp_irq < 0) 2555 return vreg->ocp_irq; 2556 } 2557 vreg->desc.id = -1; 2558 vreg->desc.owner = THIS_MODULE; 2559 vreg->desc.type = REGULATOR_VOLTAGE; 2560 vreg->desc.enable_reg = reg->base + SPMI_COMMON_REG_ENABLE; 2561 vreg->desc.enable_mask = SPMI_COMMON_ENABLE_MASK; 2562 vreg->desc.enable_val = SPMI_COMMON_ENABLE; 2563 vreg->desc.name = name = reg->name; 2564 vreg->desc.supply_name = reg->supply; 2565 vreg->desc.of_match = reg->name; 2566 vreg->desc.of_parse_cb = spmi_regulator_of_parse; 2567 vreg->desc.of_map_mode = spmi_regulator_of_map_mode; 2568 2569 ret = spmi_regulator_match(vreg, reg->force_type); 2570 if (ret) 2571 continue; 2572 2573 if (saw_regmap) { 2574 reg_node = of_get_child_by_name(node, reg->name); 2575 if (of_property_read_bool(reg_node, "qcom,saw-leader")) { 2576 spmi_saw_ops = *(vreg->desc.ops); 2577 spmi_saw_ops.set_voltage_sel = 2578 spmi_regulator_saw_set_voltage; 2579 vreg->desc.ops = &spmi_saw_ops; 2580 } 2581 of_node_put(reg_node); 2582 } 2583 2584 if (vreg->set_points && vreg->set_points->count == 1) { 2585 /* since there is only one range */ 2586 range = vreg->set_points->range; 2587 vreg->desc.uV_step = range->step_uV; 2588 } 2589 2590 config.dev = dev; 2591 config.driver_data = vreg; 2592 config.regmap = regmap; 2593 rdev = devm_regulator_register(dev, &vreg->desc, &config); 2594 if (IS_ERR(rdev)) { 2595 dev_err(dev, "failed to register %s\n", name); 2596 return PTR_ERR(rdev); 2597 } 2598 2599 INIT_LIST_HEAD(&vreg->node); 2600 list_add(&vreg->node, vreg_list); 2601 } 2602 2603 return 0; 2604 } 2605 2606 static struct platform_driver qcom_spmi_regulator_driver = { 2607 .driver = { 2608 .name = "qcom-spmi-regulator", 2609 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2610 .of_match_table = qcom_spmi_regulator_match, 2611 }, 2612 .probe = qcom_spmi_regulator_probe, 2613 }; 2614 module_platform_driver(qcom_spmi_regulator_driver); 2615 2616 MODULE_DESCRIPTION("Qualcomm SPMI PMIC regulator driver"); 2617 MODULE_LICENSE("GPL v2"); 2618 MODULE_ALIAS("platform:qcom-spmi-regulator"); 2619